`
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`__________________
`
`SEOUL SEMICONDUCTOR CO., LTD., and
`SEOUL SEMICONDUCTOR, INC.
`Petitioners
`
`v.
`
`DOCUMENT SECURITY SYSTEMS, INC.
`Patent Owner
`
`__________________
`
`Case No. IPR2018-00333
`U.S. Patent No. 7,256,486
`__________________
`
`
`
`PETITION FOR INTER PARTES REVIEW OF
`
`U. S. PATENT NO. 7,256,486 UNDER
`
`35 U.S.C. §§ 311-319 AND 37 C.F.R. § 42.100 ET SEQ.
`
`
`
`
`
`Table of Contents
`INTRODUCTION ........................................................................................... 1
`I.
`REQUIREMENTS FOR AN INTER PARTES REVIEW PETITION ............ 1
`II.
`A. GROUNDS FOR STANDING (37 C.F.R. § 42.104(A)) ....................................... 1
`B.
`NOTICE OF LEAD AND BACKUP COUNSEL AND SERVICE INFORMATION
`(37 C.F.R. § 42.8(B)(3)) ................................................................................ 1
`NOTICE OF REAL-PARTIES-IN-INTEREST (37 C.F.R. § 42.8(B)(1)) ................ 2
`C.
`D. NOTICE OF RELATED MATTERS (37 C.F.R. § 42.8(B)(2)) .............................. 2
`FEE FOR INTER PARTES REVIEW ..................................................................... 2
`E.
`F.
`PROOF OF SERVICE ........................................................................................ 2
`III.
`IDENTIFICATION OF CLAIMS BEING CHALLENGED
`(§ 42.104(B)) ................................................................................................... 3
`IV. THE PURPORTED INVENTION .................................................................. 3
`A.
`THE BACKGROUND OF THE INVENTION ......................................................... 3
`B.
`THE PURPORTED SOLUTION........................................................................... 4
`V.
`SUMMARY OF THE RELEVANT PROSECUTION HISTORY ................ 6
`VI. CLAIM CONSTRUCTION ............................................................................ 8
`A.
`“METALLIZED . . . SURFACE” .......................................................................... 8
`B.
`“THE METALLIZED TOP MAJOR SURFACE COMPRISES A FIRST ELECTRODE .
`. . AND THE METALLIZED BOTTOM MAJOR SURFACE COMPRISES A SECOND
`ELECTRODE” ................................................................................................ 11
`VII. PERSON HAVING ORDINARY SKILL IN THE ART ............................. 13
`VIII. BRIEF DESCRIPTION OF THE PRIOR ART ............................................ 14
`A.
`JAPANESE PATENT APPLICATION PUBLICATION NO. 2003-17754 (ROHM) .. 14
`B.
`JAPANESE PATENT APPLICATION PUBLICATION NO. 2001-352102
`(MATSUSHITA) .............................................................................................. 15
`U.S. PATENT NO. 5,376,580 TO KISH ET AL. (“KISH”) ................................. 17
`
`
`C.
`
`
`
`D. U.S. PATENT NO. 5,523,589 TO EDMOND ET AL. (“EDMOND 589”) ............. 18
`IX.
`PRECISE REASONS FOR THE RELIEF REQUESTED ........................... 19
`A. GROUND 1: CLAIMS 1-3 ARE RENDERED OBVIOUS BY ROHM ALONE OR
`IN VIEW OF KISH .......................................................................................... 19
`Independent Claim 1 ............................................................................... 19
`Dependent Claim 2 ................................................................................. 28
`Dependent Claim 3 ................................................................................. 32
`GROUND 2: CLAIMS 1-3 ARE RENDERED OBVIOUS BY MATSUSHITA IN
`VIEW OF EDMOND 589 ................................................................................. 33
`Independent Claim 1 ............................................................................... 33
`Dependent Claim 2 ................................................................................. 43
`Dependent Claim 3 ................................................................................. 50
`CONCLUSION .............................................................................................. 51
`
`1.
`2.
`3.
`B.
`
`1.
`2.
`3.
`
`X.
`
`CERTIFICATE OF SERVICE
`
`CERTIFICATE OF COMPLIANCE WITH 37 C.F. R. § 42.24
`
`ii
`
`
`
`PETITIONER’S EXHIBIT LIST
`
`Exhibit Description
`
`1001
`
`1002
`
` U.S. Patent No. 7,256,486 (“’486 patent”)
`
`Prosecution History of U.S. Patent No. 7,256,486 (“Prosecution
`History”)
`
`1003
`
`Declaration of Michael Pecht, Ph.D. (“Pecht”)
`
`1004 Modern Dictionary of Electronics (7th ed. 1999)) pg. 239 and 467
`
`1005 Microchip Fabrication (4th ed. 2000) pg. 396
`
`1006
`
`Pecht et al. “Plastic Encapsulated Microelectronics” (1995) pg. 459
`
`1007 Meriam Webster’s Collegiate Dictionary (10th ed. 1997) pg. 730
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`Japanese Patent Application Publication No. 2003-17754, English
`translation of Japanese Patent Application Publication No. 2003-17754
`and Translator Declaration (Rohm)
`
`Japanese Patent Application Publication No. 2001-352102 English
`translation of Japanese Patent Application Publication No. 2001-
`352102 and Translator Declaration (Matsushita)
`
`U.S. Patent No. 5,376,580 (“Kish”)
`
`U.S. Patent No. 5,523,589 (“Edmond 589)
`
`U.S. Patent No. 6,791,119 (”Slater”)
`
`U.S. Patent No. 5,416,342 (“Edmond 342”)
`
`CV of Pecht
`
`Pecht, M., R. Agarwal, P. McCluskey, T. Dishongh, S. Javadpour, and
`R. Mahajan, Electronic Packaging Materials and their Properties,
`CRC Press, Boca Raton, FL, 1999 pg. 37 (“Electronic Packaging”)
`
`iii
`
`
`
`I.
`
`INTRODUCTION
`
`On behalf of Seoul Semiconductor Co., Ltd. and Seoul Semiconductor, Inc.
`
`(collectively “Petitioners”) and in accordance with 35 U.S.C. § 311 and 37 C.F.R.
`
`§ 42.100, inter partes review of claims 1-3 of United States Patent No. 7,256,486 to
`
`Lee et al., entitled “Packaging Device For Semiconductor Die, Semiconductor
`
`Device Incorporating Same And Method Of Making Same” (hereinafter “the ’486
`
`patent”) is requested. This Petition establishes that Petitioners have a reasonable
`
`likelihood of prevailing with respect to at least one of claims 1-3. A copy of the ’486
`
`patent is provided as Ex. 1001.
`
`II.
`
`REQUIREMENTS FOR AN INTER PARTES REVIEW PETITION
`
`A. Grounds for Standing (37 C.F.R. § 42.104(a))
`
`Petitioners certify that the ’486 patent is available for inter partes review and
`
`that Petitioners are not barred or estopped from requesting an inter partes review
`
`challenging claims 1-3 of the ’486 patent on the grounds identified herein.
`
`B. Notice of Lead and Backup Counsel and Service Information (37
`C.F.R. § 42.8(b)(3))
`
`Lead Counsel:
`Michael Eisenberg (Reg. No. 50,643)
`michael.eisenberg@hklaw.com
`31 West 52nd Street
`New York, NY 10019
`
`1
`
`
`
`Backup Counsel:
`Charles H. Sanders (Reg. No. 47,053)
`charles.sanders@lw.com
`Latham & Watkins LLP
`200 Clarendon Street
`Boston, MA 02116
`
`Jonathan M. Strang (Reg. No. 61,724)
`jonathan.strang@lw.com
`Latham & Watkins LLP
`555 Eleventh Street, NW, Ste. 1000
`Washington, DC 20004-1304
`
`C. Notice of Real-Parties-in-Interest (37 C.F.R. § 42.8(b)(1))
`
`Seoul Semiconductor Co., Ltd. and Seoul Semiconductor, Inc.
`
`D. Notice of Related Matters (37 C.F.R. § 42.8(b)(2))
`
`Based on the information known to Petitioners, the following matters are
`
`related: Document Security Systems, Inc. v. Seoul Semiconductor Co. Ltd., No. 8:17-
`
`cv-00981 (C.D. Cal.); Document Security Systems, Inc. v. Cree, Inc., No. 2:17-cv-
`
`04263 (C.D. Cal.); Document Security Systems, Inc. v. Everlight Electronics Co.,
`
`Ltd. et al., No. 2:17-cv-04273 (C.D. Cal.); Document Security Systems, Inc. v.
`
`OSRAM GmbH, No. 2:17-cv-05184 (C.D. Cal.); and Document Security Systems,
`
`Inc. v. Lite-On, Inc., No. 2:17-cv-06050 (C.D. Cal.).
`
`E.
`
`Fee for Inter Partes Review
`
`The Director is authorized to charge any extra fee specified by 37 CFR
`
`§ 42.15(a) to Deposit Account No. 50-2324.
`
`Proof of Service
`
`F.
`
`
`2
`
`
`
`Proof of service of this petition is provided in Attachment A.
`
`III.
`
`IDENTIFICATION OF CLAIMS BEING CHALLENGED
`(§ 42.104(B))
`• Ground 1: Claims 1-3 Are Rendered Obvious by Rohm alone or in
`
`view of Kish; and
`
`• Ground 2: Claims 1-3 Are Rendered Obvious by Matsushita in view
`
`of Edmond 589.
`
`IV. THE PURPORTED INVENTION
`
`A. The Background of the Invention
`
`The ’486 patent has an earliest U.S. filing date of June 27, 2003. The patent
`
`begins with a description of “conventional” semiconductor packaging technology
`
`based on a metal lead frame. Ex. 1001 (’486 patent) 1:17-20. The ’486 patent
`
`describes that conventional technology as follows:
`
`A metallization layer of aluminum located on the bottom surface of the
`semiconductor die is bonded to a conductive surface that forms part of
`the lead frame to attach and electrically connect the die to the lead
`frame. Additionally, electrical connections are made between bonding
`pads on the top surface of the die and other leads of the lead frame to
`provide additional electrical connections to the die. The lead frame and
`semiconductor die are then encapsulated to complete the semiconductor
`device. The packaging device protects the semiconductor die and
`provides electrical and mechanical connections to the die that are
`compatible with conventional printed circuit board assembly processes.
`
`
`
`3
`
`
`
`Id. at 1:20-32. The bonding described in the above passage is described as “a silver
`
`epoxy adhesive that cures at a relatively low temperature, typically about 120° C.”
`
`Id. at 1:35-36. According to the ’486 patent, this conventional packaging technology
`
`possessed insufficient packing density. Id. at 1:39-45. In other words, the final
`
`packaged products were too large.
`
`As an alternative to the conventional aluminum metallization, the ’486 patent
`
`explains that “[r]ecently, semiconductor die having a substrate surface metallization
`
`layer of a gold-tin alloy (80% Au:20% Sn approximately) have been introduced in
`
`light-emitting devices.” The use of this “gold-tin eutectic” requires higher
`
`temperature processing because it “has a melting point of about 280° C.” This prior
`
`art technology was identified as having its own shortcomings, in that the high
`
`temperature required was “incompatible with the materials of many conventional
`
`packaging devices.” Id. at 1:61-63.
`
`B.
`
`The Purported Solution
`
`The link between the prior art shortcomings and the purported invention is a
`
`bit tenuous. In particular, nothing in the detailed description nor the claims limit the
`
`purported invention to specific package materials. Instead, the focus of the
`
`disclosure is on providing a planar substrate 110 (colored red) having four metal
`
`layers regions thereon. Figures 1A and 1B (reproduced respectively top and bottom
`
`below) show the substrate, the mounting pad 130 (colored green), the bonding pad
`
`
`
`4
`
`
`
`132 (colored green), the connecting pad 140 (colored orange) and the connecting pad
`
`142 (colored orange). Ex. 1001 (’486 patent) 3:36-41. The mounting pad is used to
`
`mount and electrically connect to the bottom surface of a semiconductor device (e.g.,
`
`an LED). Id. at 5:10-12. The bonding pad 132 is used to electrically connect to the
`
`top surface of the semiconductor device. Id. at 5:15-17. In addition, interconnecting
`
`elements 120 and 122 (colored purple) are provided to electrically connect the
`
`mounting pad and the bonding pad to the connecting pads 140 and 142 (colored
`
`orange) on the bottom of the substrate. Id. at 3:58-67.
`
`
`
`5
`
`
`
`
`
`V.
`
`SUMMARY OF THE RELEVANT PROSECUTION HISTORY
`
`A copy of the file history as accessed from PAIR is provided as Exhibit 1002.
`
`The ’486 patent as originally filed included 20 claims. All of the originally
`
`filed claims were cancelled during prosecution. Original claim 1 provided:
`
`1. A packaging device for semiconductor die, the packaging device
`comprising:
`a substantially planar substrate having opposed major surfaces;
`a conductive mounting pad located on one of the major
`surfaces;
`a conductive connecting pad located on the other of the major
`surfaces; and
`a conductive interconnecting element extending through the
`substrate and electrically interconnecting the mounting pad and the
`connecting pad.
`
`Id. at 249.
`
`On August 23, 2004, the Examiner rejected all of the pending claims based on
`
`anticipation and/or obviousness. Id. at 219-24. In particular, the Examiner rejected a
`
`number of claims as anticipated based on U.S. Patent No. 5,986,885 to Wyland
`
`(“Wyland”). Id. at 219. In response to the rejection, the applicants amended claim 1
`
`and sought to distinguish between a “mounting pad” as recited and “first circuitry
`
`metallizations 61 by flip-chip bonding” as allegedly disclosed in Wyland. Id. at 204.
`
`Following a long series of rejections and amendments, the applicants
`
`submitted a final amendment to application claim 22, which became patent claim 1:
`
`6
`
`
`
`22. (Currently amended) A semiconductor device, comprising:
`a substantially planar substrate having opposed major surfaces;
`an electrically conductive mounting pad located on one of the major
`surfaces of the substrate;
`The semiconductor device of claim 21 wherein the
`semiconductor die comprises a light emitting diode (LED) having a
`metallized bottom major surface that is mounted on the electrically
`conductive mounting pad, and the metallized bottom major surface
`comprises comprising one of an anode and a cathode of the LED;
`a first electrically conductive connecting pad located on the
`other of the major surfaces of the substrate; and
`a first electrically conductive interconnecting element
`extending through the substrate and electrically interconnecting the
`mounting pad and the first electrically conductive connecting pad.
`
`Id. at 80.
`
`On April 4, 2007, the Examiner issued a Notice of Allowability. Id. at 24. In
`
`the “Reasons For Allowance” attached to the Notice, the Examiner explained “[t]he
`
`device structure as set forth in the claims is not taught or suggested in the prior art,
`
`including more specifically the light emitting diode having metallized bottom
`
`surface, mounted on a mounting pad, and having the relationship to the
`
`interconnecting element and conductive connecting pad as set forth in claim 1.” Id.
`
`at 25.
`
`
`
`7
`
`
`
`VI. CLAIM CONSTRUCTION
`
`Because the ’486 patent has not expired, the Board applies the “broadest
`
`reasonable construction in light of the specification.” 37 C.F.R. § 42.100(b); see also
`
`Cuozzo Speed Techs. LLC v. Lee, 136 S. Ct. 2131, 2144-46 (2016). This claim
`
`construction standard is different from, and broader than, that applied in district
`
`court. Versata Dev. Grp., Inc. v. SAP Am., Inc., 793 F.3d 1306, 1327-28 (Fed. Cir.
`
`2015).1
`
`“metallized . . . surface”
`
`A.
`The term “metallized . . . surface” is not expressly defined in either the
`
`specification of the ’486 patent or its prosecution history. The first use of the term in
`
`the ’486 patent comes in the “Background of the Invention” section, where the
`
`patent explains “[o]ne type of packaging device widely used in the industry includes
`
`a metal lead frame. A metallization layer of aluminum located on the bottom surface
`
`of the semiconductor die is bonded to a conductive surface that forms part of the
`
`lead frame to attach and electrically connect the die to the lead frame.” Ex. 1001
`
`
`
`1 Petitioner does not concede that the meaning of any claim term is as broad
`
`under the Philips standard as under the broadest reasonable interpretation standard.
`
`Petitioner reserves the right to argue for alternative and narrower definitions in
`
`district court.
`
`
`
`8
`
`
`
`(’486 patent) 1:19-23 (emphasis added). The second usage also comes from the
`
`Background section, stating “[r]ecently, semiconductor die having a substrate
`
`surface metallization layer of a gold-tin alloy (80% Au:20% Sn approximately) have
`
`been introduced in light-emitting devices.” Id. at 1:49-51 (emphasis added).
`
`Similar to this description of the prior art, the Detailed Description begins
`
`with the explanation that “[i]n the example shown, semiconductor die 250 embodies
`
`a light-emitting diode and has anode and cathode electrodes (not shown) covering at
`
`least parts of its opposed major surfaces.” Id. at 5:7-10. As the above quote suggests,
`
`the patent discloses that the top and bottom surfaces comprise electrodes. It appears,
`
`therefore, that the ’486 patent uses the terms electrode and metallized surface
`
`somewhat interchangeably. That conclusion is further supported by the following
`
`explanation:
`
`The bonding pad on the top major surface of semiconductor die 250 is
`typically part of or connected to the anode electrode of the light-
`emitting diode. The metallization on the bottom major surface of
`semiconductor die 250 typically constitutes the cathode electrode of
`the light-emitting diode.
`
`Id. at 5:18-22 (emphasis added); see also id. at 5:10-12 (“Semiconductor die 250 is
`
`mounted on packaging device 100 with the metallization on its bottom major surface
`
`attached to mounting pad 130.”).
`
`
`
`9
`
`
`
`Consistent with the use of the term metallized surface in the specification,
`
`therefore, Petitioners assert that the broadest reasonable construction is a metal layer
`
`on at least a portion of the surface.
`
`This interpretation is supported, for example, by Ex. 1004 (Modern Dictionary
`
`of Electronics (7th ed. 1999)), which defines metallization in relevant part as “[a]
`
`film pattern (single or multilayer) of conductive material deposited onto a substrate
`
`to interconnect electronic components, or the metal film on the bonding area of a
`
`substrate that becomes part of the bond and performs both electrical and mechanical
`
`functions.” Id. at 467 (emphasis added); see also Ex. 1005 Microchip Fabrication
`
`(4th ed. 2000) 396 (“The most common and familiar use of metal films in
`
`semiconductor technology is for surface wiring. The materials, methods, and
`
`processes of ‘wiring’ the components parts together is generally referred to as
`
`metallization or the metallization process.”); Ex. 1006 (Plastic-Encapsulated
`
`Microelectronics (1995)) 459 (“METALLIZATION: A deposited or plated thin
`
`metallic film used for its protective or electrical properties.”); Ex. 1007 (Merriam
`
`Webster’s Collegiate Dictionary (10th ed.)) 730 (“metallize . . . to coat, treat, or
`
`combined with metal.”). All of these definitions suggest metallized surface is a
`
`broad technical term and are consistent with Petitioners’ proposed construction a
`
`thin layer of metal on at least a portion of the surface.
`
`
`
`10
`
`
`
`B.
`
`“the metallized top major surface comprises a first electrode . . .
`and the metallized bottom major surface comprises a second
`electrode”
`
`The term electrode appears in claim 3 of the ’486 as follows “the metallized
`
`top major surface comprises a first electrode of the LED and the metallized bottom
`
`major surface comprises a second electrode of the LED.” Thus, claim 3 refers back
`
`to the previously recited metallized top major surface of claim 2 and the metallized
`
`bottom major surface of claim 1 for antecedent basis. More specifically, claim 3
`
`further defines the previously recited structures from claims 1 and 2 to require that
`
`those structures each “comprises an electrode.” As discussed in the previous
`
`subsection, the broadest reasonable construction of the term metallized surface
`
`means a metal layer on at least a portion of the surface. The “electrode” recitations
`
`of claim 3, therefore require the previously recited metallized surfaces to comprise
`
`electrodes.
`
`The term “electrode” is not expressly defined in either the specification of the
`
`’486 patent or its prosecution history. The first use of the term in the ’486 patent
`
`comes with respect to figures 1A-1F, with the explanation that “[i]n the example
`
`shown, semiconductor die 250 embodies a light-emitting diode and has anode and
`
`cathode electrodes (not shown) covering at least parts of its opposed major
`
`surfaces.” Ex. 1001 (’486 patent) 5:7-10 (emphasis added). Although not shown in
`
`the figures, the patent explains that “[t]he bonding pad on the top major surface of
`
`11
`
`
`
`semiconductor die 250 is typically part of or connected to the anode electrode of the
`
`light-emitting diode. The metallization on the bottom major surface of
`
`semiconductor die 250 typically constitutes the cathode electrode of the light-
`
`emitting diode.” Id. at 5:18-23 (emphasis added).
`
`Petitioner, therefore, asserts that the broadest reasonable construction of “the
`
`metallized top major surface comprises a first electrode . . . and the metallized
`
`bottom major surface comprises a second electrode” means that the metallized
`
`surfaces comprise electrical contacts to the LED.
`
`This interpretation is supported, for example, by Ex. 1004 (Modern Dictionary
`
`of Electronics (7th ed. 1999)), which defines electrode in relevant part as “[t]hat part
`
`of a semiconductor device providing the electrical contact between the specified
`
`region of the device and the lead to its terminal.” Id. at 239; see also Ex. 1006
`
`(Plastic-Encapsulated Microelectronics (1995)) 453 (“ELECTRODES: The
`
`conductor or conductor lands of an electronic device.”); Ex. 1007 (Merriam
`
`Webster’s Collegiate Dictionary (10th ed.)) 730 (“electrode . . . a conductor used to
`
`establish electrical contact with a nonmetallic part of a circuit”). All of these
`
`definitions suggest electrode is a broad term and are consistent with Petitioner’s
`
`proposed construction the metallized surfaces comprise electrical contacts to the
`
`LED.
`
`
`
`12
`
`
`
`VII. PERSON HAVING ORDINARY SKILL IN THE ART
`
`As explained in M.P.E.P. § 2141.03, a number of factors may be considered in
`
`determining the proper level of skill:
`
`The person of ordinary skill in the art is a hypothetical person who is
`presumed to have known the relevant art at the time of the invention.
`Factors that may be considered in determining the level of ordinary
`skill in the art may include: (A) “type of problems encountered in the
`art;” (B) “prior art solutions to those problems;” (C) “rapidity with
`which innovations are made;” (D) “sophistication of the technology;
`and” (E) “educational level of active workers in the field. In a given
`case, every factor may not be present, and one or more factors may
`predominate.”
`
`A person of ordinary skill in the art at the time of the purported invention would
`
`have had at least a B.S. in mechanical or electrical engineering or a related field, and
`
`two years’ experience designing LED packages. Ex. 1003 (Pecht) ¶¶ 29-31.2 This
`
`description is approximate, and a higher level of education or skill might make up
`
`for less experience, and vice-versa. Id. For example, a M.S. in the above fields and
`
`two years’ experience would suffice. Id.
`
`
`
`2 Exhibit 1003 is the declaration of Michael Pecht Ph.D.
`
`
`
`13
`
`
`
`VIII. BRIEF DESCRIPTION OF THE PRIOR ART
`
`A.
`Japanese Patent Application Publication No. 2003-17754 (Rohm)
`Japanese Patent Application Publication No. 2003-17754 (“Rohm”) is entitled
`
`“Surface Mount Type Semiconductor Device.” Ex. 1008 (Rohm). Rohm, which was
`
`not of record during the prosecution of the ’486 patent, was published on January 17,
`
`2003, which is prior to the filing date of the ’486 patent. Rohm, therefore, is prior art
`
`against the ’486 patent under pre-AIA 35 U.S.C. § 102(a).
`
`As will be apparent throughout this Petition, the invention disclosed and
`
`claimed in Rohm is, for all relevant purposes, indistinguishable from the purported
`
`invention claimed in the ’486 patent.
`
`Figure 1 of Rohm (reproduced and colored below) shows a semiconductor
`
`device. The device includes a substantially planar substrate 12 (colored red) with top
`
`and bottom major surfaces. Ex. 1008 (Rohm) Abstract, Claim 1, ¶13, ¶14. The top
`
`surface is depicted in figure 1(B) and the bottom surface is shown in figure 2.
`
`
`
`14
`
`
`
`
`
`Four metal conductors are provided on the substrate 12 as shown in figure 1.
`
`An electrically conductive mounting pad (die bonding electrode 18, colored green) is
`
`shown on the left side of the top major surface of substrate 12. Ex. 1008 (Rohm)
`
`Abstract, Claim 1, ¶14, ¶23. An electrically conductive bonding pad (wire bonding
`
`electrode 20, also colored green) is shown on the right side of the top major surface
`
`of substrate 12. Ex. 1008 (Rohm) ¶14, Abstract, Claim 1, ¶1, ¶7, ¶9, ¶14. A pair of
`
`conductive pads (surface mount electrodes 22 and 24, colored orange) are provided
`
`on the bottom major surface of the substrate 12 and are connected to the mounting
`
`pad 18 and the bonding pad 20 respectively via interconnecting elements
`
`(connection electrodes 26 and 28, colored purple). Ex. 1008 (Rohm) Claim 1, ¶7,
`
`¶15, ¶19.
`
`Figure 1 also shows an LED chip 30 (colored blue). A front surface electrode
`
`30a (colored violet) is shown on the top surface of LED 30 and is connected via wire
`
`32 (colored yellow) to bonding pad 20. Ex. 1008 (Rohm) Claim 1, ¶7 ¶16. In
`
`addition, although not shown in figure 1, LED chip 30 has a “bottom surface
`
`electrode” on its bottom major surface that is electrically connected to the
`
`electrically conductive mounting pad. Ex. 1008 (Rohm) ¶16.
`
`B.
`
`Japanese Patent Application Publication No. 2001-352102
`(Matsushita)
`Japanese Patent Application Publication No. 2001-352102 (“Matsushita”) is
`
`entitled “Optical Semiconductor Device.” Ex. 1009 (Matsushita). Matsushita,
`
`
`
`15
`
`
`
`which was not of record during the prosecution of the ’486 patent, was published on
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`December 21, 2001, more than one year prior to the filing date of the ’486 patent on
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`June 27, 2003. Matsushita, therefore, is prior art against the ’486 patent under pre-
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`AIA 35 U.S.C. §§ 102(a) and (b).
`
`Here again, as with Rohm, Matsushita is, for all relevant purposes,
`
`indistinguishable from the purported invention claimed in the ’486 patent.
`
`Figure 2 of Matsushita (reproduced and colored below) shows a
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`semiconductor device. The device includes a substantially planar substrate 1
`
`(colored red) with top and bottom major surfaces. Ex. 1009 (Matsushita) Abstract,
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`Claim 1, ¶7, ¶12. The the top surface is depicted in figure 1.
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`
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`Four metal conductors are provided on the substrate 1 as shown in figure 2.
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`An electrically conductive mounting pad comprised of the upper portion of electrode
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`3 (colored green) is shown on the left side of the top major surface of substrate 1.
`
`
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`16
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`
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`Ex. 1009 (Matsushita) Abstract, Claim 1, ¶7, ¶13. An electrically conductive
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`bonding pad (also colored green) comprised of the upper portion of electrode 2 is
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`shown on the right side of the top major surface of substrate 1. Ex. 1009
`
`(Matsushita) Abstract, Claim 1, ¶7, ¶12. A pair of conductive pads (colored orange)
`
`are comprised respectively of the bottom portions of electrodes 2 and 3, and are
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`provided on the bottom major surface of the substrate 1. Ex. 1009 (Matsushita)
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`Abstract, ¶7, ¶9, ¶12. In addition, the upper and bottom portions of electrodes 2 and
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`3 are interconnected by a pair of electrically conductive interconnect elements
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`(colored purple). Ex. 1009 (Matsushita) Abstract, ¶7, ¶9, ¶12.
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`C. U.S. Patent No. 5,376,580 to Kish et al. (“Kish”)
`U.S. Patent No. 5,376,580 (“Kish”) is entitled “Wafer Bonding of Light
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`Emitting Diode Layers.” Ex. 1010. Kish, which was not of record during the
`
`prosecution of the ’486 patent, issued on December 27, 1994, more than one year
`
`prior to the filing date of the ’486 patent. Kish, therefore, is prior art against the ’486
`
`patent under pre-AIA 35 U.S.C. §§ 102(a), (b), and (e).
`
`
`
`17
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`
`
`Kish discloses a variety of vertical LEDs in which one metal electrode is
`
`provided on the top surface and the other
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`metal electrode is provided on the bottom
`
`surface. See, e.g., Ex. 1010 (Kish) Figs. 7,
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`12, 14, 15; 7:48-55; 9:64-66; 10:53-55;
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`13:30-33. In figure 14 (reproduced to the
`
`right) the metalized top and bottom surfaces are labeled 142 and 144 respectively.
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`Id. at 7:48-55; 10:53-55; 13:30-33; see also id. at 9:64-10:1.
`
`D. U.S. Patent No. 5,523,589 to Edmond et al. (“Edmond 589”)
`U.S. Patent No. 5,523,589 (“Edmond 589”) is entitled “Vertical Geometry
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`Light Emitting Diode with Group III Nitride Active Layer and Extended Lifetime.”
`
`Ex. 1011. Edmond 589, which was not of record during the prosecution of the ’486
`
`patent, issued on June 4, 1996, more than one year prior to the filing date of the ’486
`
`patent. Edmond 589, therefore, is prior art against the ’486 patent under pre-AIA 35
`
`U.S.C. §§ 102(a), (b), and (e).
`
`Edmond 589 discloses a vertical LED in which one contact is provided on the
`
`top surface and the other contact is provided on the bottom surface. Ex. 1011
`
`(Edmond 589) 5:9-12, 5:56-62; 7:67-8:5. In figure 1 (reproduced to the right) the
`
`
`
`18
`
`
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`metalized top surface is labeled 30. Id. at 5:56-62 (“An ohmic contact 30 can be
`
`applied to the upper heterostructure
`
`layer 26 to complete the advantageous
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`vertical structure of the invention.”).
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`In addition, the metallized bottom
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`surface comprises ohmic contract 22.
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`Id. at 5:9-12. Edmond 589 also
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`discloses that the ohmic contacts “are each formed of a metal such as aluminum
`
`(Al), gold (Au), platinum (Pt), or nickel (Ni), but may be formed of other material
`
`for forming ohmic contacts as understood by those skilled in the art.”). Id. at 5:56-
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`61.
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`IX. PRECISE REASONS FOR THE RELIEF REQUESTED
`
`A. Ground 1: Claims 1-3 Are Rendered Obvious by Rohm alone or in
`view of Kish
`
`1. Independent Claim 1
`
`“1. A semiconductor device comprising”
`To the extent that the preamble is found to limit the claims, Rohm discloses
`
`“[a] semiconductor device.” Rohm discloses “a light-emitting device using an LED
`
`chip 30 in the example described above, [and] the present invention may also be
`
`applied to other light-emitting devices using semiconductor lasers or the like.” Ex.
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`1008 (Rohm) ¶30, see also id. at Title (“Surface Mount Type Semiconductor
`
`
`
`19
`
`
`
`Device”); Abstract, Claim 1, ¶1, ¶7; Ex. 1003 (Pecht) ¶52. “A surface mount type
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`semiconductor light-emitting
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`device (simply called “light-
`
`emitting device” hereinafter) 10
`
`of this example [is] illustrated
`
`in FIGS. 1 and 2.” Ex. 1008
`
`(Rohm) ¶13. Figure 1 is
`
`reproduced to the right.
`
`“[a] a substantially planar substrate having opposed major
`surfaces”
`Rohm discloses “an insulating substrate 12.” Ex. 1008 (Rohm) ¶13, see also
`
`id. at Abstract, Claim 1, ¶14; Ex.
`
`1003 (Pecht) ¶53. The substrate
`
`can be seen in figures 1 and 2. In
`
`figure 1 (reproduced to the
`
`right), the planar substrate 12
`
`(colored red) can be seen in
`
`cross-section. Ex. 1008 (Rohm) ¶17 (noting that “[t]he planar shape of the substrate
`
`12 is rectangular.”); Ex. 1003 (Pecht) ¶53. The planar substrate 12 has a first major
`
`surface on top, upon which the light-emitting type LED chip 30 is mounted. Ex.
`
`
`
`20
`
`
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`1008 (Rohm) ¶16, ¶19; Ex. 1003 (Pecht) ¶53, ¶54. The planar substrate 12 also has a
`
`second major surface on the bottom, opposite the top surface. Id.
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`“[b] an electrically conductive mounting pad located on one
`of the major surfaces of the substrate”
`Rohm discloses an electrically conductive mounting pad in the form of the
`
`“the die bonding electrode 18 to which the LED chip 30 is bonded.” Ex. 1008
`
`(Rohm) ¶23; see also id. at Abstract,
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`Claim 1, ¶14; Ex. 1003 (Pecht) ¶54.
`
`This arrangement can be seen in figure
`
`1 (reproduced to the right), which
`
`depicts the die bonding electrode 18 (colored green), which corresponds to the
`
`claimed electrically conductive mounting pad located on the top major surface of the
`
`substrate. The mounting pad can also be
`
`seen in figure 2 (reproduced to the right). In
`
`addition, Rohm explains “[a] bottom surface
`
`electrode of this LED chip 30 and the die
`
`bonding electrode 18 are electrically
`
`connected.” Id. at ¶16; see also Ex. 1003
`
`(Pecht) ¶54. A person of ordinary skill would understand that the description of the
`
`structures are electrically connected indicates that the die bonding electrode 18 is
`
`
`
`21
`
`
`
`electrically conductive. Id. In addition, electrode 18 is electrically conductive
`
`because electrodes are electrically conductive. Id.
`
`“[c] a light emitting diode (LED) having a metallized bottom
`major surface that is mounted on the electrically conductive
`mounting pad, the metallized bottom major surface
`comprising one of an anode and a cathode of the LED”
`Rohm discloses an “LED chip 30.” Ex. 1008 (Rohm) Abstract, Claim 1, ¶16.
`
`Rohm explains that “[the] light-emitting type LE