` Old‘S'nOL60r,
`
`
`
`x a
`
`
`
`TO THE COMMISSIONERFOR PATENTS:
`
`Transmitted herewith is a patent application identified as follows:
`First-named inventor: Laurence B. Boucher
`Assignee: Alacritech, Inc.
`Filing Date: September 27, 2002
`Title: FAST-PATH APPARATUS FOR RECEIVING DATA CORRESPONDING TO A TCP CONNECTION
`
`‘This application claims the benefit under 35 USC §120 (prior application not abandoned)of:
`[.PriororApplication:“F“Fyast-Path Apparatus|Eor ReceivingDatDataaCorrespondingto.toa TCPConnectioron”)
`Serial No.: 10/092,967_ f
`FilingDate: March 6, 2002
`Atty. Docket: ALA-006C
`{(Brtiner:ZamMaung
`This application claims the benefit under 35 USC §120 of Application Serial No. 10/092,967, filed March 6,
`2002, which in turn claims the benefit under 35 USC §120 of Application Serial No. 10/023,240, filed December
`15, 2001, which in turn claims the benefit under 35 USC 8120 of Application Serial No. 09/464,283, filed
`December 15, 1999, which in turn claims the benefit under 35 USC §120 of Application Serial No. 09/439,603,
`filed Novembcr 12, 1999, which in turn claims the benefit under 35 USC §120 of Application Serial No.
`09/067,544,filed April 27, 1998, which in tum claims the benefit under 35 USC §119 of Provisional Application
`Serial No. 60/061,809, filed October 14, 1997.
`
`This application also claims the benefit under 35 USC §120 of Application Serial No. 09/384,792, filed
`August 27, 1999, whichin turn claims the benefit under 35 USC §120 of Application Serial No. 09/141,713, filed
`August 28, 1998, which in turn claims the benefit under 35 USC §119 of Provisional Application Serial No.
`60/098 296, filed August 27, 1998.
`
`US.
`US.
`US.
`US.
`US.
`US.
`US.
`US.
`US.
`US.
`US.
`
`(X)
`
`(xX)
`
`(X)
`
`This application also claims the benefit under 35 U.S.C. §120 ofthe following:
`Patent Application Serial No.
`09/416,925 (ALA-005), filed October 13, 1999;
`Patent Application Serial No:
`09/514,425 (ALA-007), filed February 28, 2000;
`Patent Application Serial No.
`09/675,484 (ALA-010A), filed September 29, 2000;
`Patent Application Serial No.
`09/675,700 (ALA-010B), filed September 29, 2000;
`Patent Application Serial No.
`09/789,366 (ALA-013), filed February 20, 2001;
`Patent Application Scrial No.
`09/801,488 (ALA-011), filed March 7, 2001;
`Patent Application Serial No.
`09/802,551 (ALA-012), filed March 9, 2001;
`Patent Application Serial No.
`09/802,426 (ALA-014), filed March 9, 2001;
`Patent Application Serial No.
`09/802,550 (ALA-015), filed March 9, 2001;
`Patent Application Serial No.
`09/855,979 (ALA-016), filed March 14, 2001; and
`Patent Application Serial No.
`09/970,124 (ALA-020), filed October 2, 2001.
`
`The specification contains a statementclaiming priority under 35 USC § 120 and claiming the benefit under
`35 U.S.C. §119.
`The entire disclosure of each of the prior applications (10/092,967; 10/023,240; 09/464,283; 09/439,603;
`09/067,544; 09/384,792; 09/141,713; 09/416,925; 09/514,425; 09/675,484; 09/675,700; 09/789,366;
`09/801,488; 09/802,551; 09/802,426; 09/802,550; 09/855,979; 09/970,124) 1s consideredas being partof the
`disclosure of the accompanying application and is hereby incorporated by reference therein.
`The entire disclosure of each of the prior provisional applications (60/061,809; 60/098,296) is considered as
`being part ofthe disclosure of the accompanying application and is hereby incorporated by referencetherein.
`
`WISTRON CORP. EXHIBIT 1002.001
`
`
`
`WISTRON CORP. EXHIBIT 1002.001
`
`
`
`i.
`
`b e o
`
`Enclosedare:
`
`
`
`aK
`
`page Terminal Disclaimer Over A Prior Patent
`A checkforfiling fee ($ 922.00)
`Return Receipt Postcard
`
`145
`
`4
`
`tN
`
`x
`
`pages Application Transmittal Letter
`pages Specification
`pages Claims
`page Abstract
`89—pages Drawings
`4
`pages Declaration/Powerof Attorney from prior
`application 10/092,967 (signed - copy)
`pages Declaration/Power of Attorney from prior
`application 10/092,967 (signed - copy)
`page CD Appendix Transmittal Letter
`CD Appendix (two copics)
`
`*
`
`Se..
`
`‘%
`
`Newly Executed Declaration Not Required:
`A newly executed declaration is not filed in this application because, under 37 CFR 1.63(d)(1), a newly executed
`declaration is not required because:
`the prior application contained a declaration as prescribed by 37 CFR 1.63; the
`continuation application (this application)is filed by all of the inventors namedin the prior application; the specification
`and drawings in the continuation application (this application) contain no matter that would have been new matter in the
`prior application; and a copy ofthe executed declaration (there were two)in the prior applicationis being submitted in the
`continuation application (this application).
`
`Thefiling fee is calculated as follows:
`
`CLAIMSASFILED
`
`$922.00
`
`I hereby certify that this is being deposited with the U.S. Postal
`Service “Express Mail Post Office to Addressee” service under
`37 CFR § 1.10 on the date indicated below and 1s addressed to:
`
`Box Patent Application
`Assistant Commissionerfor Patents
`Washington, D.C. 20231
`
` By:
`
`Typed Name: Mark Lauer
`
`Express Mail Label No.: EL928548779US.
`Date ofDeposit: 27 Gz.
`.
`—_
`
`~
`
`Respectfully submitted,
`By: gxeeZ
`
`
`Mark Lauer
`
`Attorney for Applicants
`Reg. No. 36,578
`(~ Customer No.2455017~~
`Date: GS-27 -22.
`
`Correspondence Address:
`MarkLauer, Patent Attorney
`Pleasanton, California 94566
`7041 Koll Center Parkway, Suite 280
`
`Phone:
`Fax:
`
`(925) 484-9295
`(925) 484-9291
`
`
`
`WISTRON CORP. EXHIBIT 1002.002
`
`WISTRON CORP. EXHIBIT 1002.002
`
`
`
`aT
`teRE iy
`ws
`Reg Te TS
`Ch Supa we AB ule Php Pop AoA at ty
`2 Red? How
`
`TO THE ASSISTANT COMMISSIONER FOR PATENTS:
`
`Inventors:
`
`Laurence B. Boucher,etal.
`
`Atty Docket: ALA-006E
`
`Filing Date:
`
`September 27, 2002
`
`Serial No.:
`
`Unknown
`
`FAST-PATH APPARATUS FOR RECEIVING DATA CORRESPONDING TO
`A TCP CONNECTION
`
`
`Compact Disk Transmittal Letter per 37 CFR 1.52(e)3(ii1))
`
`Title:
`
`Sir:
`
`Transmitted herewith are:
`
`Two Labeled Compact Discs — Recordable (CD-R) — “Copy 1” and “Copy 2,” each in a
`
`CD case and contained in a padded envelope.
`
`The content on the two discs is identical
`
`The machine format is: IBM-PC
`
`The operating system is: MS-Windows
`
`The creation date of the CDsis: September 26, 2002
`
`The name,date and size of the files on the CDsarelisted below:
`
`There are three folders on each disc: 1) CD Appendix A,
`
`2) CD Appendix B, and
`
`3) CD Appendix C.
`
`Folder Appendix A contains twofiles:
`
`CD Appendix A Title Page.txt. Its size is 370 bytes. It was created 9/26/02.
`
`Rev.v. Its size is 84.4KB. It was created 1/7/99.
`
`Folder Appenidix B contains twofiles:
`
`CD Appendix B Title Page.txt. Its size is 495 bytes. It was created 9/26/02.
`
`Microcode.txt. Its size is 105 KB. It was created 10/1/99.
`
`WISTRON CORP. EXHIBIT 1002.003
`
`
`
`WISTRON CORP. EXHIBIT 1002.003
`
`
`
`2
`-*.W
`
`Ae MEA
`unm Ey
`py ey
`US geo ae gee we ene eee
`Eres
`ed. BOP fee Healt He Ua lt Goa 4OUR aLUr,
`nt may
`
`Folder Appendix C contains three files:
`
`CD Appendix C Title Page.txt. Its size is 416 bytes. It was created 9/26/02.
`
`atcpsource.wrd.ixt. Iis size is 778 KB. It was created (written to disc) 2/19/02.
`
`simbasource.wrd.txt. Its size is 262 KB. It was created (written to disc) 2/19/02.
`
`Respectfully submitted,
`
`CERTIFICATE OF MAILING
`
`I hereby certify that this correspondence 1s being deposited with
`the United States Postal Service as Express Mail Label No.
`EL928365779USin an envelope addressed to: Box PATENT
`APPLICATION,Assistant Commissionerfor Patents,
`Washington, D.C. 20231, on September 27, 2002.
`
`Date: 7 =Z7 ~22 a Tel:
`Mark Lauer
`Fax:
`
`Mark Lauer
`Reg. No. 36,578
`7041 Koll Center
`Parkway
`Suite 280
`Pleasanton, CA 94566
`
`(925) 484-9295
`(925) 484-929]
`
`va
`fo
`
`v '
`
`_
`
`\
`
`|
`
`2
`
`WISTRON CORP. EXHIBIT 1002.004
`
`
`
`WISTRON CORP. EXHIBIT 1002.004
`
`
`
`
`
`ia ih
`
`wee a DeadHae
`
`ALA-006E
`
`TERMINAL DISCLAIMER OVER A PRIOR PATENT
`:
`10/03/2002 DTESSEM 00000026 10260;
`8
`;
`In re Application of: Laurence B. Boucheret al.
`93 FC:148
`
`a
`110.00 Op
`
`Application No.:
`
`Unknown
`
`Filed:
`
`Title:
`
`September 27, 2002
`
`FAST-PATH APPARATUS FOR RECEIVING DATA
`CORRESPONDING TO A TCP CONNECTION
`
`Express Mail No.:
`
`EL928365779US
`
`The owner, Alacritech, Inc., of a one hundred percentinterest in the instant
`_ application hereby disclaims, except as provided below,the terminal part of the statutory
`’ term ofany patent granted ontheinstant application, which would extend beyond the
`expiration date of the full statutory term defined in 35 U.S.C. 154 to 156 and 173, as
`presently shortened by any terminal disclaimer, of prior U.S. Patent Nos. 6,226,680 and
`6,247,060. The ownerhereby agrees that any patent so granted on the instant application
`shall be enforceable only for and during such period that it and the prior patents are
`commonly owned. This agreement runs with any patent granted on the instant application
`and is binding upon the grantee, its successorsor assigns.
`
`In making the above disclaimer, the owner does not disclaim the terminal part of
`any patent granted on the instant application that would extend to the expiration date of
`the full statutory term as defined in 35 U.S.C. 154 to 156 and 173 of the prior patents, as
`presently shortened by any terminal disclaimer, in the event that they later: expire for
`failure to pay a maintenance fee, are held unenforceable, are found invalid by a court of
`competent jurisdiction, are statutorily disclaimed in whole or terminally disclaimed under
`37 CFR 1.321, have all claims canceled by a reexamination certificate, are reissued, or
`are in any manner terminated prior to the expiration of its full statutory term as presently
`shortened by any terminal disclaimer.
`
`I hereby declare that all statements made herein of my own knowledgeare true
`and thatall statements made on information and belief are believed to be true; and further
`that these statements were made with the knowledgethat willful false statements and the
`like so made are punishable by fine or imprisonment, or both, under Section 1001 of Title
`18 of the United States Code and that such willful false statements may jeopardize the
`validity of the application or any patent issued thereon.
`
`The undersigned is an attorney or agent of record.
`7 22,
`Gee
`
`Date:
`
`_
`
`Mark Lauer
`Registration No. 36,578
`
`The terminal disclaimer fee under 37 CFR 1.20(d) is included.
`
`a el
`Ne NN
`
`
`
`WISTRON CORP. EXHIBIT 1002.005
`
`WISTRON CORP. EXHIBIT 1002.005
`
`
`
`YO.
`* ALA-006E
`
`
`fed?
`
`SUDer HT oF Beeee
`bs Halk
`WP Fees at
`thal’ En
`
`FAST-PATH APPARATUS FOR RECEIVING DATA
`
`CORRESPONDINGTO A TCP CONNECTION
`
`5
`
`10
`
`Laurence B. Boucher
`
`Stephen E. J. Blightman
`
`Peter K. Craft
`
`David A. Higgen
`
`Clive M. Philbrick
`
`Daryl D. Starr
`
`CROSS-REFERENCE TO RELATED APPLICATIONS
`
`This application claims the bencfit under 35 U.S.C. §120 of U.S. Patent Application Serial
`No. 10/092,967, entitled “FAST-PATH APPARATUS FOR RECEIVING DATA
`
`CORRESPONDING TO A TCP CONNECTION,”filed March 6, 2002, by Laurence B.
`Boucheret al., which in turn claims the benefit under 35 U.S.C. §120 of U.S. Patent
`
`15
`
`Application Serial No. 10/023,240 (Attorney Docket No. ALA-006A), entitled “TRANSMIT
`_ FAST-PATH PROCESSING ON TCP/IP OFFLOAD NETWORK INTERFACEDEVICE,”
`
`filed December 15, 2001, by Laurence B. Boucheret al., which in turn claims the benefit
`under 35 U.S.C. §120 of U.S. Patent Application Serial No. 09/464,283 (Attomey Docket No.
`
`20
`
`ALA-006), entitled “INTELLIGENT NETWORK INTERFACE DEVICE AND SYSTEM
`
`FOR ACCELERATED COMMUNICATION”, filed December 15, 1999, by Laurence B.
`
`Boucheret al., which in turn claims the benefit under 35 U.S.C. §120of U.S. Patent
`
`Application Serial No. 09/439,603 (Attorney Docket No. ALA-009), entitled “INTELLIGENT
`
`NETWORK INTERFACE SYSTEM AND METHOD FOR ACCELERATED PROTOCOL
`
`25
`
`PROCESSING”,filed November 12, 1999, by Laurence B. Boucher et al., which in turn
`
`claims the benefit under 35 U.S.C. §120 of U.S. Patent Application Serial No. 09/067,544
`
`(Attorney Docket No. ALA-002), entitled “TINTELLIGENT NETWORK INTERFACE
`
`SYSTEM AND METHOD FOR ACCELERATED PROTOCOL PROCESSING”,filed April
`
`27, 1998, which in turn claims the benefit under 35 U.S.C. § 119(e)(1) of the Provisional
`
`
`
`30~=—sApplication filed under 35 U.S.C. §111(b) entitled “INTELLIGENT NETWORK
`
`WISTRON CORP. EXHIBIT 1002.006
`
`
`
`WISTRON CORP. EXHIBIT 1002.006
`
`
`
`ALA-006E
`
`
`
`INTERFACE CARD AND SYSTEM FOR PROTOCOL PROCESSING,” Serial No.
`
`60/061,809 (Attorney Docket No. ALA-001),filed on October 14, 1997,
`
`This application also claims the benefit under 35 U.S.C. §120 of U.S. Patent Application
`
`Serial No. 09/384,792 (Attorney Docket No. ALA-008), entitled “INTELLIGENT
`
`NETWORK INTERFACE DEVICE AND SYSTEM FOR ACCELERATED
`
`COMMUNICATION,”filed August 27, 1999, which in turn claims the benefit under 35
`
`U.S.C. §120 of U.S. Patent Application Serial No. 09/141,713 (Attorney Docket No. ALA-
`
`003), entitled “INTELLIGENT NETWORK INTERFACE DEVICE AND SYSTEM FOR
`
`ACCELERATED PROTOCOL PROCESSING”, filed August 28, 1998, which both claim the
`
`10
`
`benefit under 35 U.S.C, § 119(e)(1) of the Provisional Application filed under 35 U.S.C.
`
`§111(b) entitled “INTELLIGENT NETWORK INTERFACE DEVICE AND SYSTEM FOR
`
`ACCELERATED COMMUNICATION,”Serial No. 60/098,296 (Attorney Docket No. ALA-
`
`004), filed August 27, 1998.
`
`15
`
`This application also claims the benefit under 35 U.S.C. §120 of U.S. Patent Application
`Serial No. 09/416,925 (Attorney Docket No. ALA-005), entitled “QUEUE SYSTEM FOR
`- MICROPROCESSORS,” filed October 13, 1999, U.S. Patent Application Serial No.
`
`09/514,425 (Attorney Docket No. ALA-007), entitled “PROTOCOL PROCESSING STACK
`
`FOR USE WITH INTELLIGENT NETWORK INTERFACE CARD,”filed February 28,
`
`2000, U.S. Patent Application Serial No. 09/675,484 (Attorney Docket No. ALA-010A),
`
`20
`
`entitled “INTELLIGENT NETWORK STORAGE INTERFACE SYSTEM,”filed September
`
`29, 2000, U.S. Patent Application Serial No. 09/675,700 (Attorney Docket No. ALA-01 0B),
`
`entitled “INTELLIGENT NETWORK STORAGE INTERFACE DEVICE,”filed September
`
`29, 2000, U.S. Patent Application Serial No. 09/789,366 (Attorney Docket No. ALA-013),
`
`entitled “OBTAINING A DESTINATION ADDRESS SO THAT A NETWORK
`
`25
`
`INTERFACE DEVICE CAN WRITE NETWORK DATA WITHOUT HEADERS
`
`DIRECTLY INTO HOST MEMORY,”filed February 20, 2001, U.S. Patent Application
`
`Serial No, 09/801 ,488 (Attorney Docket No. ALA-011), entitled “PORT AGGREGATION
`
`FOR NETWORK CONNECTIONS THAT ARE OFFLOADED TO NETWORK
`
`INTERFACE DEVICES,”filed March 7, 2001, U.S. Patent Application Serial No. 09/802,551
`
`30
`
`(Attorney Docket No. ALA-012), entitled “INTELLIGENT NETWORK STORAGE
`
`INTERFACE SYSTEM,”filed March 9, 2001, U.S. Patent Application Serial No. 09/802,426
`
`(Attorney Docket No. ALA-014), entitled “REDUCING DELAYS ASSOCIATED WITH
`2
`
`WISTRON CORP. EXHIBIT 1002.007
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`
`
`WISTRON CORP. EXHIBIT 1002.007
`
`
`
`ALA-006E
`
`
`
`INSERTING A CHECKSUM INTO A NETWORK MESSAGE,”filed March 9, 2001, U.S.
`Patent Application Serial No. 09/802,550 (Attorney Docket No. ALA-015), entitled
`
`“INTELLIGENT INTERFACE CARD AND METHOD FOR ACCELERATED PROTOCOL
`
`PROCESSING,”filed March 9, 2001, U.S. Patent Application Serial No. 09/855,979
`
`(Attorney Docket No. ALA-016), entitled “NETWORK INTERFACE DEVICE
`
`~ EMPLOYING DMA COMMAND QUEUE,”filed March 14, 2001, U.S. Patent Application
`
`Serial No. 09/970,124 (Attorney Docket No. ALA-020), entitled “NETWORK INTERFACE
`
`DEVICE THAT FAST-PATH PROCESSES SOLICITED SESSION LAYER READ
`
`COMMANDS,”filed October 2, 2001.
`
`10
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`The subject matter ofall of the above-identified patent applications (including the
`
`subject matter in the Microfiche Appendix of U.S. Application Serial No. 09/464,283), and of
`
`the two above-identified provisional applications, is incorporated by reference herein.
`
`REFERENCE TO COMPACT DISC APPENDIX
`
`15
`
`The Compact Disc Appendix (CD Appendix), whichis a part of the present disclosure,
`
`includes three folders, designated CD Appendix A, CD Appendix B, and CD Appendix C on
`
`the compact disc. CD Appendix A contains a hardware description language (verilog code)
`description of an embodimentof a receive sequencer. CD Appendix B contains microcode
`executed by a processorthat operates in conjunction with the receive sequencer of CD
`
`20
`
`Appendix A. CD Appendix C contains a device driver executable on the host as well as ATCP
`
`code executable on the host. A portion of the disclosure of this patent document contains
`
`material (other than any portion of the ‘“‘free BSD” stack included in CD Appendix C) which is
`
`subject to copyright protection. The copyright ownerof that material has no objection to the
`
`facsimile reproduction by anyone of the patent documentor the patent disclosure, as it appears
`
`25
`
`in the Patent and Trademark Office patentfiles or records, but otherwise reserves all copyright
`
`rights.
`
`TECHNICAL FIELD
`
`The present invention relates generally to computer or other networks, and more
`
`particularly to processing of information communicated between hosts such as computers
`
`connected to a network.
`
`WISTRON CORP. EXHIBIT 1002.008
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`WISTRON CORP. EXHIBIT 1002.008
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`ALA-006E
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`Wop Aa Site ae ae
`a
`yO eon
`Boo BOP a al ae BOP a!
`
`BACKGROUND
`The advantages of network computing are increasingly evident. The convenience and
`
`efficiency of providing information, communication or computational powerto individuals at
`
`- their personal computeror other end user devices has led to rapid growth of such network
`
`computing, including internet as well as intranet devices and applications.
`
`Asis well known, most network computer communication is accomplished with the aid of
`a layered software architecture for moving information between host computers connected to
`the network. The layers help to segregate information into manageable segments, the gencral
`functions of cach layer often based on an international standard called Open Systems
`
`10
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`Interconnection (OSI). OSI sets forth seven processing layers through which information may
`
`pass whenreceived by a host in order to be presentable to an end user. Similarly, transmission
`of information from a host to the network maypass through those seven processing layers in
`reverse order. Each step of processing and service by a layer may include copying the
`processed information.. Another reference modelthat is widely implemented, called TCP/IP
`(TCP stands for transport control protocol, while IP denotes internet protocol) essentially
`
`employs five of the seven layers of OSI.
`
`Networks may include, for instance, a high-speed bus such as an Ethernet connection or an
`
`internet connection between disparate local arca networks (LANs), cach of which includes
`
`multiple hosts, or any of a variety of othcr known meansfor data transfer between hosts.
`
`20
`
`According to the OSI standard, physical layers are connected to the network at respective
`
`hosts, the physical laycrs providing transmission and receipt of raw data bits via the network.
`
`A datalink layer is serviced by the physical layer of each host, the data link layers providing
`- frame division anderror correction to the data received from the physical layers, as well as
`
`processing acknowledgment framessent by the receiving host. A network layer of each hostis
`serviced by respective data link layers, the network layers primarily controlling size and
`
`25
`
`coordination of subnets of packets of data.
`
`A transport layer is serviced by each network layer and a session layer is serviced by each
`transport layer within each host. Transport layers accept data from their respective session
`
`layers and split the data into smaller units for transmission to the other host’s transport layer,
`
`30
`
`which concatenates the data for presentation to respective presentation layers. Scssion layers
`
`allow for enhanced communication control between the hosts. Presentation layers are serviced
`
`by their respective session layers, the presentation layers translating between data semantics
`4
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`WISTRON CORP. EXHIBIT 1002.009
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`WISTRON CORP. EXHIBIT 1002.009
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`ALA-006E
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`iy
`Sg ghCg Seee
`GS Sb hyoe get mn
`aul, RQGa eR OR PWS un Be CIE Brae ot
`EanBee
`
`and syntax which may bepeculiar to each host and standardized structures of data
`representation. Compression and/or encryption of data may also be accomplishedat the
`
`presentation level. Application layers are serviced by respective presentation layers, the
`
`application layers translating between programs particular to individual hosts and standardized
`
`programs for presentation to either an application or an end user. The TCP/IP standard
`includes the lower four layers and application layers, but integrates the functions of session
`layers and presentation layers into adjacent layers. Generally speaking, application,
`
`presentation and session layers are defined as upper layers, while transport, network and data
`
`link layers are defined as lowerlayers.
`
`10
`
`The rules and conventions for each layer are called the protocol of that layer, and since the
`
`protocols and general functions of each layer are roughly equivalent in various hosts, it is
`
`useful to think of communication occurring directly between identical layers of different hosts,
`
`even thoughthese peer layers do not directly communicate without information transferring
`
`sequentially through each layer below. Each lower layer performsa service for the layer
`
`15
`
`-
`
`immediately aboveit to help with processing the communicated information. Each layer saves
`the information for processing and serviceto the next layer. Due to the multiplicity of
`hardware and software architectures, devices and programs commonly employed, each layeris
`
`necessary to insure that the data can makeit to the intended destination in the appropriate
`form, regardless of variations in hardware and software that may intervene.
`.
`20
`In preparing data for transmission fromafirst to a second host, some control data is added
`
`at each layer of the first host regarding the protocol of that layer, the control data being
`
`indistinguishable from the original (payload) data for all lower layers of that host. Thus an
`
`application layer attaches an application header to the payload data and sends the combined
`
`data to the presentation layer of the sending host, which receives the combined data, operates
`on it and addsa presentation headerto the data, resulting in another combined data packet.
`
`25
`
`The data resulting from combination of payload data, application header and presentation
`
`headeris then passed to the session layer, which performs required operations including
`
`attaching a session headerto the data and presenting the resulting combination of data to the
`
`transport layer. This process continues as the information movesto lower layers, with a
`
`30
`
`transport header, network header and data link header andtrailer attached to the data at each of
`
`those layers, with each step typically including data moving and copying, before sending the
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`data as bit packcts over the network to the second host.
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`The receiving host generally performs the converse of the above-described process,
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`beginning with receiving the bits from the network, as headers are removed and data processed
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`in order from the lowest (physical) layer to the highest (application) layer before transmission
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`to a destination of the receiving host. Each layer of the receiving host recognizes and
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`manipulates only the headers associated with that layer, since to that layer the higher layer
`control data is included with and indistinguishable from the payload data. Multiple interrupts,
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`valuable central processing unit (CPU)processing time and repeated data copies may also be
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`necessary for the receiving host to place the data in an appropriate form at its intended
`destination.
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`The above description of layered protocol processing is simplified, as college-level
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`textbooks devoted primarily to this subject are available, such as Computer Networks, Third
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`Edition (1996) by Andrew S. Tanenbaum,whichis incorporated herein by reference. As
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`defined in that book, a computer network is an interconnected collection of autonomous
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`computers, such as internet and intranet devices, including local area networks (LANs), wide
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`. area networks (WANs), asynchronous transfer mode (ATM), ring or token ring, wired,
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`wireless, satellite or other means for providing communication capability between separate
`processors. A computer is defined herein to include a device having both logic and memory
`functions for processing data, while computers or hosts connected to a network are said to be
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`heterogeneousif they function according to different operating devices or communicate via
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`different architectures.
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`As networks grow increasingly popular and the information communicated thereby
`becomes increasingly complex and copious, the need for such protocol processing has
`increased.
`It is estimated that a large fraction of the processing power of a host CPU may be
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`devoted to controlling protocol processes, diminishing the ability of that CPU to perform other
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`tasks. Network interface cards have been developed to help with the lowest layers, such as the
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`physical and data link layers. It is also possible to increase protocol processing speed by
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`simply adding more processing power or CPUs according to conventional arrangements. This
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`solution, however, is both awkward and expensive. But the complexities presented by various
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`networks, protocols, architectures, operating devices and applications generally require
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`extensive processing to afford communication capability between various network hosts.
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`WISTRON CORP. EXHIBIT 1002.011
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`WISTRON CORP. EXHIBIT 1002.011
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`SUMMARY OF THE INVENTION
`Thecurrent invention provides a device for processing network communicationthatgreatly
`increases the speed ofthat processing and the efficiency oftransferring data being
`communicated. The invention has been achieved by questioning the long-standing practice of
`performing multilayered protocol processing on a general-purpose processor. The protocol
`processing method andarchitecture that results effectively collapses the layers of a connection-
`based, layered architecture such as TCP/IPinto a single wider layer whichis able to send
`network data moredirectly to and from a desired location or buffer on a host. This accelerated
`processing is provided to a host for both transmitting and receiving data, and so improves
`performance whether oneor both hosts involved in an exchange of information have such a
`feature.
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`The accelerated processing includes employing representative control instructions for a
`given messagethat allow data from the message to be processed via a fast-path which accesses
`message data directly at its source or delivers it directly to its intended destination. This fast-
`path bypasses conventional protocol processing of headers that accompanythe data. The fast-
`path employsa specialized microprocessor designed for processing network communication,
`avoiding the delays andpitfalls of conventional software layer processing, such as repeated
`copying andinterrupts to the CPU.
`Ineffect, the fast-path replaces the statcs that are
`traditionally found in several layers of a conventional network stack with a single state
`machine encompassingall those layers, in contrast to conventional rules that require rigorous
`differentiation and separation ofprotocol layers. The host retains a sequential protocol
`processing stack which can be employedfor setting up a fast-path connection or processing
`message exceptions. The specialized microprocessor and the host intelligently choose whether
`a given messageor portion ofa message is processed by the microprocessoror the host stack.
`One embodimentis a methodofgenerating a fast-path response to a packet received onto a
`network interface device where the packet is received over a TCP/IP network connection and
`where the TCP/IP network connectionis identified at least in part by a TCP source port, a TCP
`destination port, an IP source address, and an IP destination address. The method comprises:
`1) Examining the packet and determining from the packet the TCP source port, the TCP
`destination port, the IP source address, and the IP destination address; 2) Accessing an
`appropriate template header stored on the network interface device. The template header has
`TCP fields and IP fields; 3) Employing a finite state machine that implements both TCP
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`protocol processing and IP protocol processingto fill in the TCP fields and IP fields of the
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`template header; and 4) Transmitting the fast-path response from the network interface device.
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`The fast-path response includesthe filled in template header and a payload. Thefinite state
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`machinedoesnot entail a TCP protocol processing layer and a discrete IP protocol processing
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`layer where the TCP and IP layers are executed one after another in sequence. Rather, the
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`finite state machine covers both TCP andIP protocol processing layers.
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`In one embodiment, buffer descriptors that point to packets to be transmitted arc pushed
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`onto a plurality of transmit queues. A transmit sequencer pops the transmit queues and obtains
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`the buffer descriptors. The buffer descriptors are then used to retrieve the packets from buffers
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`where the packets are stored. The retrieved packets are then transmitted from the network
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`interface device. In one embodiment, there are two transmit queues, one having a higher
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`transmission priority than the other. Packets identified by buffer descriptors on the higher
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`priority transmit queue are transmitted from the network interface device before packets
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`identified by the lower priority transmit queue.
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`Other structures and methodsare disclosed in the detailed description below. This
`summary does not purport to define the invention. The invention is defined by the claims.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIG. 1 is a plan view diagram of a device of the present invention, including a host
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`computer having a communication-processing device for accelerating network
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`communication.
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`FIG.2 is a diagram of information flow for the host of FIG. 1 in processing network
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`communication, including a fast-path, a slow-path and a transfer of connection context
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`between the fast and slow-paths.
`FIG.3 is a flow chart of message receiving according to the presentinvention.
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`FIG. 4Ais a diagram of information flow for the host of FIG. 1 receiving a message packet
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`processed by the slow-path.
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`FIG.4Bis a diagram of information flow for the host of FIG. 1 receiving an initial message
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`packet processed by the fast-path.
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`FIG.4C is a diagram of information flow for the host of FIG. 4B receiving a subsequent
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`message packet processed by the fast-path.
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`WISTRON CORP. EXHIBIT 1002.013
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`FIG.4D is a diagram of information flow for the host of FIG. 4C receiving a message
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`packet having anerror that causes processingto revert to the slow-path.
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`FIG,5 is a diagram of information flow for the host of FIG. 1 transmitting a message by
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`either the fast or slow-paths.
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`FIG.6 is a diagram of information flow for a first embodimentof an intelligent network
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`interface card (INIC) associated with a client having a TCP/IP processing stack.
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`FIG. 7 is a diagram of hardwarelogic for the INIC embodiment shownin FIG.6, including
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`a packet control sequencer and a fly-by sequencer.
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`FIG.8 is a diagram ofthe fly-by sequencer of FIG. 7 for analyzing headerbytes as they are
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`received by the INIC.
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`FIG.9 is a diagram of information flow for a second embodiment of an INIC associated
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`with a server having a TCP/IP processing stack.
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`FIG. 10 is a diagram of a command driverinstalled in the host of FIG. 9 for creating and
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`controlling a communication control block for the fast-path.
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`FIG, 11 is a diagram of the TCP/IP stack and commanddriver of FIG. 10 configured for
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`NetBios communications.
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`FIG. 12 is a diagram of a communication exchange between the client of FIG. 6 and the
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`server of FIG. 9,
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`FIG. 13 is a diagram of hardware functions included in the INIC of FIG. 9.
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`FIG. 14 is a diagram of a trio of pipelined microprocessors included in the INIC of FIG. 13,
`including three phases with a processor in each phase.
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`FIG. 15Ais a diagram ofa first phase of the pipelined microprocessor of FIG. 14.
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`FIG. 15B is a diagram of a second phase of the pipelined microprocessorof FIG.14.
`FIG. 15C is a diagram ofa third phase of the pipelined microprocessor of FIG. 14.
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`FIG. 16 is a diagram of a plurality of queue storage units