' .
`
`5 .1.3 Register Usage
`
`There will be 512 registers available. The first 256 will be used for process contexts. The
`remaining 256 will be split between the 3 sequencers as follows:
`257 - 320: 64 for RCV general processing I main loop.
`321 - 384: 64 for XMT general processing I main loop.
`385 - 512: 128 for 3rd sequencer use.
`
`5.2 Receive Pr ocessing
`
`5.2.l Main Loop
`The following is a summary of the main loop of Receive:
`
`forever {
`while there are any Receive events {
`if(anew event) {
`if(no new context available)
`ignore the event;
`
`}
`call appropriate event handler to service the event;
`this may make a waiting process runnable or set up
`a new process to be run (get free context, hddr buffer,
`TCB buffer, set the context up).
`
`}
`while any process contexts are runable {
`run them by jumping to the start/resume address;
`if (process complete)
`free the context;
`
`}
`
`5.2.2 Receive Events
`The events that will be processed on a given context are:
`• accept a context
`•
`release a context command (from the host via Transmit)
`•
`release a context request (from Transmit)
`•
`receive a valid frame; this will actually become 2 events based on the received frame
`- receive an ACK, receive a segment
`•
`receive an "invalid" frame i.e. one that causes the TCB to be flushed to the host
`• a valid ACK needs to be sent (delayed ACK timer expiry).
`• There are expected to be the following sources of events:
`l. Receive input queue: it is expected that hardware will automatically DMA arriving
`frames into frame buffers and queue an event into a RCV-event queue.
`2. Timer event queue: expiration of a timer will queue an event into this queue.
`3. Transmit sequencer queue: for requests from the transmit processor.
`
`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence B. Boucher el al.
`Express Mail Label# EH756230105US
`
`52
`
`WISTRON CORP. EXHIBIT 1031.056
`
`

`

`For the sake of brevity the following only discusses receive-frame processing .
`
`5.2.3 Receive Details - Valid Context
`
`The base for the receive processing done by the INIC on an existing context is the fast(cid:173)
`path or "header prediction" code in the FreeBSD release. Thus the processing is divided
`into 3 parts: header validation and checksumming, TCP processing and subsequent SMB
`processing.
`
`5.2.3.1 Header Validation
`There is considerable hardware assist here. The first step in receive processing is to dma
`the frame header into an SRAM header buffer. It is useful for header validation to be
`implemented in conjunction with this dma by scanning the data as it flies by. The
`following tests need to be "passed":
`• MAC header: destination address is our MAC address (not MC or BC too), the
`Ethertype is IP.
`•
`IP header: header checksum is valid, header length = 5, IP length > header length,
`protocol = TCP, no fragmentation, destination IP is our IP address.
`• TCP header: checkswn is valid (incl. pseudo-header), header length = 5 or 8
`(timestamp option), length is valid, dest port = SMB or FTP data, no
`FIN/SYN/URG/PSWRST bits set, timestamp option is valid if present, segment is in
`sequence, the window size did not change, this is not a retransmission, it is a pure ACK
`or a pure receive segment, and most important, a valid context exists. The valid-context
`test is non-trivial in the amount of work involved to detennine it. Also note that·for pure
`ACKs, the window-size test will be relaxed. This is because initially the output PERSIST
`state is to be handled on the INIC.
`Many but perhaps not all of these tests will be performed in hardware - depending upon
`the embodiment
`
`5.2.3.2 TCP Processing
`
`Once a frame has passed the header validation tests, processing splits based on whether
`the frame is a pure ACK or a pure received segment.
`
`5.2.3.2.1 Pure RCV Packet
`
`The design is to split off headers into a small header buffer and pass the aligned data in
`separate large buffers. Since a frame bas been received, eventually some receiver process
`on the host will need to be informed. In the case of FTP, the frame is pure data and it is
`passed to the host immediately. This involves getting large buffers and dmaing the data
`into them, then setting the appropriate details in a small buffer that is used to notify the
`host. However for SMB, the INIC is performing reassembly of data when the fiiame
`consists of headers and data. So there may not yet be a complete SMB to pass to the host.
`In this case, a small buffer will be acquired and the header moved into it. If the received
`segment completes an SMB, then the procedures are pretty much as for FTP. Ifiit does
`not, then the scheme is to at least move the received data (not the headers) to the host to
`free the INIC buffers and to save latency. The list of in-progress host buffers is
`maintained in the TCB and moved to the header buffer when the SMB is complete.
`
`Provisional Pat. App. of AJacrit.ech, Inc.
`Inventors Laurence B. Boucher el al.
`Express Mail Label# EH756230105US
`
`53
`
`WISTRON CORP. EXHIBIT 1031.057
`
`

`

`

`

`

`

`• <
`
`5.3 Transmit Processing
`
`5.3. l Main Loop.
`
`The following is a summary of the main loop of Transmit:
`
`forever {
`while there are any Transmit events {
`if (a new event) {
`if(no new context available)
`ignore the event;
`
`}
`call appropriate event handler to service the event;
`this may make a waiting process runnable or set up
`a new process to be run (get free context, hddr buffer,
`TCB buffer, set the context up).
`
`}
`while any process contexts are runable {
`run them by jumping to the start/resume address;
`if (process complete)
`free the context;
`
`}
`
`5.3.2 Transmit Events
`
`The events that will be processed on a given context and their sources are:
`•
`accept a context (from the Host).
`•
`release a context command (from the Host).
`•
`release a context command (from Receive).
`• valid send request and window> 0 (from host or RCV sequencer).
`• valid send request and window= 0 (from host or RCV sequencer).
`•
`send a window update (host has accepted data).
`• persist timer expiration (persist timer).
`•
`context-release event e.g. window shrank (XMT processing or retransmission timer).
`•
`receive-release request ACK( from RCV sequencer).
`
`5.3.3 Transmit Details - Valid Context
`
`The following is an overview of the transmit flow:
`
`The host posts a transmit request to the INIC by filling in a command buffer with
`appropriate data pointers etc and posting it to the INIC via the Command Buffer Address
`register. Note that there is one host command buffer queue, but there are 4 phys.ical
`transmit lines. So each request needs to include an interface number as well as the context
`number. The INIC microcode will dma the command in and place it in l of 4 internal
`command queues which the transmit sequencer will work on. This is so that transmit
`processing can round-robin service these 4 queues to keep all 4 interfaces busy, and not
`
`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence B. Boucher et al.
`Express Mail Label # EH756230l05US
`
`56
`
`WISTRON CORP. EXHIBIT 1031.060
`
`

`

`•
`
`t
`
`let a highly-active interface lock out the others (which would happen with a single
`queue).
`The transmit request may be a segment that is less than the MSS, or it may be as.much as
`a full 64K SMB READ. Obviously the fonner request will go out as one segment, the
`latter as a number ofMSS-sized segments. The transmitting TCB must hold on tp the
`request until all data in it has been transmitted and acked. Appropriate pointers to do this
`will be kept in the TCB. A large buffer is acquired from the free buffer fifo, and the MAC
`and TCP/IP headers are created in it. It may be quicker/simpler to keep a basic frame
`header set up in the TCB and either dma directly this into the frame each time. Then data
`is dmad from host memory into the frame to create an MSS-sized segment. This dma also
`checksums the data. Then the checksum is adjusted for the pseudo-header and placed into
`the TCP header, and the frame is queued to the MAC transmit interface which may be
`controlled by the third sequencer. The final step is to update various window fieids etc in
`the TCB. Eventually either the entire request will have been sent and acked, or a
`retransmission timer will expire in which case the context is flushed to the host. In either
`case, the INIC will place a command response in the Response queue containing the
`command buffer handle from the original transmit command and appropriate st&tus.
`The above discussion has dealt how an actual transmit occurs. However the real
`challenge in the transmit processor is to determine whether it is appropriate to transmit at
`the time a transmit request arrives. There are many reasons not to transmit: the receiver's
`window size is <= 0, the Persist timer has expired, the amount to send is less thap a full
`segment and an ACK is expected I outstanding, the receiver's window is not half-open
`etc. Much of the transmit processing will be in determining these conditions.
`
`5.3.4 Transmit Details - No Valid Context
`
`The main difference between this and a context-based transmit is that the queued request
`here will already have the appropriate MAC and TCP/IP (or whatever) headers in the
`frame to be output. Also the request is guaranteed not to be greater than MSS-sized in
`length. So the processing is fairly simple. A large buffer is acquired and the frame is
`dmad into it, at which time the checksum is also calculated. If the frame is TCP/IP, the
`checkswn will be appropriately adjusted ifnecessary (pseudo-header etc) and pfaced in
`the TCP header. The frame is then queued to the appropriate MAC transmit intepace.
`Then the command is immediately responded to with appropriate status through the
`Response queue.
`
`5.3.5 Transmit Notes
`
`1. Slow-start: the INIC will handle the slow-start algorithm that is now a part of the
`TCP standard. This obviates waiting until the connection is sending a full-rate
`before passing it to the INIC.
`2. Window Probe vs Window Update: an explanation for posterity ....
`A Window Probe is sent from the sending TCB to the receiving TCB, and it means the
`sender has the receiver in PERSIST state. Persist state is entered when the receiver
`advertises a zero window. It is tbus the state of the transmitting TCB. In this state, be
`sends periodic window probes to the receiver in case an ACK from the receiver bas been
`lost The receiver will return his latest window size in the ACK.
`
`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence B. Boucher et al.
`Express Mail Label# EH756230105US
`
`57
`
`WISTRON CORP. EXHIBIT 1031.061
`
`

`

`A Window Update is sent from the receiving TCB to the sending TCB, usually to tell him
`that the receiving window has altered. It is mostly triggered by the upper layer when it
`accepts some data. This probably means the sending TCB is viewing the receiving TCB
`as being in PERSIST state.
`3. Persist state: it is designed to handle Persist state on the INIC. It seems
`unreasonable to throw a TCB back to the host just because its receiver advertised a
`zero window. This would nonnally be a transient situation, and would tent-1 to
`happen mostly with clients that do not support slow-start. Alternatively, tl:i.e code
`can easily be changed to throw the TCB back to the host as soon as a receiver
`advertises a zero window.
`4. MSS-sized frames: the INIC code will expect all transmit requests for which it has
`no TCB to not be greater than the MSS. If any request is, it will be dropped and an
`appropriate response status posted.
`S. Silly Window avoidance: as a receiver, the INIC will do the right thing here and
`not advertise small windows - this is easy. However it is necessary to also do
`things to avoid this as a sender, for the cases where a stupid client does advertise
`small windows. Without getting into too much detail here, the mechanism requires
`the INIC code to calculate the largest window advertisement ever advertised by the
`other end. It is an attempt to guess the size of the other end's receive buffer and
`assumes the other end never reduces the size of its receive buffer. See Stevens Vol.
`l pp. 325-326.
`
`6 The Utility Processor
`
`6.1 Summary
`
`The following is a summary of the main functions of the utility sequencer of the
`microprocessor:
`
`look at the event queues: Eventl3Type & Event23Type (we assume there will be an
`•
`event status bit for this -
`USE_EV13 and USE_EV23) in the events register; these
`are events from sequencers 1 and 2; they will mainly be XMIT requests from the XMT
`sequencer. Dequeue request and place the frame on the appropriate interface.
`• RCV-frame support: in the model, RCV is done through VinicReceiveO which is
`registered by the lower-edge driver, and is called at dispatch-level. This routine calls
`VinicTransferDataCompleteO to check if the xfer (possibly DMA) of the frame into host
`buffers is complete. Tue latter rtne is also called at dispatch level on a DMA-coi;npletion
`interrupt. It queues complete buffers to the RCV sequencer via the nonnal queue
`mechanism.
`• Other processes may also be employed here for supporting the RCV sequencer.
`•
`service the following registers: (this will probably involve micro-interrupts)
`Header Buffer Address register:
`buffers are 256 bytes long on 2?6-byte boundaries.
`31-8 - physical addr in host of a set of
`contiguous hddr buffers
`7-0 - number ofhddr buffers passed.
`Use contents to add to SmallHType queue
`
`Provisional Pat. App. of Alacritech, Inc.
`Inventors Laurence B. Boucher et al.
`Express Mail Label# EH75623010SUS
`
`58
`
`WISTRON CORP. EXHIBIT 1031.062
`
`

`

`...
`
`Data Buffer Handle & Data Buffer Address registers:
`buffers are 4K long aligned on 4K boundaries ...
`Use contents to add to the FreeType queue.
`
`Command Buffer Address register:
`buffers are multiple of32 bytes up to lK long (2**5 • 32)
`31-5 - physical add.r in host of cmd buffer
`4-0 - length of cmd in bytes/32
`(i.e. multiples of32 bytes)
`Points to host cmd; get FreeSType buffer and move
`command into it; queue to Xmit0-Xmit31'ype queues.
`
`Response Buffer Address register:
`buffers are 32 bytes long on 32-byte boundaries
`31-8 - physical addr in host of a set of
`contiguous resp buffers
`7-0 - number of resp buffers passed.
`Use contents to add to the ResponseType queue.
`
`low buffer threshold support: set approp bits in the ISR when the available-buffers
`•
`count in the various queues filled by the host falls below a threshold.
`
`6.2 Further Operations of the Utility Processor
`
`The utility processor of the microprocessor housed on the INIC is responsible for setting
`up and implementing all configuration space and memory mapped operations, and also as
`described below, for managing the debug interface.
`
`All data transfers, and other INlC initiated transfers will be done via OMA.
`Configuration space for both the network processor function and the utility processor
`function will define a single memory space for each. This memory space will d~fine the
`basic commwtlcation structure for the host. In general, writing to one of these memory
`locations will perform a request for service from the INIC. This is detailed in t.l1e
`memory description for each function. This section defines much of the operatibn of the
`Host interface, but should be read in conjunction with the Host lnterface Strategy for the
`Alacritech INIC to fully define the Host/INIC interface.
`
`Two registers, DMA hardware and an interrupt function comprise the INIC interface to
`the Host through PCI. The interrupt function is implemented via a four bit register
`(PCl_INT) tied to the PCI interrupt lines. This register is directly accessed by the
`microprocessor.
`
`THE MICROPROCESSOR uses two registers, the PCI_Data_Reg and the
`PCI_Address_Reg, to enable the Host to access Configuration Space and the memory
`space allocated to the INIC. These registers are not available to the HosL but are used by
`THE MICROPROCESSOR to enable Host reads and writes. The function of these two
`registers is as follows.
`
`Provisional Pat. App. of Alacritecb, Inc.
`Inventors Laurence B. Boucher et al.
`Express Mail Label# EH756230105US
`
`59
`
`WISTRON CORP. EXHIBIT 1031.063
`
`

`

`

`

`

`

`

`

`s:their"it:n“a""a.»r:s:"r:Eltrnl'fii
`
`processor will construct the data required and transfer it. Reads to this memory will
`generate 00 for data.
`
`6.2.2.1 Network Processor
`
`The following four byte registers, beginning at location 1100 of the network processor‘s
`allocated memory, are defined.
`
`00 e
`
`04 —
`
`Interrupt Status Pointer -- Initialized by the host to point to a four byte area
`where status is stored
`
`Interrupt Status — Returned status from host. Sent afier one or more
`status conditions have been reset. Also an interlock for storing any
`new status. Once status has been stored at the Interrupt Status Pointer
`location, no new status will be stored until the host writes the Interrupt
`Status Register. New status will be cred with any remitting
`uncleared status (as defined by the contents of the returned status)
`and stored again at the Interrupt Status Pointer location. Bits are
`as follows:
`Bit 31 -- ERR - Error bits are set
`Bit 30 v RCV — Receive has occurred
`
`Bit 29 — XMT # Transmit command complete
`Bit 25 — RMISS — Receive drop occurred due to no buffers
`
`08 —
`
`Interrupt Mask — Written by the host. Interrupts are masked for each
`of the bits in the interrupt status when the same bit in the mask
`register is set. When the Interrupt Mask register is Written and as
`a result a status bit is unmasked, an interrupt is generated. Also,
`when the Interrupt Status Register is written, enabling new status
`to be stored, when it is stored if a bit is stored that is not masked
`by the Interrupt Mask. an interrupt is generated.
`
`0C — Header Buffer Address — Written by host to pass a set of header buffers to the
`MC.
`
`10 — Data Buffer Handle — First register to be written by the Host to transfer a receive
`data buffer to the NC. This data is Host reference data. It is not used by the
`MC, it is returned with the data bufi'er. However, to insure integrity of the
`buffer, this register must be interlocked with the Data Buffer Address register.
`Once the Data Buffer Address register has been written, neither register can be
`written until after the Data Buffer Handle register has been read by THE
`MICROPROCESSOR.
`
`14 _ Data Buffer Address * Pointer to the data buffer being sent to the [NIC by the
`Host. Must be interlocked with the Data Buffer Handle
`
`register.
`
`18 n Command Buffer Address XMTO u Pointer to a set of command
`
`butters sent by the Host. THZE‘. MICROPROCESSOR will DMA the buffers to
`local DRAM found on the FreeSType queue and queue the Command
`
`vaisional Pet. App. at Maeritech. Inc.
`Inventors Laurence B. Boucher et 11.
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`
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`WISTRON CORP. EXHIBIT 1031.067
`
`

`

`
`
`.Iafl'i.est-rt?W’TJ'"1.2"»5"}H"l;“1""!iii!'53
`
`
`
`
`
`Buffer Address XMTO with the local address replacing the host
`Address.
`
`10 — Command Buffer Address SM'I‘l
`
`20 — Command Buffer Address SMT2
`
`24 a Command Buffer Address SMT3
`
`28 — Response Buffer Address -- Pointer to a set of reaponse butters sent
`by the Host. These will be heated in the same fashion as the
`Command Buffer Address registers.
`
`6.2.2.2 Utility Processor
`
`Ending status will be handled by the utility processor in the same fashion as it is handled
`by the network processor. At present tw0 ending status conditions are defined B31 —
`command complete, and B30 -— error. When end status is stored an interrupt is
`generated.
`
`Two additional registers are defined, Command Pointer and Data Pointer. The Host is
`responsible for insuring that the Data Pointer is valid and points to sufficient memory
`before storing a command pointer. Storing a command pointer initiates command decode
`and execution by the debug processor. The Host must not modify either command or
`Data Pointer until ending status has been received, at which point a new command may
`be initiated. Memory space is write only by the Host, reads will receive 00. The format
`is as follows:
`
`00 —
`
`Interrupt Status Pointer - Initialized by the host to point to a four byte area
`where status is stored
`
`04 —
`
`Interrupt Status — Returned steals from host. Sent after one or more
`status conditions have been reset. Also an interlock for storing any
`new status. Once status has been stored at the Interrupt Status Pointer
`location, no new status will be stored until the host writes the Interrupt
`Status Register. New status will be ored with any remaining
`nucleated status (as defined by the contents of the returned status)
`and stored again at the Interrupt Status Pointer location. Bits are
`as follows:
`
`Bit 31 — CC — Command Complete
`Bit 30 — ERR — Error
`Bit29 —- Transmit Processor Halted
`BitQB — Receive Processor Halted
`
`Bit27 — Utility Processor Halted
`
`08 -
`
`Interrupt Mask — Written by the host. Interrupts are masked for each
`of the bits in the interrupt status when the same bit in the mask
`register is set. When the Interrupt Mask register is written and as
`a result a status bit is unmasked, an interrupt is generated. Also,
`
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`Inventors laurenoe B. Boucher et at.
`Express Mail Label it EH756230105US
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`WISTRON CORP. EXHIBIT 1031.068
`
`

`

`when the Interrupt Status Register is written, enabling new status
`to be stored, when it is stored if a bit is stored that is not masked
`by the Interrupt Mask, an interrupt is generated.
`
`0C — Command Pointer — Points to command to be executed. Storing
`this pointer initiates command decode and execution.
`
`10 — Data Pointer — Points to the data buffer. This is used for both read and write data,
`determined by the conunand function.
`:
`
`7 Debug Interface
`
`In order to provide a mechanism to debug the microcode running on the microprocessor
`sequencers, a debug process has been defined which will run on the utility sequencer.
`This processor will interface with a control program on the host processor over PCI.
`
`7.1
`
`PCI Interface
`
`This interface is defined in the combination of the Utility Processor and the Host
`Interface Strategy sections, above.
`
`7.2 Command Format
`
`The first byte of the command, the command byte, defines the structure of the remainder
`of the command. The first five bits of the command byte are the command itself. The
`nest bit is used to Specify an alternate processor, and the last two hits specify which
`processors are intended for the command.
`
`7.2.1 Command Byte
`
`7 ,_ 3
`Command
`
`2
`Alt. Proc.
`
`1 - 0
`Processor
`
`fittill‘3
`
`
`
`if...fish‘EF'If]"Ll?"'1E1it'llH?
`
`7.2.2 Processor Bits
`
`00 — Any Processor
`01 _ Transmit Processor
`10 — Receive Processor
`
`1] — Utility Processor
`
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`
`

`

`.~ 4
`
`it}if‘5][Til3Ell
`
`
`.r‘i15.1:"it'53'£1"if'"fitill]
`
`7.2.3 Alternate Processor
`
`This bit defines which processor should handle debug processing if the utility processor
`is defined as the processor in debug.
`
`0 — Transmit Processor
`1 — Receive Processor
`
`7.2.4 Single Byte Commands
`
`00 — Halt
`
`This command asynchronously halts the processor.
`
`08 — Run
`
`This command starts the processor.
`
`IO—Step
`
`This command steps the processor.
`
`7.2.5 Eight Byte Commands
`
`18 — Break
`
`0
`Command
`
`1
`Reserved
`
`2—3
`Count
`
`4‘7
`Address
`
`This command sets a stop at the specified address. A count of 1 causes the specified
`processor to halt the first time it executes the instruction. A count of 2 or more causes the
`processor to halt after that number of executions. The processor is halted just before
`executing the instruction. A count ofO does not halt the processor, but causes a_ sync
`signal to be generated. If a second processor is set to the same break address, the count
`data from the first break request is used, and each time either processor executes the
`instruction the count is decremented.
`
`20 — Reset Break
`
`0
`Command
`
`1 - 3
`Reserved
`
`4 e 7
`Address
`
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`
`

`

`I'Eil
`
`
`
`at".it‘s-i1“Ii?flitT"i152:{It25]1.?'EilHi.
`
`This command resets a previously set break point at the specified address. Reset break
`fully resets that address. If multiple processors Were set to that break point, all Will be
`reset.
`
`‘28 — Dump
`
`0
`
`1
`
`Command
`
`Descriptor
`
`2 - 3
`
`Count
`
`4 — 7
`
`Address
`
`This command transfers to the host the contents of the descriptor. For descriptors larger
`than four bytes, :1 count, in four byte increments is specified. For descriptors utilizing an
`address the address field is specified.
`
`7.2.6 Descriptor
`
`00 v Register
`
`This descriptor uses both count and address fields. Both fields are four byte based (3
`count of 1 transfers four bytes).
`
`01 — Sram
`
`This descriptor uses both count and address fields. Count is in four byte blocks. Address
`is in bytes, but if it is not four byte aligned, it is forced to the lower four byte aligned
`address.
`
`02 — Drain
`
`This descriptor uses both count and address fields. Count is in four byte blocks. Address
`is in bytes, but if it is not four byte aligned, it is forced to the lower four byte aligned
`address
`
`03 — Cstore
`
`This descriptor uses both count and address fields. Count is in four byte blocks. Address
`is in bytes, but if it is not four byte aligned, it is forced to the lower four byte aligned
`address
`
`Stand-alone descriptors:
`
`The following descriptors do not use either the count or address fields. They transfer the
`contents of the referenced register.
`
`04 — CPU‘STATUS
`
`IDS-PC
`
`Provisional Pat. App. of Alaeritech, Inc.
`Inventors Laurence B. Beecher or. 3].
`Express Mail Label d EH756230105US
`
`67
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`WISTRON CORP. EXHIBIT 1031.071
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`WISTRON CORP. EXHIBIT 1031.071
`
`

`

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`431':Iifiu’i‘r'lr"a?“iif“'IE1:HHT5'53Eliiii“53
`
`05 — ADDR§REGA
`
`07 , ADDR_REGB
`
`08 — RAM_BASE
`
`09 — FILE_BASE
`
`0A — INSTR_REG_L
`
`OB - mSTR_REG_H
`
`0C — MAC_DATA
`
`0D — DMAfiEVENT
`
`OE — MISC_EVENT
`
`0F — Q_IN_RDY
`
`10 —- CLOUT_RDY
`
`11 — LOCK. STATUS
`
`12 — STACK - This returns 12 bytes
`
`13 — Sense _ Reg
`
`This register contains four bytes of data. If error status is posted for a command, if the
`next command that is issued reads this register, a code describing the error in more detail
`may be obtained. If any command other than a dump of this register is issued after error
`status, sense information will be reset.
`
`30 # Load
`
`0
`Command
`
`1
`Descriptor
`
`2 — 3
`Count
`
`4 ~- 7
`Address
`
`This command transfers from the host the contents of the descriptor. For descriptors
`larger than four bytes, a count, in four byte increments is specified. For deecrip‘tors
`utilizing an address the address field is specified.
`
`7.2.7 Descriptor
`
`00 4 Register
`
`This descriptor uses both count and address fields. Both fields are four byte based.
`
`Provisional Pat. App. of Macriteeh. Inc.
`Inventors Laurence B. Boucher et a1.
`
`Express Mail Label if EH756230105US
`
`,
`
`68
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`WISTRON CORP. EXHIBIT 1031.072
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`WISTRON CORP. EXHIBIT 1031.072
`
`

`

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`£1TE'ih“i“t'E-‘E~hfi:‘.=~ir'“iii:anH"E7‘iliFE][W31
`
`01—Sram
`
`This descriptor uses both count and address fields. Count is in four byte blocks. . Address
`is in bytes, but if it is not four byte aligned, it is forced to the lower four byte aligned
`address.
`
`02-Dram
`
`This descriptor uses both count and address fields. Count is in four byte blocks. Address
`is in bytes, but if it is not four byte aligned, it is forced to the lower four byte aligned
`address
`
`03 — Cstore
`
`This descriptor uses both count and address fields. Count is in four byte blocks. Address
`is in bytes, but if it is not four byte aligned, it is forced to the lower four byte aligned
`address. This applies to WCS only.
`
`Stand-alone descriptors:
`
`The following descriptors do not use either the count or address fields. They transfer the
`contents of the referenced register.
`
`04 -— ADDR_REGA
`
`05 ~ ADDR_REGB
`
`06 «- RAM_BASE
`
`o7 — FILE_BASE
`
`08 — MACpATA
`
`09 -— Q_[N_RDY
`
`0A — O_0UT_.RDY
`
`OB -» DBG_ADDR
`
`38 — Map
`
`This command allows an instruction in ROM to be replaced by an instruction in WCS.
`The new instruction will be located in the Host buffer. It will be stored in the first eight
`bytes of the buffer, with the high bits unused. To rose: a mapped out instruction, map it
`to location 00.
`
`0
`Command
`
`1 - 3
`Address to
`Map To
`
`4 — 7
`Address to
`Map Our
`
`Provisional Pat. App. of Alacritech. Inc.
`Inventors laurence B. Bounher et 31.
`Express Mail Label # EH756230£05US
`
`69
`
`WISTRON CORP. EXHIBIT 1031.073
`
`WISTRON CORP. EXHIBIT 1031.073
`
`

`

`.-.i
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`it”.ifu‘iittiii'fili'15"”3E1“Eifl'ii'flllt'iilii‘uiiifli.
`
`
`
`
`
`8
`
`HARDWARE SPECIFICATION
`
`FEATURES
`
`- Peripheral Component Interconnect (PCI) Interface
`
`- Universal PCl interface supports both 5.0V and 3.3V signaling environments.
`
`— Supports both 32-bit and 64 bit PCI interface.
`
`- Supports PCI clock frequencies from lSMI-Iz to 661MHz
`
`- High perfomtanoe bus mastering architecuire.
`
`- Host mentor)»r based communications reduce register accesses.
`
`- Host memory based interrupt status word reduces register reeds.
`
`- Plug and Play compatible.
`
`- PCI specification revision 2.1 compliant.
`
`- PCI bursts up to 512 bytes.
`
`- supports cache line operations up to 123 bytes.
`
`- Both big-endian and little-endian byte alignments supported.
`
`- Supports Expansion ROM.
`
`. Network Interface
`
`- Four internal 802.3 and ethernet compliant Macs.
`
`- Media Independent Interface (Mil) supports external PHYS.
`
`— lOBASB—T, lOGBASE—TXIFX and 100BASE-T4 supported.
`
`— Full and halfduplex modes supported.
`
`- Automatic PHY status polling notifies system of status change.
`~ Provides SNMP statistics counters.
`
`~ Supports broadcast and multicast packets.
`
`- Provides promiscuous mode for network monitoring or nmltiple unicast address detection.
`
`— Supports “huge packets” up to 32KB.
`
`- Mac—layer loop-back test mode.
`
`- Supports auto-negotiating Phys.
`
`Provisional Pat. App. of AlaCritOCh. Inc.
`Inventors Laurence B. Boucher et a1.
`Express Mail Label it EH756230I05US
`
`70
`
`WISTRON CORP. EXHIBIT 1031.074
`
`WISTRON CORP. EXHIBIT 1031.074
`
`

`

`
`
`
`
`.fh-"it"5?EP-‘ll?"iii;fl:3"ET“341I33Hill"5.!
`
`ll‘ -
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`
`- Memory Interface
`
`- External Dram buffering of tranmit and receive packets.
`
`- Bufi'ering configurable as 4MB, 3MB. 16MB or 32MB.
`
`- 32-bit interface supports throughput of 224MBJ'5
`
`- Supports external FLASH ROM up to 4 MB, for diskless boot applications.
`
`- Supports external serial EEPROM for custom configuration and Mac addrcswc.
`
`- Protocol Processor
`
`- High speed. custom, 32—bit processor executes 66 million instructions per second.
`
`~ Processes IP, TCP and NETBIOS protocols.
`
`- Supports up to 256 resident 'FCPIIP contexts.
`
`- Writable control store (WCS) allows field updates for feature enhancements.
`
`0 Power
`
`— 3.3V chip operation.
`
`- PCI controlled 5.0V13.3V U0 cell operation.
`
`It Packaging
`
`- 212-pin plastic ball grid array.
`
`- 91 PCI signals.
`
`- 68 MI] signals.
`
`- 58 external memory signals.
`
`— l clock signal.
`
`— 54 signals split between power and ground.
`
`- 272 total pins.
`
`Provisional Pat. App. of Alacriteclt, Inc.
`Inventors Lamcncc B. Boucher ct 3].
`Express Mail Label all EH756230105US
`
`'Il
`
`WISTRON CORP. EXHIBIT 1031.075
`
`WISTRON CORP. EXHIBIT 1031.075
`
`

`

`"Eli-'25I?filltillHIE-l
`
`t.3g:
`
`
`
`
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`
`GENERAL DESCRIPTION
`
`The microprocessor is a 32-bit, full-duplex, four channel. 10f lilo-Megabit per second [Mbpst Intelligent
`Network Interface Controller. designed to provide high-speed protocol processing for server applications. It
`combines the functions of a standard network interface controller and a protocol processor within a single
`chip. Although designed specifically for server applications. The microprocessor can. be used by; PCs.
`workstations and routers or anywhere that: 'I‘CPIIP protocols are being utilized.
`
`When combined with four 302.3!MII compliant Phys and Synchronous Dram (SDrarn), the INIC comprises
`four complete ethernet nodes. It contains four 802.3!ethemet compliant Macs, a PCI Bus Interface Unit (BIU),
`a memory controller. transmit fifos, receive fifos and a custom 'I‘CPFIPINETBIOS protocol processor. The
`[MC supports lUBase-T . IOOBase-TX, Immoe—FX and lOflBm-Ttt via the M11 interface attachment of
`appropriate Phys.
`
`The INIC Macs provide statistical information that may be used for SNMP. The Macs operate in promiswous
`mode allowing the [NIC to function as a network monitor, receive broadcast and multicast packets and
`implement multiple Mac addresses for each node.
`
`Any 802.3!MII compliant PHY can be utilized. allowing the lNIC to support lflBASE-T, IOBA