Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 1 of 46
`
`EXHIBIT D
`
`to Declaration of Dr. Gregory L. Chesson in Support of Microsoft’s
`Opposition to Alacritech’s Motion for Preliminary Injunction
`
`WISTRON CORP. EXHIBIT 1024.001
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 2 of 46
`-r::!!'l Protocol Engine,s
`iD §4 Incorporated
`
`Protocol Engine® Handbook
`
`1
`
`WISTRON CORP. EXHIBIT 1024.002
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 3 of 46
`
`( _:
`
`"(,.
`
`.
`
`/
`
`j
`
`2
`
`WISTRON CORP. EXHIBIT 1024.003
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 4 of 46
`
`> 4 Protocol Engines
`b C
`/ncorporill1d
`
`•
`
`Silicon Graphics
`CDmpUsr Systems
`
`This document contains copyrighted information proprietary to
`Protocol Engines8 Inc. and Silicon Graphics• Computer Systems.
`The information in this document is accurate as of the publication date only, and is subject
`to change wit~ut notice. PEl, SGI, and the authors of the attached documents are not responsible
`for any inadvertent errors, or any consequences resulting from the use of any information contained herein.
`
`( __
`
`\
`
`Copyright© 1990, Protocol Engines8 Inc. and Silicon Graphics• Computer Systems.
`
`3
`
`WISTRON CORP. EXHIBIT 1024.004
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 5 of 46
`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 5 of 46
`
`l
`L
`
`Beams3d
`
`4
`
`WISTRON CORP. EXHIBIT 1024.005
`
`WISTRON CORP. EXHIBIT 1024.005
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 6 of 46
`
`•
`
`-
`
`4 Protocol Engines
`-
`lru:orportlled
`
`PE Chipset
`
`PRELIMINARY
`(subject to change without notice)
`
`to 200 Mbps end-to-end
`
`1. Features
`• provides up
`throughput
`• hardware support f(X' XTP, TCP, ISO, and
`XNS checksums
`• programmable support for multiple protocols
`• supports multicast, priority sorting, and other
`advanced features.
`
`2. General Description
`The Protocol Engine • chipset offers real-time protocol
`processing for high-speed networks. A wide range of
`cost-performance subsystem solutions are available
`through various configurations based on the PE
`ChipseL The chipset (shown in Figure 1) consists of
`four chips: MPORT, HPORT, BCIL, and CP. A
`basic configuration consists of MPORT, HPORT, and
`BCIL
`MPORT (MAC Port) provides an intelligent medium
`~K:cess control (MAC) layer interface to FDDI and
`other generic MACs. MPORT performs various tasks
`in its datapatb, including checksumming, protocol
`ilentification, and address recognition. One to three
`MAC interfaces are supJXXted by the architecture. A
`
`high-speed MAC, such as FDDI, requires a dedicated
`MPORT. Lower-speed MACs, such as Ethernet, can
`share an MPORT with the aid of external logic and
`buffering.
`HPORT (Host Port) provides an intelligent direct
`memory access (DMA) engine with a synchronous
`bus inttrface (HBus) to the hosL The· HBus is
`C<lllpatible with industry standard buses (e.g., SBus,
`VME) and is easily inttzfaced to others. HPORT can
`interface to a data soun:e (e.g., sensor) or a data sink
`(e.g., image buffer). One or two HPORT chips can
`be used in the PE subsystem. The architecture
`supports combinations of MPORT and HPORT chips
`up to a combined maximum of four.
`BCIL (Buffer Controller) manages the external direct
`random access memory (DRAM) for buffering fmmes
`and storing state infonnation. The chipset assumes the
`use of generic, page-mode DRAM chips.
`CP (Control Processor) provides low latency, high
`perfonnance processing for management functions,
`error recovery. and protocol processing functions not
`handled by MPORT, HPORT, or BCIL components.
`The multi-thread instruction architecture of this chip
`minimizes context switching. and branching overhead,
`and maximizes proces5Ql" efficiency.
`
`T..,_.._.
`
`'Oc:rabor 1!1!10
`
`To lilAC 1'1.- lilAC
`
`Figure 1. PE Chipset.
`
`5
`
`1
`
`WISTRON CORP. EXHIBIT 1024.006
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 7 of 46
`
`3. Basic Configuration
`A basic configuration of the PE Chipset uses the
`(Figure 2
`HPORT, MPORT, and BCIL chips.
`illusttates a basic configuration.) In addition to these
`three chips, two memory blocks are required: Control
`Memory (CM) and Network Buffer Memory (NBM).
`Control Memory is based on static, random access
`memory (SRAM); Network Buffer Memory is based
`on dynamic, random access memory (DRAM).
`
`3.1 HPORT
`Data arriving from the host is processed by Host Port
`(HPOR'lj. HPORT packetizes the dala into proper
`into the
`inserts proper values
`packet size and
`number,
`sequence
`(e.g.,
`fields
`header/ttailer
`checksum). The packets are temporarily sURd in
`Network Buffer Memory before they are sent to the
`MAC layer by MPORT, when the next service
`opportunity arrives.
`
`3.2 MPORT
`MAC Port (MPOR'l) provides a duplex interface to
`one medium access control (MAC) device. Each
`received frame is processed appropriately depending
`on its. address and protocol type. Various address
`types are supported, including local, broad<:aSt. and
`multicast addresses, as well as a number of wild card
`conditions. MPORT executes checksumming, byte
`swapping, and other data manipulations, while data
`the datapath. The header/trailer
`through
`flows
`information is filtered to an on-chip Packet Processor.
`The packet processor is a programmable micro(cid:173)
`the header/ttailer dala and
`It processes
`engine.
`decides the disposition of the packet.
`The received packets are stored in Network Buffer
`Memory. A number of programmable modes are
`provided for deciding if and how packets will be
`further processed. "Raw data" mode causes packets to
`be delivered to the host via HPORT without further
`processing. This allows the use of existing protocol
`codes with ·minimum or no modification. Other modes
`activate further processing of the packets in order to
`achieve faster end-to-end throughpuL The chipset acts
`as a fasapath protocol processor. Software must be
`provided (in CP, in the host. or in another nearby
`CPU) to do non-faslpath processing.
`
`3.3 BCTL
`The Buffer Controller (BCIL) both manages Network
`Buffer Memory and arbittates access to iL BCIL
`generates DRAM control signals and address signals
`
`' Oclabcor 1990
`
`PEChipset
`
`for reading from and writing to Network Buffer
`Memory. BCIL also performs periodic DRAM
`refresh cycles.
`
`3.4 Control Memory
`Control Memory (CM) is used for storing control
`infmnation. It is accessed by the MPORT, HPORT,
`and BCIL chips for storing/retrieving various dala
`structures, including tables, maps, control blocks, and
`com~d blocks. The locations where the dala
`structures reside are programmable through on-chip
`registers. The structures are accessed through page
`registers and pointers.
`Control Memory is accessible by words only. (Each
`word is 32 bits.) Optional byte parity can be included.
`The maximum Control Memory size supported by the
`chipset is 25& words. For an end-host with two
`thousand active connections, a minimum of 32k words
`of Control Memory is recommended.
`
`3.5 Network Buffer Memory
`Network Buffer Memory (NBM) is used to buffer
`network traffic. Both received frames and transmitting
`frames are buffered in Network BUffer Memory.
`Like Control Memory, Network Buffer Memory is
`accessible by 32-bit words only. Network Buffer
`Memory can be constructed by 256kx4 or 1Mx4
`DRAMs. It is organized by modules. Each module is
`32-bits wide with four bits of optional byte .parity. Up
`to four modules are supported in each bank of
`memory. Up to two banks are supported by this
`architecture. In a non-interleaved NBM (Network
`Buffer Memory) structure, one bank of memory is
`used. In an interleaved memory, two are used. The
`minimum Network Buffer Memory size is 256k words
`(1 MByte) and the maximum size is 8M words (32
`MBytes).
`In addition to being a temporary repository for frame
`data, Network Buffer Memory is also used for storing
`the bulk of context-related information fOI' each
`connection. Various dala structures reside in Network
`Buffer Memory to facilitate storing, organizing, and
`moving data. The dala structures, their locations, and
`their sizes are programmable via the on-chip registers
`in MPORT, HPORT, and BCIL.
`
`3.6 OPTIONS
`BCIL can have optional Instruction Memory (BIM)
`connected to it direcdy. This memory provides an
`expansion area for firmware that overflows the on(cid:173)
`chip instruction memory.
`
`2
`
`SA
`
`WISTRON CORP. EXHIBIT 1024.007
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 8 of 46
`
`PEChipset
`
`c
`
`To/From Haet
`
`BCTL
`
`IIPOAT
`
`•BIM
`
`;
`
`:"" ............ .
`,_.., ;
`................ ,
`
`iiiiAu•! =--·
`
`C8uo
`
`DBue
`
`To MAC From MAC
`
`Figure 2. Basic Configuration.
`
`ToJFrom Hoot
`
`1
`
`HPORT
`
`Figure 3. An Extended Configuration lor Dual-anach FDDI.
`
`9 Ocaobor 1990
`
`6
`
`3
`
`WISTRON CORP. EXHIBIT 1024.008
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 9 of 46
`
`4. Extended Configurations
`A number of extended coofiguratims are available.
`These involve adding a CP chip and/ol inaeasing the
`number ofMPORT and/or HPORT chips.
`
`4.1 CP
`Addition of a CP chip to the basic configuration
`provides significant performance enhancement. As
`shown in Figures 3. 4, and s. CP is connected to CBus
`and DBus. These two buses provide CP direct access
`to the memories that store pertinent information for
`protocol processing. With multi-thread architecture,
`CP is able to attend to multiple processes without
`incmring context switching overhead. CP also bas
`to perform routine network
`dedicated hardware
`processing functions.
`Like the chips of the basic contigulation, CP can own
`some of the clara structures in Network Buffer
`Memory (NBM).
`
`4.2 Two MPORTs
`A second MPORT can be added to the basic
`configuration. It could be connected to a second MAC
`
`PEChipset
`
`layer device that may be the same type as the first one,
`or may be different This configmation could be ~
`to construct a dual MAC. dual aaacb FDDI station in
`ordel' to offez a higher level of redlUldancy. (See
`Figure 3.) Or. the second MPORT could be used as a
`gateway to connect two networks as illusarated in
`Figure 4. In this configuration. the packets received
`from one MAC go to Network Buffez Memory and
`then are delivered to the other MPORT. which
`tmnsfers the data to the other MAC. 1be packets are
`not~ by HPORT and are not passed over the
`HBus. ·and hence do not require any host intervention.
`A third use for a second MPORT could be to CODSirUCt
`a bridge. This cooJd be done by connecting the
`second MPORT to a different type of MAC than the
`first
`
`4.3 Three MPORTs
`A third MPORT can be added thus making it possible
`to implement any ccmbination of the above. For
`example. a three MPORT system can be configured
`for both dual MAC FDDI and a bridge/gateway
`application.
`
`(~,
`
`Figure 4. An Extended Configuration for an FDDI Gateway.
`
`Dllua
`
`7
`
`4
`
`WISTRON CORP. EXHIBIT 1024.009
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 10 of 46
`
`PEChipset
`
`4.4 Two HPORTs
`the basic
`A second HPORT can be added to
`configuratian. This HPORT can be connected to a
`data sink m a data source. or both. Typical data
`analog-to-digital
`sensors and
`include
`soun:es
`converters with adequate buffers. A typical data sink
`is an image buffer. A typical data sink and source is a
`frame buffec m mass storage device. Data can be fed
`directly into the data sink/source device via the second
`the host bus. This
`HPORT without uaversing
`significantly improves the data throughput to these
`devices.
`The second HPORT could also be connected to the
`router backplane. 1bis configuration provides high
`performance routing fer high bandwidth network
`media. (See Figure 5.)
`
`Figure 5. Extended ConftguraUon with two HPORTL
`
`(_
`
`8
`
`s
`
`WISTRON CORP. EXHIBIT 1024.010
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 11 of 46
`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 11 of 46
`
`wow
`
`9
`
`WISTRON CORP. EXHIBIT 1024.011
`
`WISTRON CORP. EXHIBIT 1024.011
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 12 of 46
`
`r
`r
`
`zc Protocol Engines
`I11Ct1f71D't11ed
`2Q
`
`PREUMINARY
`(subject to change wi1hout notice)
`
`MPORT
`
`1. Features
`• one micron CMOS technology
`• 33MHz system clock
`• synchronization to external MAC device clock.
`upto2SMHz
`• asynchronous MAC device clock and system
`clock
`• two simplex. 9-bit channels: one to and one
`from MAC device
`• handles peak dala rate to 200M bits/s for each
`simplex channel
`• separate. on-chip receiver and
`FIFOs
`• 32-bit packet processing engine
`• hardware support for XlP, TCP, ISO. and
`XNS checksums
`• pogrammable support for multiple protocols
`
`ttansmitter
`
`2. General Description
`MAC Port (MPOR1) of the Protocol Engine • chipset
`is a programmable controller that supports high-speed
`
`~···
`
`protocol processing. It provides hardware interfaces
`to the medium access control (MAC) device, the data
`bus (DBus). and the conll'Ol bus (CBus).
`The MAC interface provides a b~wide, duplex data
`channel to the MAC device. This channel is operated
`by the MAC device clock, up to 2S MHz. The MAC
`device clock may be asynchronous to the PB Chipset's
`system clock.
`the DBus interlace, MPORT accesses
`11uough
`Netwolt Buffer Memory to stme received frames and
`to retrieve frames for transmission.
`interlace, MPORT accesses
`the CBus
`Through
`, Conll'Ol Memory and sencWreceives conll'Ol messages
`to peer devices.
`With these three interfaces. an on-chip pogrammable
`processor. and datapath functional units, MPORT
`performs checksumming. header processing. packet
`demultiplexing, and other functions. The user has the
`freedom to program a variety of protocols and
`policies. limited to the on-chip hardware resources.
`
`Te lilAC " - lilAC
`
`Flglft1. PE Chipset.
`
`10
`
`9~1990
`
`1
`
`WISTRON CORP. EXHIBIT 1024.012
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 13 of 46
`
`MPORT
`
`~
`
`PIN
`
`CAD
`CDP
`ems
`am
`CWi"'
`CRQ
`CGf'
`CEiR
`csr
`
`CSCM
`C:SBCTL
`CSlP
`DDATA
`DDP
`DTG
`DRQ
`i5GT
`i5WR
`Ma.IC
`MDO
`MPO
`MDI
`MPI
`Olben
`ax
`RE8BT
`TiS
`TCIC
`TMS
`IDI
`TDO
`TRST
`
`Fwu:tion
`
`Type
`
`#ofpins
`
`CBua~
`CBua~pujly
`CBua lllldma lbobe
`CBualad
`CBuswrile
`CBuan:qaat
`CBusput
`CBusemr
`CBu ac1ec:t in
`CBua aelect OUl for CM (CClllbOl memory)
`CBus aelect OUl for BCil. (bufferc:cDnlUer)
`CBus IClecl OUl for CP (CClllbOl poceuor)
`
`DBuadala
`DBua dala pujly
`DButaa
`DBua JeqDell
`DBuaana
`DBuawrila
`
`MAC cl8vice dock
`MAC cilia CIUipUl
`MAC pujly OUiplll
`MAC dala iaput
`MAC pujly iDpat
`TBD
`
`Clock
`Reset
`
`Tat iDicrmlscm
`Tatcloc:k
`Tat mode select
`Taadalaia
`Ta&dalaout
`Taaract
`
`Table1. IIPORT Pin SUmmary.
`
`32
`4
`
`1
`1
`1
`1
`
`32
`4
`4
`
`1
`8
`1
`8
`
`lAO
`LtO
`LtO
`LtO
`lAO
`0
`I
`LtO
`I
`0
`0
`0
`
`lAO
`LtO
`LtO
`0
`I
`0
`
`I
`0
`0
`I
`I
`
`I
`I
`
`I
`I
`I
`I
`0
`I
`
`9 Ocllabor 19!10
`
`11
`
`3
`
`WISTRON CORP. EXHIBIT 1024.013
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 14 of 46
`
`MPORT
`
`CBusPins
`
`Symbol
`CAD[31:0]
`
`CDP[3:0]
`
`CADS
`
`CiiD
`
`CWR
`
`CRQ
`
`CGT
`
`CBRR
`
`csr
`
`CSCM
`
`CSBCTI.
`
`CSCP
`
`,Oct.-1!190
`
`J/0 Descripdoo
`J/0 Address/data bus. It is ai-stared when CBus is not granted. When CBus is granted,
`address is driven onto this bus dming address cycle, and dala is driven onto this bus
`during dala cycle. 1be data is driven by MPORT in a write transfer, or it is driven by
`a slave device in a read ttansfer.
`
`J/0 Byte parity for the CAD(31:0] bus. CDP has the same timing as CAD[31:0]. CDP[3]
`covezs the CAD(31:24], and so on.
`
`J/0 Address Slrobe. When CBus is granted, it is an· outpuL lls assertion indicates that
`address is being driven onto CAD[31:0] by MPORT.
`When CBus is not granted, it is an input. lls assertion along with the assertion of
`CSI indicates that CAD[31:0] carries address driven by the current CBus master to
`address a slave register on MPORT.
`
`1/0 Read strobe. When CBus is granted, it is an outpUL Its assertion indicates a read
`transfer.
`When CBus is not granted, it is an inpuL Its asseztion indicates that the current CBus
`master is making a read transfer.
`
`1/0 Write sttobe. When CBus is granted, it is an outpuL Its assertion indicates a write
`transfer.
`When CBus is not granted, it is an input. Its asSC21ion indicates that the current CBus
`master is making a write transfer.
`
`0
`
`I
`
`CBus request. This signal is asserted to request CBus mastership. It may remain
`asserted to request multiple transactions fm- a bus tenure.
`
`CBus granL This input indicates the granting of CBus mastership.
`
`J/0 CBus error. This pin is both input and output. The~ drain, active low output
`reports CBus error to the peer devices which have CERR pins connected together.
`The input circuitry detects CBus errors reported by any device connected on CBus.
`
`I
`
`0
`
`0
`
`0
`
`Olip select inpuL 1be assertion of this pin indicates that the current CBus master is
`making a transaction with MPORT, as a slave deviCe.
`
`Control Memm-y selecL It is ai-stated when CBus is not granted. It is asserted when
`CBus is granted and MPORT is addressing Control Memory.
`
`Ben. selecL It is ai-stated when CBus is not granted. It is asserted when CBus is
`granted and MPORT is addressing BC'IL.
`
`CP select. It is ai-stated when CBus is not granted. It is asserted when CBus is
`granted and MPORT is addressing CP.
`
`12
`
`4
`
`WISTRON CORP. EXHIBIT 1024.014
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 15 of 46
`
`MPORT
`
`c···
`
`'·· f
`
`DBus Pius
`
`Symbol
`DDATA[31:0}
`
`DDP[3:0]
`
`DTG[3:0]
`
`DRQ
`
`DGT
`
`i5Wif
`
`i <·;. ~­
`.. ,.
`
`1/0
`1/0
`
`1/0
`
`1/0
`
`0
`
`I
`
`0
`
`Description
`Data bus. It is lri-stated when DBus is not granted. When DB us is granted,
`data is driven onto Ibis bus in a write transaction to the Netwodc Buffer Memory.
`Data is driven by the Network Buffer Memory in a read transaction.
`
`Byte parity fcx' the DDATA[31:0]. It has the same timing as DDATA[31:0]. DDP[3]
`covers the DDATA[31:24], and so on.
`
`Tags. These lag bits are lri-stated when DBus is not granted. When DBus is granted,
`the same timing as
`they are outputs in a write transaction, driven with
`DDATA[31:0]. ~ lag bits are sensed by BC'IL to determine the data typeS and
`the status on DDATA[31:0].
`They are inputs in a read transaction. MPORT senses these lag bits to determine the
`data typeS and status on DDATA£31:0], indicated by BC'IL.
`
`DBus request. This signal is asserted to request DBus mastelSbip. It may remain
`asserted to request multiple transactions f<r a bus tenure.
`
`DBus granL This input indicates the granting of DBus rnasttnhip.
`
`DBus write sttobe. This signal, when negated, indicates the requested DBus
`transactions are reads. When asserted, it indicates the requested DBus transactions
`are writes.
`
`MAC Interface PiDs
`
`Symbol
`MCLK
`
`MD0[7:0]
`
`MPO
`
`MD1[7:0]
`
`MPI
`
`TBD
`
`1/0
`I
`
`Description
`MAC clock. This clock is used to synchronize with the extemal MAC device.
`It may be asynchronous to the system clock, Cl.K. Tbe on-chip dual-clock FIFO
`synchronizes MCLK and CLK.
`
`0
`
`0
`
`I
`
`I
`
`Data oulpUt to MAC device.
`
`Parity for the data output to MAC device.
`
`Data input from MAC device.
`
`Parity for the data input from MAC device.
`
`The cmtrol signals f<r the MAC device interface are to-be-determined.
`
`tOdallwU!IO
`
`13
`
`s
`
`WISTRON CORP. EXHIBIT 1024.015
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 16 of 46
`
`MPORT
`
`c
`
`System Control Pills
`
`1/0 Description
`System clock. This input signal provides synchronization for the on-chip circuitry.
`I
`
`I
`
`System reset. This input signal resets on-chip circuitry to a known stare. It should
`remain asserted for at least S 12 CLK cycles to assure proper reset of the chip.
`
`1/0 Description
`Test internal scan. Assertion of this signal selects the internal scan test.
`I
`
`I
`
`I
`
`I
`
`0
`
`I
`
`Test clock. This input signal is used to synchronize on-chip testing circuitry.
`
`Test mode selecL This signal is used to select among various test modes.
`
`Test data inpuL This pin is used for input test data.
`
`Test data OUipDL This pin is used for OUipnt test data.
`
`Test reset. This pin is used to reset test modes.
`
`Symbol
`
`CLK
`
`RESET
`
`Test Pills
`
`Symbol
`TiS
`
`TCK
`
`TMS
`
`IDI
`
`TOO
`
`TRST
`
`Power Pills
`
`'Odobor 1990
`
`14
`
`6
`
`-·
`
`( '·
`
`\
`
`(_
`
`WISTRON CORP. EXHIBIT 1024.016
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 17 of 46
`
`MPORT
`
`the packet in the frame, extracts certain information,
`4. Functional Description
`and delivers it to the Packet Processing Unit
`MPORT (MAC Port) transfers fiames between the
`A Checksummer validates the checksum on the packet
`extemal MAC device and Network Buffer Memory
`flowing through the Receive Pipeline Unit Packet
`the input tiame passes ~
`(NBM). When
`Process<x finnware detezmines the actions to be taken
`MPORT, processing is done in the datapatb. This
`in the event of checksum failure or otha' failure.
`processing includes cbecksumming, byte swapping,
`identification,
`protOCOl
`parsing,
`header/trail«
`demultiplexing. etc.
`The processing is done in various functiooal blocks
`that are illustrated in F'J.gUie 3.
`There are six map functional blocks in MPORT:
`MAC Intezface Unit (MIU), Receive Pipeline Unit,
`Transmit Pipeline Unit, DBus Interface Unit {DIU),
`Packet Processing Unit (PPU) and CBus Intaface
`.
`Unit(CRJ).
`
`4.3 Transmit Pipeline Unit
`
`Like the Receive Pipeline Unit, the Transmit Pipeline
`Unit is a single directional datapath. The data flow
`starts from DIU. The data flows into a Transmit DBus
`FIFO, through a Transmit Datapath and a Transmit
`MAC FIFO and ends at the MAC Interface Unit
`(MIU).
`The Transmit MAC FIFO is similar to the Receive
`MAC FIFO with opposite data flow directioo. The
`data flow into the FIFO is clocked by CLK and the
`data flow out of the FIFO is clocked by MCLK to
`provide synchronization between two clock systems.
`
`4.4 DBus Interface Unit (DIU)
`
`The DBus Interface Unit contains state machine· for
`DBus control. It performs burst read/write on the
`DBus to maximize DBus efficiency. Two operating
`modes are available: the non-interleaved mode and the
`interleaved mode.
`The non-interleaved mode works with non-interleaved
`to deliver 320 Mbps
`Netwmc Buffer Memory
`bandwidth on DBus. The interleaved mode works with
`interleaved Network. Buffer Memory to deliver 700
`Mbpsbandwidth on DBus.
`
`4.5 Packet Processing Unit (PPU)
`
`The Packet Processing Unit contains a Packet
`Processcr and Instmction Memory. The pogram for
`the Packet Processor is down-loaded into Instruction
`Memory at boot time. The Packet Processor processes
`the information received from the Receive Pipeline
`Unit As a result of the processing in Packet Processor,
`the receiving packets are demultiplexed to each
`context They are also properly disposed accmfing to
`the information retrieved from the header/trailer in the
`packet
`
`4.6 CBus Interface Unit (CIU)
`
`The CBus Interface Unit interfaces to CBus to aa:ess
`the Conttol Memory and othez devices in the PE
`Chipset. The Packet Processar may access the data
`
`4.1 MAC Interface Unit (MIU}
`
`The MAC Interface Unit contains the state machines
`to interface to the external MAC devices. It has an
`eight bit data input bus and an eight bit data oulpUt bus
`to connect to the MAC. Both buses have parity bits.
`The parity can be optionally tmned off. The conttol
`signals interfacing to the MAC device have not been
`finalized.
`
`4.2 Receive Pipeline Unit
`
`The Receive Pipeline Unit lw a single directional data
`flow. The data flow starts from MIU. It is fed into a
`Receive MAC FIFO. The data coming out of the
`Receive MAC FIFO flows into a Receive Da&apath,
`then goes to a Receive DBus FIFO. The data coming
`out of Receive DBus FIFO goes to a DBus lnraface
`Unit (DIU). DIU will store the data into Network
`Buffer Memory via DBus.
`The Receive MAC FIFO is opcnted by both MCLK
`and O.K. MCLK is used to feed data into the FIFO
`and CLK is used to retrieve data from FIFO. This
`scheme allows the MAC device, running oo MCLK,
`to be asyncluonous to the system clock, O.K.
`The data, embodied in frames, flows into the Receive
`Datapath to obtain a series of processing steps. The
`data are word aligned, padded with fill-pallml if
`necessary, byte swapped if necessary to become big(cid:173)
`endian. These pocessing steps are controlled by a
`is a programmable
`Proto Parser. Proto Parser
`processor. Its micro program is down-loaded at boot
`time. It can be programmed to adapt to various media
`and various protocols. Proto Parsec counts the bytes in
`frames and examines their header to determine further
`action. Proto Parser recognizes the profOCOl used by
`
`9 Oclala' 1990
`
`15
`
`7
`
`WISTRON CORP. EXHIBIT 1024.017
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 18 of 46
`
`MPORT
`
`base stored in Control Memory, or request slave
`access to the other devices attached oo CBus. These
`the Packet
`uansactioos provide information for
`Processor to decide the disposition of the packet being
`proc:essed, updates information in Coolrol Manay to
`facilitate processing for the following packets, and
`receives and provides commands to peer devices.
`
`(
`
`16
`
`8
`
`WISTRON CORP. EXHIBIT 1024.018
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 19 of 46
`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 19 of 46
`
`
`
`-.lHOdH
`
`
`
`WISTRON CORP. EXHIBIT 1024.019
`
`17
`17
`
`WISTRON CORP. EXHIBIT 1024.019
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 20 of 46
`
`• < Protocol Engines
`C
`P
`IN:orporated
`
`PREUMINARY
`(subject to change without notice)
`
`HPORT
`
`1. Features
`• one micron CMOS technology
`• 33MHz system clock
`• syncbrmization to external host bus clock. up
`to25MHz
`• asynchronous host bus clock and system clock
`transmiuer
`intemal
`receiver and
`• separate
`FIFOs
`• 32-bit host interface with parity
`• performs checksum generatioo, packetization,
`byte swapping. word alignment, and other
`'
`fiwnctions
`• hardware support for XTP, TCP, ISO, and
`XNS checksums
`• pugrammable support for multiple protocols
`• supports both big- and little-endian hosts.
`
`2. General Description
`Host Port (HPORT) of the Protocol Engine• chipset is
`a programmable cootroller that supports high-speed
`three extmUll
`protocol processing:
`It provides
`
`hardware interfaces: host bus (HBus), data bus
`(DBus), and control bus (CBus).
`11uoogh HBus, HPORT provides DMA and slave
`intelfaces to the host bus or to a dedicated bus
`coonecting to a data sinlc/soun::e device, such as image
`buffer and sens<X'. HBus is opezated by a separate
`clock. HCLK, to synchronize to the host bus.
`11uoogh · DBus. HPORT accesses Netwodt Buffer
`Memory to store output packets, to retrieve received
`packets, and to update tbe buffer management data
`structures.
`Through CBus, HPORT accesses Control Memory
`and sends/receives control messages to peer devices. It
`also povides a datapath for the host to make slave
`accesses to HPORT's peer devices..
`these buses, an on-chip pogrammable
`11uoogh
`processor, and the datapath functiooal unit. the
`HPORT perfonns checksum generation, packetization,
`intelligent DMA. and other fiwnctions. HPORT can
`support a variety of protoCOls and custom host
`interfaces.
`
`C.
`
`Te IIAC Fn.IIAC
`
`Flgan1. PE Chipset.
`
`18
`
`1
`
`WISTRON CORP. EXHIBIT 1024.020
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 21 of 46
`
`HPORT
`
`3. Pin Description
`
`cue
`IIQI 11:111 ,.
`
`TCK
`TIIS
`TDI
`TOO
`lAST
`
`Figure 2. HPORT Symbol Dl-aram.
`
`--l !
`
`Aa
`
`FFO
`
`Aa
`Dllllpallt
`
`I
`Rx,..,..,.T
`.....
`T
`
`-lT
`............ ._.,tiU) I
`I 1lr,..,..,.
`.....
`! H:l
`.,.......
`Til b]::!..:l
`
`Til
`
`FFO
`
`P6tdr«-
`
`~mil
`
`Nlructlan
`
`.......,
`.....
`
`,._
`
`T
`
`All
`D8US
`FFO
`
`l
`
`Til
`D8US
`FFO
`
`I
`
`I
`!
`........... ._.(DIUt I
`
`I
`
`!T
`
`- -
`
`Figure 3. HPORT Block Diagram.
`
`ICBua ........ ._. CCIUII
`
`I
`
`!T
`
`-- --
`
`19
`
`2
`
`WISTRON CORP. EXHIBIT 1024.021
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 22 of 46
`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 22 of 46
`
`I-IPORT
`HPORT
`
`PW
`
`I-n—I—I-I—a-I—I—I-I—fig
`
`H‘Hflhfluflfl—“u—uu.
`—I-l—~_—Ia~
`
`CBulIeloaouforOd (molmcmory)
`CBuuehclalforBCILGIfletcmuofla)
`CBuuelectouforCP(cmndploceuor)
`DBuI dun
`
`DBIu dun puity
`DB‘s lug
`DBIu request
`DBum
`
`agaqamaaaaea.
`wasmag
`
`DDATA
`
`E
`
`
`
`DBu m‘u
`
`5'O
`
`I O 0 0 1
`
`&0
`MO
`no
`
`0 I O 1
`
`&0
`no
`no
`1&0
`no
`
`I I 0 n
`
`o
`
`I O I I I I I I I I I I 0 I
`
`Tabl- 1. HPORT Pin Summary.
`
`vomqum
`
`20
`20
`
`
`3
`
`WISTRON CORP. EXHIBIT 1024.022
`
`WISTRON CORP. EXHIBIT 1024.022
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 23 of 46
`
`HPORT
`
`CBusPiDs
`
`Synbol
`CAD[31:0]
`
`Description
`110
`1&0 Address/data bus. It is bi-stated when CBus is not granted. When CBus is granted.
`address is driven onto thiS bus during address cycle. and data is driven onto this
`bus during dala cycle. The data is driven by HPORT in a write ttansfer, er it is
`driven by a slave device in a read ttansfer.
`
`CDP[3:0]
`
`1/0
`
`Byte parity fer the CAD[31:0] bus. It has the same timing as the CAD[31:0].
`CDP[3] covm the CAD[31:24], and so on.
`
`CADS
`
`1/0
`
`Address strobe. When CBus is granted. it is an output Its assertion indicates that
`address is being driven onto CAD[31:0] by HPORT.
`When CBus is not granted, it is an illput Its assertion along with the assertion of
`CSI indicates that CAD[31:0] carries address driven by the current CBus master
`to address a slave register on HPORT.
`
`CiiD
`
`1/0
`
`Read strobe. When CBus is granted, it is asserted to indicate a read IJ30Sfer.
`When CBus is not granted, it is an input Its assertion indicates that the current
`CBus master is making a read ttansfer.
`
`CWR
`
`CRQ
`
`CGf'
`
`CERR
`
`CSI
`
`CSCM
`
`1/0 Write strobe. When CBus is granted, it is asserted to indicate a write ttansfer.
`When CBus is not granted, it is an inpUL Its assertion indicates that the current
`CBus masta' is making a write transfer.
`
`0
`
`I
`
`1/0
`
`I
`
`0
`
`CBus request. This signal is asserted to request CBus mastership. It may remain
`asserted to JeQUest multiple transactions fer a bus tenure.
`
`CBus grant This input indicates the granting of CBus mastership.
`
`CBus enor. This pin is both input and oulpUL The open drain, active low output
`reports CBus error to the peer devices which have CERR pins connected
`together. The ~put circuiuy detects CBus emn repmt.ed by any device
`connectedonCBus.
`
`Olip select in. The assertion of this pin indicates that the current CBus master is
`making a transaction with HPORT, as a slave device.
`
`Conuol Memory select It is bi-stated when CBus is not granted. It is asserted
`when CBus is granted and HPORT is addressing Conuol Memory.
`
`CSBCTL
`
`0
`
`BCIL select It is bi-stated when CBus is not granted. It is asserted when CBus is
`granted and HPORT is addressing BCil..
`
`CSCP
`
`0
`
`CP select It is tri-stated when CBus is not granted. It is asserted when CBus is
`granted and HPORT is addressing CP.
`
`(
`'-----
`
`21
`
`4
`
`WISTRON CORP. EXHIBIT 1024.023
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 24 of 46
`
`HPORT
`
`1/0 Description
`1/0 Data bus. It is tri-stared when DBus is not granted. When DBus is granted, data is driven mto
`this bus in a write transaction to the Netwmc Buff« Memory. Data is driven by the Netwodc
`Buffer Memory in a read aansaction.
`
`1/0 Byte parity for the DDATA[31:0]. It hu the same timing as DDATA[31:0]. DDP(3] covers
`the DDATA[31:24), and so on.
`
`1/0 Tags. These lag bits are tri-stared when DBus is not granted. When DBus is granted, they are
`oulpUts in a write aansaction, driven with the same timing as DDATA[31:0). These tag bits
`are sensed by BCil. to determine the data typeS and the slalus on DDATA[31:0].
`They are inputs in a read transactim. HPORT senses these tag bits to determine the data
`typeS and status on DDATA[31:0], indicated by BCil..
`
`0
`
`I
`
`I
`
`DBus requesL This signal is asserted to request DBus mastership. It may remain asserted to
`request multiple ttansactions for a bus tenure.
`
`DB us granL This input indicates the granting of DB us mastership.
`
`DBus write sttobes. This signal, when negated, indicates the requested DBus ttansactions are
`reads. When asserted, it indicates the requested DB us ttansactions are writes.
`
`DBusPins
`
`Symbol
`DDATA[31:0]
`
`DDP [3:0]
`
`DTG[3:0)
`
`DRQ
`
`DOT
`
`DWR
`
`HBusPins
`
`Symbol
`HAD[31:0]
`
`1/0 Description
`1/0 HBus addresB/dara. Data and addresses are transferred over these lines. When HPORT is HBus master,
`these lines are inputs