United States Patent [191
`Lewis et al.
`
`[11] Patent Number:
`[45] Date of Patent:
`
`4,831,523
`May 16, 1989
`
`(75]
`
`[54] MULTIPLE DMA CONTROLLER CHIP
`SEQUENCER
`Inventors: Richard P. Lewis, Sandown, N.H.;
`John A. Klashka, North Andover,
`Mass.
`[73] Assignee: BULL HN Information Systems Inc.,
`Billerica, Mass.
`(21] Appl. No.: 239,074
`Aug. 31, 1988
`[22] Filed:
`
`Related U.S. Application Data
`(63] Continuation of Ser. No. 925,344, Oct. 31, 1986, aban(cid:173)
`doned.
`Int. 0.4 ....................... G06F 13/22; G06F 13/00
`[51]
`(52] u.s. a .................................. 364/200; 364/241.1;
`364/242.3; 364/242.33
`(58] Field of Search ... 364/200 MS File, 900 MS File
`References Cited
`(56]
`U.S. PATENT DOCUMENTS
`4,017,839 4/1977 Calle eta! ........................... 364/200
`4,067,059 1/1978 Derchak .............................. 364/200
`4,374,416 2/1983 Catiller et al. ...................... 364/200
`4,479,179 10/1984 Dinwiddie, Jr ..................... 364/200
`
`4,688,166 8/1987 Schneider ........................... 364/200
`Primary Examiner-Eddie P. Chan
`Attorney, Agent, or Firm-George Grayson; John S.
`Solakian; Lewis P. Elbinger
`ABSTRACT
`[57]
`A universal peripheral controller is disclosed which
`uses DMA devices to provide access between a plural(cid:173)
`ity of peripheral devices and other circuits within a
`computer system. A processor in the computer system
`recognizes a request from the controller to connect a
`peripheral via the system bus to another circuit con(cid:173)
`nected thereto and establishes the connection. The pro(cid:173)
`cessor then passes information to the controller and
`leaves the task of controlling the transfer of information
`to the DMA circuitry in the controller. The controller
`has a sequencer which examines each of the plurality of
`peripherals connected to it in a round robin operation to
`determine which peripherals are requesting a connec(cid:173)
`tion via the computer system bus to transfer informa(cid:173)
`tion. The sequencer limits the time each peripheral can
`be connected to the system bus before servicing another
`peripheral request in order that all peripherals have
`equal access to the system bus.
`
`9 Qaims, 9 Drawing Sheets
`
`207a -1r- 207b
`
`l2 BITS .11£, DATA BUS
`£11li£R ~ DR
`EllliER ~ QR l2 !ITS 1111£, AOIIIESS IllS
`
`WISTRON CORP. EXHIBIT 1012.001
`
`

`

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`PRIOR ART
`
`FIG I
`
`6
`
`PROCESSOR
`CENTRAL
`
`I
`
`J (114
`
`CONTROLLER
`NAG. TAPE
`NASS STORE/
`
`I Ill ... l
`
`I (112
`
`BUS
`
`CONTROLLER
`
`CONNUNICATIONS
`
`(110
`
`100--.
`
`CONTROLLER
`
`DEVICE
`BASIC
`
`I (108
`
`ARITHNETIC
`SCIENTIFIC
`
`UNIT
`
`216-1\
`
`N
`
`MENORY
`
`I
`MENORY
`
`I (104
`
`I (102
`
`PERIPHERAL
`
`DISK
`
`PERIPHERAL
`
`TAPE
`
`(120
`
`1>18 l
`
`~
`
`NOOENS
`
`TO
`
`PERIPHERAL
`
`RECORD
`UNIT
`
`216-21
`
`PERl PHERAL
`
`RECORD
`UNIT
`
`I
`
`WISTRON CORP. EXHIBIT 1012.002
`
`

`

`U.S. Patent
`
`May 16,1989
`
`Sheet 2 of9
`
`4,831,523
`
`201
`I'
`
`CONTROLLER
`
`( 202
`MEGA BUS
`MEMORY
`
`( 200
`
`;' 203
`
`SM F
`
`c ss
`
`M EGABUS1
`
`204../
`
`207a '-1 /207b
`CONNECT
`UPC CAN
`EITHER SECTION
`
`-
`~205
`/"207b
`
`207a/
`TO
`
`-"
`
`207o~207b
`
`16 OR 32 BITS WIDE , DATA BUS
`EITHER
`El THER 24 OR 32 BITS VII DE , ADDRESS BUS
`
`(209
`
`PERl PHERAL
`UNIVERSAL
`CONTROLLER
`
`;-210
`
`UPC -TEST
`CONNECTOR
`
`PORT
`0
`
`PORT
`I
`
`PORT
`2
`
`PORT
`3
`
`212)~ I
`
`/21 2
`
`2121
`
`2121
`
`ADAPTER
`
`ADAPTER
`
`ADAPTER
`
`ADAPTER
`
`(213
`
`r215o
`
`(214
`
`(215 b
`
`TAPE
`PERIPHERAL
`
`UNIT RECORD
`PERIPHERAL
`
`DISK
`PERIPHERAL
`
`UNIT RECORD
`PERl PHERAL
`
`FIG 2
`
`WISTRON CORP. EXHIBIT 1012.003
`
`

`

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`
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`
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`
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`
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`
`I
`I
`/316
`
`SHEET 2
`CONT ON
`
`I
`l
`£310
`
`I
`I XCVRS
`
`327)
`
`BUS
`
`GLOBAL
`
`312
`
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`
`(313
`
`I XCVRS
`
`/31
`
`I H
`
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`
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`
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`
`DECODERS
`CONTROL
`
`251
`
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`ADDRESS
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`A
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`
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`3261
`3251
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`
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`l D~A I
`
`305
`
`I D~A I
`
`304
`
`TINER
`
`I BUS
`
`WISTRON CORP. EXHIBIT 1012.004
`
`

`

`U.S. Patent
`
`May 16,1989
`
`Sheet 4 of9
`
`4,831,523
`
`[309
`PORT
`Ao
`
`,311
`PORT
`AI
`
`1'322
`PORT
`A2
`
`(323
`
`PORT
`A3
`
`ADAPTER
`
`{ 309 a
`CHAN A
`
`CHAN N OR MAX
`
`ADAPTER
`
`[311a
`CHAN N-tl
`
`CHAN M OR MA X.
`
`ADAPTER
`
`/322a
`CHAN M+l
`
`CHAN P OR MA X.
`
`ADAPTER
`
`[323a
`CHAN p +I
`
`CHAN 0 OR MAX
`
`FIG 3
`
`SHEET 2 of 2
`
`CONT. FROM
`SHEET I
`
`WISTRON CORP. EXHIBIT 1012.005
`
`

`

`U.S. Patent May 16,1989
`
`Sheet 5 of9
`
`4,831,523
`
`0 t.
`
`C> <
`::z: =
`
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`
`WISTRON CORP. EXHIBIT 1012.006
`
`

`

`U.S. Patent May 16,1989
`
`/
`
`s
`FLOP
`co
`c
`R
`
`PULUPS • 00
`PCLXGO + 10
`8.0 MHZ - II
`RSTBLK - 00
`
`PCLXGO- 00
`
`4,831,523
`
`Sheet 6 of9
`
`509
`BLKCTR +00
`
`BLKCTR - 00
`
`A
`
`511
`
`CYCLO - 00
`
`OMACLK + 00
`CYCCT4 - 00
`
`CYCCLK +00
`
`PULUPO + 00
`UOSOTC- 00
`CYCLKR - 00
`
`OMA, AS- 00
`
`ODMOTC - 00
`
`PULUPS +00
`MAXCNT + 10
`
`DMA,AS+IO
`REQDMA + 00
`
`S FLOP
`co
`c
`R
`
`/510
`PC LCLK + 00
`
`PCLCLK - 00
`
`512
`CYCCLK + 10
`
`/"513
`
`S FLOP
`co
`c
`R
`
`CYCCLK -00
`
`514
`
`[515
`2WDSET+OO
`
`2WDSET -00
`
`S FLOP
`CD
`c
`R
`
`FIG 5
`SHEET
`I of 4
`
`rr=
`I
`
`E
`
`WISTRON CORP. EXHIBIT 1012.007
`
`

`

`U.S. Patent May 16,1989
`
`Sheet 7 of9
`
`4,831,523
`
`A
`
`E
`
`F
`c
`
`II
`j 1
`
`K
`
`L
`
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`
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`PULUPI +00 c
`l CNTR I
`
`8.0 MHZ •10
`CTRLOD • 20
`REQDNA •00
`68KBR
`•00
`
`ZGND
`ZGND
`ZGND
`ZGND
`
`/ 50 I
`
`c
`Gl
`
`COUNT! .. 00
`COUNT2 + 00
`COUNT 4 +00
`COUNT 8 + 00
`
`DPPCLO -10
`
`RQAOEN -00
`
`I
`
`DPPCLI -10
`
`RQAIEN- 00
`
`RQBOEN -00
`
`DPPCL2 - 10
`
`DPPCL3 -10
`
`RQBI EN -00
`
`CYCCLK • 10
`PULUPE + 00
`
`-00
`CYCLD
`RESET - 10
`
`ZGND
`BSSZI6+10
`PULUPI •00
`ZGND
`
`CARRY
`
`::>---
`
`n50711
`
`:__.
`
`PCLOGO+OO
`
`5078
`PCLIGO •00
`
`507C
`PCL 2GO •00
`
`5070
`PCUGO +00
`
`vso3
`
`CYCCTI +00
`CYCCT2 +00
`CYCCT4 +00
`CYCCT8 +00
`
`r
`
`!--
`
`FIG 5
`SHEET 2of4
`
`c
`
`~
`Gl
`
`IR
`
`WISTRON CORP. EXHIBIT 1012.008
`
`

`

`U.S. Patent
`
`May 16,1989
`
`Sheet 8 of9
`
`4,831,523
`
`R
`
`s
`
`r
`
`IJ
`
`II
`
`DEC
`EN
`I
`2
`
`/ 521
`
`00
`01
`02
`03
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`
`I
`
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`PCLXGO -00
`
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`REQAO
`
`+00
`
`REQAO
`
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`
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`REQAI
`
`+00
`
`REQAI
`
`-00
`
`502C
`REQBO +00
`
`REQBO
`
`-00
`
`CD FLOP
`c
`R
`
`CO FLOP
`c
`R
`
`CD FLOP
`c
`R
`
`CD FLOP
`c
`R
`
`520 0
`
`5020
`REQBI
`
`REQBI
`
`+00
`
`-00
`
`DMACLK+OO
`
`519
`
`MAXCNT + 10
`
`516
`CYCCST
`
`... oo
`
`FIG 5
`SHEET 3 of 4
`
`COUNT I - 00
`COUNT 2 + 00
`COUNT 4 + 00
`
`PCL2GO +00
`PCLOGO + 00
`PCL I GO+ 00
`PCL3GO + 00
`
`PC LOGO -00
`BLKCTR + 00
`DMREQR -30
`
`PCL IGO -00
`
`PCL2GO -00
`
`PCL3GO -00
`
`8.0 MHZ +10
`
`REQDMA +00
`
`MAXCNT +00
`
`JUSONE +00
`
`2WDSET •00
`
`DONEAB •10
`
`- -
`
`f
`G
`
`-
`
`K
`
`IV
`
`0
`
`p -------,
`() - - - - - - ,
`
`WISTRON CORP. EXHIBIT 1012.009
`
`

`

`U.S. Patent
`
`May 16,1989
`
`Sheet 9 of9
`
`4,831,523
`
`REQ B I
`
`CYCCST
`
`-00
`
`+ 00
`
`REQBO
`
`CYCCST
`
`-00
`
`+00
`
`CYCCST
`
`REQAI
`
`+00
`
`-00
`
`CYCCST
`
`REQAO
`
`+00
`
`-00
`
`CYCCT2
`
`-+-00
`
`WORD NO
`
`+00
`
`5040
`REQBI
`
`-10
`
`504C
`REQBO
`
`-10
`
`-10
`
`-10
`
`5048
`REQAI
`
`\
`
`504A
`REQAO
`
`518
`
`CT2WRO +00
`
`CYCCTI +00
`
`517
`MAXCNT +00
`
`\
`
`FIG 5
`SHEET 4 of4
`
`-
`
`s
`-
`
`-
`T
`
`u
`-
`y
`
`WISTRON CORP. EXHIBIT 1012.010
`
`

`

`1
`
`MULTIPLE DMA CONTROLLER CHIP
`SEQUENCER
`
`4,831,523
`
`2
`having the highest priority and with the central proces(cid:173)
`sor 106 having the lowest priority. Also connected on
`the bus may be included, for example, a scientific-arith-
`metic unit 108 and various controllers 110, 112. 114
`Controller 110 may be coupled to control, for example.
`4 unit record peripheral devices 216. Controller 112
`may be used to provide communication control via
`modem devices; whereas controller 114 may be utilized
`to control mass storage devices, such as a tape periph-
`10 eral device 118 and a disk peripheral device 120. Any
`one of the devices coupled with the bus 100 may ad(cid:173)
`dress a memory or any other unit connected to the bus.
`Thus tape peripheral 118 may, via controller 114. ad(cid:173)
`dress memory 102. Each of such units directly con-
`IS nected to bus 100 includes a tie-breaking logic in the
`event that two units request simultaneous service to the
`bus further.
`A channel number exists for every end point in the
`particular system with the exception of the memory
`type processing elements which are identified by the
`memory address. A channel number is assigned for each
`such device. Full duplex devices, as well as half duplex
`devices, utilize two channel numbers. Output only or
`input only devices use only one channel number each.
`25 Channel numbers are easily variable and accordingly
`one or more hexidecimal rotary switches (thumb wheel
`switches) may be utilized for each such unit or devices
`connected to the bus to indicate a devices address. Thus
`when a system is configured, the channel number may
`30 be designated for each particular unit or device con(cid:173)
`nected to the bus, as may be appropriate for that partic(cid:173)
`ular system. Units with multiple inputs/outputs gener(cid:173)
`ally will require a block of consecutive channel num-
`bers By way of example, a 4 port unit may use rotary
`switches to assign the upper 7 bits of a channel number
`and may use the lower order 3 bits thereof to define the
`port number to distinguish input ports from output
`ports. The channel number of the slave unit will appear
`on the address bus for all non-memory transfers. Each
`unit compares that number with its own internally
`stored number (internally stored by means of the rotary
`switches). The unit which achieves a comparison match
`is, by definition, the slave, and must respond to that
`cycle. Generally, no two points in a single system will
`be assigned to the same channel number. The function
`codes may designate output or input operations. All odd
`function codes designate output transfers (write), while
`all even function codes designate input transfer requests
`(read). The central processor examines the least signifi(cid:173)
`cant bit of a 6 bit function code field for an input/ output
`command and uses a bus lead to designate the direction.
`A unique device identification number is assigned to
`every different type of device or unit which is con(cid:173)
`nected to the bus. This number is presented on the bus
`in response to the input function command, entitled
`input device identification.
`A unit wishing to interrupt the central processor
`requests the bus cycle. When this bus cycle is granted,
`the unit places its interrupt vector on the bus, the inter(cid:173)
`rupt vector includes the channel number of the central
`processor and the interrupt level number. The unit thus
`provides, as its interrupt vector, the master's channel
`number and its interrupt level number. If this is the
`central processor's channel number, the central proces(cid:173)
`sor will accept the interrupt if the level presented is
`numerically smaller than the current internal central
`processor level and if the central processor has not just
`accepted another interrupt.
`
`This is a continuation of copending application Ser. 5
`No. 06/925,344 filed on Oct. 31, 1986, now abandoned.
`
`RELATED CASES
`The following patent applications, which are as(cid:173)
`signed to the same assignee as the instant application,
`are related to the instant application:
`1. System Management Apparatus for a Multiproces(cid:173)
`sor System, invented by George J. Barlow, Elmer W.
`Carroll, James W. Keeley, Wallace A. Martland, Victor
`M. Morganti, Arthur Peters an Richard C. Zelley, Ser.
`No. 869,164, Filed May 30, 1986.
`2. Universal Peripheral Controller Self-Configuring
`Bootloadable Ramware, invented by John A. K1ashka,
`Sidney L. Kaufman, Krzysztof A. Kowal, Richard P.
`Lewis, John L. McNamara, Jr., and Susan L. Raise- 20
`beck, Ser. No. 925,431, Filed May 31, 1986, now U.S.
`Pat. No. 4,803,623.
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`This invention relates generally to data processing
`systems having data processing operations provided
`over a common input/output bus, and more particularly
`with a universal peripheral controller for controlling
`various types of peripherals coupled to the bus.
`2. Description of the Prior Art
`Many data processing systems include a common bus
`to which a plurality of units are connected for the trans(cid:173)
`fer of information. The bus permits any two units to
`communicate with each other at a given time via a 35
`common (shared) signal path. Any unit wishing to com(cid:173)
`municate, requests the bus cycle. When that bus cycle is
`granted, that unit becomes the master and may address
`any other unit in the system as the slave. Most transfers
`are in the direction of a master to a slave. Some types of 40
`bus interchange require a response cycle (read memory,
`for example). In cases where a response cycle is re(cid:173)
`quired, the requester assumes the role of the master,
`indicates a response is required, and identifies itself to
`the slave. When the required information becomes 45
`available (depending on slave response time), the slave
`now assumes the role of the master and initiates a trans-
`fer to the requesting unit. This completes the inter(cid:173)
`change which has taken two bus cycles. Intervening
`time on the bus between these two cycles may be used SO
`for other system traffic not involving these two units.
`A master may address any other unit on the bus as a
`slave. It does this by placing the slave address on the
`address leads. There may be 24 address leads, for exam(cid:173)
`ple, which can have either of two interpretations de- SS
`pending on the state of an accompanying control lead,
`called the memory reference cycle. In essence when the
`memory is being addressed, the bus enables up to 224
`bytes to be directly addressed to memory. When units
`are passing control information, data or interrupts, they 60
`address each other by a channel number. The channel
`number allows up to 210 channels to be addressed by the
`bus. Along with the channel number a 6 bit function
`code is passed which specifies which up to 26 possible
`functions this transfer implies.
`A typical prior art data processing system utilizing a
`bus is shown on FIG. 1. A multiline bus 100 coupled
`with memory 1 102 to memory N 104, such memories
`
`65
`
`WISTRON CORP. EXHIBIT 1012.011
`
`

`

`4,831,523
`
`4
`OBJECTS OF THE INVENTION
`It is a primary object of the invention to provide an
`improved peripheral controller system.
`Another major object of the invention is to provide
`an improved data processing system having an im(cid:173)
`proved bus architecture.
`Still another object of the invention is to provide a
`universal peripheral controller that can be compatible
`with different computer architectures.
`Yet another object of the invention is to provide a
`universal peripheral controller that can accommodate
`the coupling of different types of peripheral devices to
`the Megabus.
`Still a further object of the invention is to provide a
`universal peripheral controller that will award the bus
`to peripheral devices on a rotating priority basis.
`Yet a further object of the invention is to provide a
`20 universal peripheral controller that will permit several
`levels of simultaneity in the transfer of data on the bus.
`
`3
`In this type of system different units have different
`priorities in order to obtain bus cycles. For example, the
`memory has the highest priority and the central proces(cid:173)
`sor has the lowest priority, and they reside physically at
`opposite ends of the bus 100. Other units occupy inter- 5
`mediate positions and have priority which increases
`relative to their proximity to the memory end of the bus.
`More detail is disclosed in regard to the above type of
`bus system in the following U.S. patents. The subject
`patents pertain to the proprietary bus system of Honey- 10
`well known in the trade as Megabus*.
`*Megabus-a trademark of Honeywell fnformation Systems Inc.
`(a) Data Processing System Providing Split-Bus
`Cycle Operation by Frank V. Cassarino, Jr. et al,
`issued Dec. 14, 1976, and having U.S. Pat. No. 15
`3,997,896.
`(b) Data Processing System Providing Locked Oper(cid:173)
`ation of Shared Resources by George J. Barlow et
`al, issued Dec. 28, 1976 and having U.S. Pat. No.
`4,000,485.
`(c) Data Processing System Having Distributed Pri(cid:173)
`ority Network by George J. Barlow, issued June
`14, 1977, and having U.S. Pat. No. 4,030,075.
`(d) Data Processing System Having Distributed Pri(cid:173)
`ority Network with Logic for Deactivating Infor- 25
`mation Transfer Requests by George J. Barlow,
`issued June 20, 1978, and having U.S. Pat. No.
`4,096,569.
`(e) Apparatus for Processing Data Transfer Requests
`in a Data Processing System by Frank V. Cas- 30
`sarino, Jr. et al, issued Nov. 23, 1976, and having
`U.S. Pat. No. 3,993,981.
`(f) Data Processing System Having a Data Integrity
`Technique by George J. Barlow, issued Nov. 30,
`1976, and having U.S. Pat. No. 3,995,258.
`It can be seen that with this hierarchical bus process
`system and the diversity of peripheral systems attached
`to the bus by different types of controllers that it was
`necessary to have a universal peripheral controller
`which could control different types of devices, and 40
`eliminate the necessity of having different controllers
`for different peripherals.
`Accordingly a new architecture was necessary, so
`that the controller would provide equal access to all 45
`peripherals coupled to the bus and not lock out or deny
`access to any peripheral because of priority problems.
`In order that the controller be cheaper yet more effi(cid:173)
`cient it was required that data transfers on the bus be
`performed autonomously under local control by com- 50
`mercially available direct memory access (DMA) chips
`once tee Megabus microprocessor (J.LP) had set up the
`transfer requirements. In this way the J.LP would be left
`free to attend to other tasks while the DMA chips could
`oversee the transfer of information between devices 55
`coupled to the J.LP. Thus several levels of simultaneity
`could be achieved for data processors.
`One problem that presented itself in achieving this
`result was the fact that the architecture, in order to
`provide equal access to the bus by various peripherals 60
`required a rotating priority scheme, wherein each port,
`to which a peripheral device was attached, was to re(cid:173)
`ceive up to 4 bytes of information at one given time then
`proceed to the other ports in round robin fashion. How(cid:173)
`ever the commercially available DMA chip has a prior- 65
`ity scheme which awards the bus channel to the highest
`priority channel when both channels presented requests
`for the bus simultaneously.
`
`35
`
`SUMMARY OF THE INVENTION
`These and other objects of the invention are achieve
`by providing a method and apparatus that utilizes a
`round robin technique in the transfer of information
`between peripheral devices and other devices coupled
`to the Megabus. The invention allows equal access for
`each port coupled to a global bus 316, which in turn is
`coupled to the Megabus 204, 205. The global bus 316 is
`also coupled to a plurality of ports 309, 311, 322, 323
`which have adapters 309a, 311a, 322a and 323a respec(cid:173)
`tively coupled to the ports which are utilized to couple
`a variety of different types of peripheral devices to the
`computer system via the UPC 209. Also coupled to the
`global bus is a plurality of DMA chips 305, 306 for
`controlling the transfer of information between periph(cid:173)
`eral devices and other devices on the system.
`When a request is made to the ~-tP 301 coupled to the
`Megabus for access to the Megabus, the ~-tP sets up the
`necessary paths for a dialog with the medium requesting
`access an provides the DMA chip controlling the trans(cid:173)
`fer with address and range information. It then proceeds
`to other tasks while the DMA chip controls the transfer
`of information in round robin fashion utilizing a DMA
`chip sequencer 350. The sequencer advances until it
`finds a channel that has a request. The global bus is then
`granted to that channel but only to transfer up to 4
`bytes. The sequencer methodically advances to tee next
`port requesting DMA activity and repeats the scenario
`of a 4 byte transfer.
`
`BRIEF DESCRIPTION OF THE ORA WINGS
`The manner in which the apparatus of the present
`invention is constructed and its mode of operation can
`best be understood in the light of the following detailed
`description, together with the accompanying drawings
`in which:
`FIG. 1 is a schematic drawing of a prior art computer
`system utilizing a bus architecture.
`FIG. 2 is a high-level block diagram of the invention.
`FIG. 3 (2 sheets) is a more detailed block diagram of
`the invention.
`FIG. 4 is a high level block diagram of the D MA chip
`sequencer of the invention.
`FIG. 5 (4 sheets) is a detailed logic circuit diagram of
`the invention.
`
`WISTRON CORP. EXHIBIT 1012.012
`
`

`

`5
`DESCRIPTION OF A PREFERRED
`EMBODIMENT OF THE INVENTION
`Referring now to FIG. 2 there is shown a block dia(cid:173)
`gram of the Universal Peripheral Controller Subsystem 5
`(UPCS). The UPCS provides a common controller, the
`universal peripheral controller (UPC) 209 for all Mega(cid:173)
`bus 204, 205 input/output (I/0) configurations with a
`facility to interface with a variety of peripheral devices.
`The UPC permits four simultaneous data transfers as 10
`well as peripheral control functions on Not Busy Chan(cid:173)
`nels. The UPC supports a high priority, low data rate
`section of the Megabus 204 or a low priority, high data
`rate section of the Megabus 205. The UPC can further
`support either a 16 or 32 bit data bus and either a 24 or 15
`32 address bus.
`Coupled to the Megabus 204, 205 are a variety of
`devices as shown in the above subject patents. Shown
`on FIG. 2 coupled to the Megabus 204, 205 are typically
`a controller 201 which includes the system management 20
`facility (SMF) 200, a Megabus memory 202 and a cen(cid:173)
`tral subsystem CSS 203.
`The universal peripheral controller 209 can couple to
`either the high priority, low data rate section of Mega(cid:173)
`bus 204 via a data bus 207a, which may be either 16 or 25
`32 bits wide and an address bus 207b, which may be
`either 24 or 32 bits wide to provide an interface assem(cid:173)
`bly enabling any Megabus I/0 configuration to commu(cid:173)
`nicate with UPC/adapter connected peripherals. The
`UPCS further includes up to 4 peripheral adapters 212, 30
`each adapter having one or more channels, allowing a
`total of up to eight logical channels per UPC. Coupled
`to the adapters via one controller 209 are typical periph(cid:173)
`erals, such as tape peripheral 213, disk peripheral 214
`and unit record peripherals 215a and 215b. Although 35
`not shown in the Figures supra, all adapters provide
`some data buffering for data rate synchronization and
`for error detection. Also coupled to the UPC is a RAM
`expansion 210 which may also be an integral part of the
`UPC.
`Referring now to FIG. 3 there is shown a more de(cid:173)
`tailed block diagram of the Universal Peripheral Con(cid:173)
`troller. A commercially available Motorola 68000 type
`microprocessor (~-tP) 301 is coupled to internal data and
`address buses 325, 326 respectively. A commercially 45
`available programmable read only memory (PROM)
`302 is also coupled to the data and address buses 325,
`326 and is also coupled to commercially available con(cid:173)
`trol decoders 314. A commercially available dynamic
`random access memory (DRAM) 303 is further coupled 50
`to the data and address bus lines 325, 326 and is further
`coupled to the MY COMMAND register 315. The
`DRAM 303 may have storage capacity for at least 64K
`words and is provided with random logic implementa(cid:173)
`tion to refresh information stored therein. A commer- 55
`cially available bus timer 304 is coupled to the data
`address bus 325 and provides three functions. The first
`function is to detect if there is no response to a request
`for the bus and notify the ~J.P. The second function of
`the bus timer 304 is to determine if the instruction being 60
`executed takes longer than a predetermined value and
`whether or not it has to abort the execution of the in(cid:173)
`struction. Finally, the third function of the bus timer 304
`is to determine if there is a DMA request cycle which
`takes longer than a predetermined period and abort that 65
`DMA cycle. A global bus 316 is coupled to data and
`address lines 325, 326, respectively, via a commercially
`available transceiver 313. The global bus 316 is further
`
`40
`
`4,831,523
`
`6
`coupled to the interface 324 of the Megabus. Addition(cid:173)
`ally the global bus 316 is coupled to ports 309, 311, 322
`and 323, respectively, via commercially available trans(cid:173)
`ceivers 310 through path 327. Each port 309, 311, 322
`and 323 has a respective adapter coupled to it, 309a.
`31la, 322a, and 323a. In addition the global bus 316 has
`MY address register 319 and MY data register 321 cou(cid:173)
`pled to it. These registers 319, 321 each have 4 bytes
`each. MY data register 321 has bytes A, B. C, D, each
`8 bits wide including a parity bit. While MY address
`register 319 also has 4 bytes E, F, G, H, each 8 bits wide
`including a parity bit. These bytes and data and address
`registers 321, 319, respectively, correspond to data and
`address registers A, B, C, D, and E, F, G, H, located in
`the Megabus interface 324. Also in the Megabus inter(cid:173)
`face 324 are command registers each having 8 bits in(cid:173)
`cluding a parity bit, and are each individually and se(cid:173)
`quentially marked 0---7 P, 8---15 P, etc. Also included in
`the Megabus interface 324 are commercially available
`transceivers 26S 10.
`Also coupled to the global address and data bus 316
`are two typical commercially available DMA chips 305,
`306 via transceiver 312.
`The gist of the peripheral controller is to have the f.LP
`301 set up the paths for a dialog from a peripheral de(cid:173)
`vice requesting service through transceivers 313, global
`bus 316, Megabus interface 324, transceivers 310, ports
`309, 311, 322, 323 and finally through adapters 309a,
`311a, 322a, 323a, and on to the specific peripheral de(cid:173)
`vices and to further provide address and range informa(cid:173)
`tion to the DMA chips 305, 306 via transceiver 313,
`global bus 316 and transceiver 312. Once the ~-tP 301 has
`set up the particular dialog between a given peripheral
`and another device, it turns over the task of actually
`performing the transfer of information to one of the
`DMA devices 305, 306, which then controls a round
`robbin access to global bus 366 from the various ports
`309, 311, 322, 323.
`A typical request for service via the Megabus and its
`subsequent response by the DMA chip controller se(cid:173)
`quencer system may be accomplished in the following
`manner. Referring to FIG. 3, when a request is received
`by the multiple DMA controller system which identi(cid:173)
`fies a channel number of the system, the information is
`stored in a task decoder 251. The data and the address
`pertaining to this request will be stored in MY DATA
`REGISTER 321 and MY ADDRESS REGISTER 319
`as they arrive. The task decoder 251 determines the
`particular ports/channels that this new request is to
`then determines
`service. The microprocessor 301
`whether or not that particular channel identified by the
`request is available (i.e., whether it is busy or present)
`and it will signal RAMW ARE* means (not shown) that
`a request has been received for a particular adapter.
`(The Ramware means is the subject of another inven(cid:173)
`tion assigned to the same assignee as the instant inven(cid:173)
`tion and filed on the same date as the instant application
`and having the title Universal Peripheral Controller
`Self-Configurating/Bootloadable Ramware, invented
`by John Klashka et al. It is not necessary to the practice
`of the instant claimed invention.) The microprocessor
`301 will then set up the particular DMA chip 305, 306,
`that is to handle the request and set up the parameters
`that the chip will require, such as the starting address,
`the range address, and other parameters which are not
`necessary to the practice of this invention. The particu(cid:173)
`lar adapter, for example, 309a involved in the transfer is
`cleared and made ready for transfer of information
`
`WISTRON CORP. EXHIBIT 1012.013
`
`

`

`4,831,523
`
`7
`which is to be read into or out of the adapter buffer
`memory 380-383 The DMA chip 305, 306, then notifies
`the Megabus memory 202 (FIG. 2) that it is ready to
`transfer information into/out of a particular location in
`memory 202. The information requested from a particu-
`lar location in memory 202 will be applied to Megabus
`interface 324 and made available to the UPC 209. As
`discussed supra, the information available on the Mega(cid:173)
`bus interface 324 will be up to 4 bytes, 32 bits wide.
`These 32 bits are broken up into 2 word transfers--data 10
`words, A, B, C, D, and address words E, F, G, H. Each
`byte is 9 bits wide comprising a byte 0--7, and a parity
`bit P. The adapter 309a, 311a, 322a, and 323a may be a
`byte wide (i.e., 9 bits) or they may be able to access
`words 18 bits wide. Accordingly for byte transfers, four 15
`separate transfer operations are required; whereas with
`word transfers only two separate operations are re(cid:173)
`quired via the DMA chip 305, 306, the MY registers
`321, 319, the global data and address bus 316 and trans(cid:173)
`ceivers 310. In the case of a byte transfer a typical trans- 20
`fer may be as follows. The cognizant adapter involved
`in the transfer makes a request which is placed on inter(cid:173)
`nal bus 327 via transceivers 310. This request is received
`by sequence controller 350. (To be described in greater
`detail infra.) The purpose of the sequencer 350 is to 25
`provide equal access to the global bus to all adapters in
`round-robin fashion rather than granting the global bus
`to the highest priority unit which could exclude lower
`priority units from access to the global bus 316 for con(cid:173)
`siderable periods of time The sequencer 350 examines 30
`the first adapter 309A to determine whether or not
`there is any information to be transferred to/from it. If
`there is information to be transferred to/from adapter
`309a, global bus 316 is granted to it and up to 4 bytes are
`transferred to/from the adapter 309a via its buffer mem- 35
`ory 380. The sequence control will then advance to the
`next adapter 311a which is examined to determine
`whether or not it has a request for service. If it does, it
`will be serviced in a similar manner as adapter 309a; if
`on the other hand it does not have a request for service, 40
`the sequencer proceeds round-robin to the other adapt-
`ers until all the adapters have been examined for service
`request and serviced, if necessary, wherein the sequence
`begins all over again.
`•Ramware-a trademark of Honeywell Information Systems Inc.
`Referring now to FIG. 4 and 5, a detailed description 45
`of the DMA controller chip sequencer will be given.
`FIG. 4 is a high level block diagram of the more de(cid:173)
`tailed logic block diagram of FIG. 5. Sequence counter
`401 on FIG. 4, corresponds to sequence counter 501 on
`FIG. 5. It is a commercially available 74L8169 type of 50
`free-running counter that cycles sequentially through
`the different ports 309, 311, 322, 323. When a port, such
`as for example 309 on FIG. 3, makes a request for ser(cid:173)
`vice, it asserts the PCL line coupled to the interface 424.
`(The interface 424 on FIG. 4 corresponds to interface 55
`324 on FIG. 3.) When the sequencer 401, 501 cycles to
`port 309 which has made a service request, the flip-flop
`402, corresponding to flip-flops 502A and 502D on
`FIG. 5, is set. This sets latching logic so that a data
`request may beg