`US 6,366,128 B1
`(10) Patent N0.:
`Ghia et al.
`
`(45) Date of Patent: Apr. 2, 2002
`
`USOO6366128B1
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`(54)
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`(75)
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`CIRCUIT FOR PRODUCING LOW-VOLTAGE
`DIFFERENTIAL SIGNALS
`
`Inventors: Atul V. Ghia, San Jose; Suresh M.
`Menon, Sunnyvale; David P. Schultz,
`San Jose, all of CA (US)
`
`(73)
`
`Assignee: Xilinx, Inc., San Jose, CA (US)
`
`(*)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21)
`
`(22)
`
`(51)
`(52)
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`(58)
`
`(56)
`
`Appl. No.: 09/655,168
`
`Filed:
`
`Sep. 5, 2000
`
`Int. Cl.7 ..................... H03K 19/094; H03K 19/173
`
`US. Cl.
`........ 326/83; 326/44; 326/40;
`326/49
`Field of Search .............................. 326/83, 86, 87,
`326/38, 40, 44, 45, 46, 49, 30
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`.................. 327/433
`5,355,035 A * 10/1994 Vora et al.
`5,812,461 A *
`9/1998 Komarek et al.
`...... 365/189.05
`5,958,026 A
`9/1999 Goetting et a1.
`FOREIGN PATENT DOCUMENTS
`
`JP
`
`60260254
`
`*
`
`6/1987
`
`.................. 326/30
`
`OTHER PUBLICATIONS
`
`Electrical Characteristics of Low Voltage Differential Sig-
`naling (LVDS) Interface Circuits, TIA/EIA—644, Mar. 1996.
`Jon Brunetti and Brian Von Herzen, “Multi—Drop LVDS
`with Virtex—E FPGAs,” XAPP231 (Version 1.0) Sep. 23,
`1999.
`
`Application Report “LVDS Multidrop Connections” pub-
`lished by Texas Instruments, Jul. 1999.
`
`* cited by examiner
`
`Primary Examiner—Michael Tokar
`Assistant Examiner—Daniel D. Chang
`(74) Attorney, Agent, or Firm—Arthur J. Behiel; Edel M.
`Young
`
`(57)
`
`ABSTRACT
`
`Described are systems for producing differential logic sig-
`nals. These systems can be adapted for use with different
`loads by programming one or more programmable elements.
`One embodiment
`includes a series of driver stages,
`the
`outputs of which are connected to one another. The driver
`stages turn on successively to provide increasingly powerful
`differential amplification. This progressive increase in
`amplification produces a corresponding progressive
`decrease in output resistance, which reduces the noise asso-
`ciated with signal reflection. The systems can be incorpo-
`rated into programmable IOBs to enable PLDs to provide
`differential output signals.
`
`23 Claims, 10 Drawing Sheets
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`
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`Apr. 2, 2002
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`Sheet 1 0f 10
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`US 6,366,128 B1
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`
`
`FIG. 1
`
`
`
`FIG. 2
`
`(PRIOR ART)
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`Sheet 2 0f 10
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`US 6,366,128 B1
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`TX_A .......... +250 TO 400 mV
`
`D/
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`TX_B
`
`TX_A - TX_B
`
`‘5 300
`
`ov (DIFF)
`
`-250 TO -400 mV
`
`FIG. 3
`
`(PRIOR ART)
`
`400 \‘
`
`
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`Sheet 3 0f 10
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`US 6,366,128 B1
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`405 \‘
`
`X_DS/
`
`528
`
`’
`
`VCCO
`
`EN_DS “I .
`up..."
`
`D_|N
`
`——-——-——|
`I
`I
`
`o
`12
`514
`
`DX
`
`D
`
`:|
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`
`’3
`€1.81
`
`
`
`——————l
`P:20
`I
`o
`| D/
`N210
`I
`522
`{
`|
`>0 >24
`:
`N22
`529]
`
`P24
`
`'
`
`530
`
`p-
`
`cm
`
`FIG. 5A
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`Sheet 4 0f 10
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`US 6,366,128 B1
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`[415
`
`TXA
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`TX__B
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`Sheet 5 0f 10
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`US 6,366,128 B1
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`PBIAS
`
`|
`
`l
`
`fl
`
`I'— ————————— —I
`
`vcco
`556 -
`558
`
`‘/"4‘°
`
`TX_A
`
`__________:—_.
`
`*——— ——1
`lx_Ds
`M:
`
`II
`
`N
`
`TX_B
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`Sheet 6 0f 10
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`US 6,366,128 B1
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`/600
`
`
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`FIG. 6
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`Sheet 7 0f 10
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`US 6,366,128 B1
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`
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`VCCO
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`D/
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`D1/
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`D2/
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`530
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`DX/
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`FIG. 7A
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`Sheet 8 0f 10
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`US 6,366,128 B1
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`VCCO
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`AXT
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`TXB
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`FIG. 7B
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`Sheet 9 0f 10
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`US 6,366,128 B1
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`800 —\
`
`[810
`”—“— —‘1
`I SRAM
`
`BIAS
`
`ICBIT
`
`320 I
`
`
`
`H_SUP
`
`I
`
`BIAS
`
`BIAS/
`
`-l
`
`808
`
`V
`
`CB|T_B
`
`B ’0 B/
`
`CBIT_C
`
`849
`
`C ’0 C/
`
`FIG. 8A
`
`302
`
`x‘
`
`m
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`Sheet 10 0f 10
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`US 6,366,128 B1
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`mAs
`
`mAS/
`
`852
`
`NGATE
`
`NmAs
`
`VCCO
`
`-'l
`
`815
`
`H_SUPPLY
`
`NEAS
`
`PmAs
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`854
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`1
`CIRCUIT FOR PRODUCING LOW-VOLTAGE
`DIFFERENTIAL SIGNALS
`
`FIELD OF THE INVENTION
`
`This invention relates generally to methods and circuits
`for providing high-speed, low-voltage differential signals.
`
`BACKGROUND
`
`The Telecommunications Industry Association (TIA)
`published a standard specifying the electrical characteristics
`of low-voltage differential signaling (LVDS) interface cir-
`cuits that can be used to interchange binary signals. LVDS
`employs low-voltage differential signals to provide high-
`speed, low-power data communication. The use of differ-
`ential signals allows for cancellation of common-mode
`noise, and thus enables data transmission with exceptional
`speed and noise immunity. For a detailed description of this
`LVDS Standard, see “Electrical Characteristics of Low
`Voltage Differential Signaling (LVDS) Interface Circuits,”
`TIA/EIA-644 (March 1996), which is incorporated herein
`by reference.
`FIG. 1 (prior art) illustrates an LVDS generator 100
`connected to an LVDS receiver 110 via a transmission line
`
`115. Generator 100 converts a single-ended digital input
`signal DiIN on a like-named input terminal into a pair of
`complementary LVDS output signals on differential output
`terminals TXiA and TXiB. A 100-ohm termination load
`RL separates terminals TXiA and TXiB, and sets the
`output impedance of generator 100 to the level specified in
`the above-referenced LVDS Standard.
`
`LVDS receiver 110 accepts the differential input signals
`from terminals TXiA and TXiB and converts them to a
`single-ended output signal DiOUT. The LVDS Standard
`specifies the properties of LVDS receiver 110. The present
`application is directed to differential-signal generators: a
`comprehensive discussion of receiver 110 is not included in
`the present application.
`FIG. 2 (prior art) schematically depicts LVDS generator
`100 of FIG. 1. Generator 100 includes a preamplifier 200
`connected to a driver stage 205. Preamplifier 200 receives
`the single-ended data signal DiIN and produces a pair of
`complementary data signals D and D/ (signal names termi-
`nating in “/” are active low signals). Unless otherwise
`specified, each signal is referred to by the corresponding
`node designation depicted in the figures. Thus, for example,
`the input terminal and input signal to generator 100 are both
`designated DiIN. In each instance, the interpretation of the
`node designation as either a signal or a physical element is
`clear from the context.
`
`Driver stage 205 includes a PMOS load transistor 207 and
`an NMOS load transistor 209, each of which produces a
`relatively stable drive current in response to respective bias
`voltages PBIAS and NBIAS. Driver stage 205 additionally
`includes four drive transistors 211, 213, 215, and 217.
`If signal DiIN is a logic one (e.g., 3.3 volts), preamplifier
`200 produces a logic one on terminal D and a logic zero
`(e.g., zero volts) on terminal D/. The logic one on terminal
`D turns on transistors 211 and 217, causing current to flow
`down through transistors 207 and 211, up though termina-
`tion load RL, and down through transistors 217 and 209 to
`ground (see the series of arrows 219). The current through
`termination load RL develops a negative voltage between
`output terminals TXiA and TXiB.
`Conversely, if signal DiIN is a logic zero, preamplifier
`200 produces a logic zero on terminal D and a logic one on
`
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`terminal D/. The logic one on terminal D/ turns on transistors
`213 and 215, causing current to flow down through transistor
`207, transistor 215, termination load RL, transistor 213, and
`transistor 209 to ground (see the series of arrows 221). The
`current through termination load RL develops a positive
`voltage between output terminals TXiA and TXiB.
`FIG. 3 (prior art) is a waveform diagram 300 depicting the
`signaling sense of the voltages appearing across termination
`load RL of FIGS. 1 and 2. LVDS generator 100 produces a
`pair of differential output signals on terminals TXiA and
`TXiB. The LVDS Standard requires that
`the voltage
`between terminals TXiA and TXiB remain in the range of
`250 mV to 450 mV, and that the voltage midway between the
`two differential voltages remains at approximately 1.2 volts.
`Terminal TXiA is negative with respect to terminal TXiB
`to represent a binary one and positive with respect
`to
`terminal B to represent a binary zero.
`Aprogrammable logic device (PLD) is a well-known type
`of IC that may be programmed by a user (e.g., a circuit
`designer) to perform specified logic functions. Most PLDs
`contain some type of input/output block (IOB) that can be
`configured either to receive external signals or to drive
`signals off chip. One type of PLD, the field-programmable
`gate array (FPGA), typically includes an array of config-
`urable logic blocks (CLBS) that are programmably inter-
`connected to each other and to the programmable IOBs.
`Configuration data loaded into internal configuration
`memory cells on the FPGA define the operation of the FPGA
`by determining how the CLBS,
`interconnections, block
`RAM, and IOBs are configured.
`IOBs configured as output circuits typically provide
`single-ended logic signals to external devices. As with other
`types of circuits, PLDs would benefit from the performance
`advantages offered by driving external signals using differ-
`ential output signals. There is therefore a need for IOBs that
`can be configured to provide differential output signals.
`There is also a need for LVDS output circuits that can be
`tailored to optimize performance for different loads.
`SUMMARY
`
`The present invention addresses the need for differential-
`signal output circuits that can be tailored for use with
`different loads. In accordance with one embodiment, one or
`more driver stages can be added, as necessary, to provide
`adequate power for driving a given load. Driver stages are
`added by programming one or more programmable
`elements, such as memory cells, fuses, and antifuses.
`A differential driver in accordance with another embodi-
`
`ment includes a multi-stage delay element connected to a
`number of consecutive driver stages. The delay element
`produces two or more pairs of complementary input signals
`in response to each input-signal transition, each successive
`signal pair being delayed by some amount relative to the
`previous signal pair. The pairs of complementary signals are
`conveyed to respective driver stages, so that each driver
`stage successively responds to the input-signal transition.
`The output terminals of the driver stages are connected to
`one another and to the output terminals of the differential
`driver. The differential driver thus responds to each input-
`signal transition with increasingly powerful amplification.
`The progressive amplification produces a corresponding
`progressive reduction in output resistance, which reduces
`the noise normally associated with signal reflection.
`Extendable and multi-stage differential amplifiers in
`accordance with the invention can be adapted for use in
`PLDs. In one embodiment, adjacent pairs of IOBs are each
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`3
`provided with half of the circuitry required to produce LVDS
`signals. Adjacent pairs of IOBs can therefore be used either
`individually to provide single-ended input or output signals
`or can be combined to produce differential output signals.
`This summary does not
`limit the invention, which is
`instead defined by the appended claims.
`
`BRIEF DESCRIPTION OF THE FIGURES
`
`FIG. 1 (prior art) illustrates an LVDS generator 100
`connected to an LVDS receiver 110 via a transmission line
`115.
`
`FIG. 2 (prior art) schematically depicts LVDS generator
`100 of FIG. 1
`
`FIG. 3 (prior art) is a waveform diagram 300 depicting the
`signaling sense of the voltages appearing across termination
`load RL of FIGS. 1 and 2.
`
`FIG. 4 depicts an extensible differential amplifier 400 in
`accordance with an embodiment of the invention.
`
`FIG. 5A is a schematic diagram of predriver 405 of FIG.
`
`4
`
`FIG. 5B is a schematic diagram of driver 415 of FIG. 4.
`FIG. 5C is a schematic diagram of extended driver 410 of
`FIG. 4.
`
`FIG. 6 depicts a multi-stage driver 600 in accordance with
`another embodiment of the invention.
`
`FIG. 7A schematically depicts a predriver 700 in which a
`predriver is connected to delay circuit 605 of FIG. 6 to
`develop three complementary signal pairs.
`FIG. 7B schematically depicts differential-amplifier
`sequences 610 and 615 and termination load 620, all of FIG.
`6.
`
`FIGS. 8A and 8B schematically depict a programmable
`bias-voltage generator 800 in accordance with an embodi-
`ment of the invention.
`
`DETAILED DESCRIPTION
`
`FIG. 4 depicts an extensible differential amplifier 400 in
`accordance with an embodiment of the invention. Amplifier
`400 includes a predriver 405 connected to a pair of driver
`stages 410 and 415. The combination of predriver 405 and
`driver 415 operates as described above in connection with
`FIGS. 2 and 3 to convert the single-ended input on terminal
`DiIN into differential output signals on lines TXiA and
`TXiB. In accordance with the invention, driver 410 can be
`activated as needed to provide additional drive power. In one
`embodiment, drivers 410 and 415 reside within a pair of
`adjacent programmable IOBs (collectively labeled 417) and
`lines TXiA and TXiB connect to the respective input/
`output (I/O) pads of the pair. This aspect of the invention is
`detailed below.
`
`The program state of a configuration bit 420 determines
`whether amplifier 400 is enabled, and the program state of
`a second configuration bit 425 determines whether the driver
`stage of amplifier 400 is extended to include driver 410. An
`exemplary configuration bit is described below in connec-
`tion with FIG. 8A.
`
`If bit 420 is programmed to provide a logic one on “enable
`differential signaling” line ENiDS, then predriver 405 and
`driver 415 function in a manner similar to that described
`above in connection with FIG. 2. If desired,
`the drive
`circuitry can be extended to include driver 410 by program-
`ming bit 425 to provide a logic one on “extended differential
`signaling” line XiDS. The signals on lines XiDS and
`ENiDS are logically combined using an AND gate 430 to
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`produce an “enable termination load” signal ENiT to driver
`415. This signal and its purpose are described below in
`connection with FIG. 5B.
`
`FIG. 5A is a schematic diagram of an embodiment of
`predriver 405 of FIG. 4. Predriver 405 includes a pair of
`conventional tri-state drivers 500 and 502. A conventional
`
`inverter 504 provides the complement of signal ENiDS.
`Amplifier 400 is inactive when signals ENiDS and
`ENiDS/ are low and high, respectively. These logic levels
`cause tristate drivers 500 and 502 to disconnect
`input
`terminal DiIN from respective tristate output terminals T1
`and T2. Signal ENiDS and its complementary signal
`ENiDS/ also connect terminals T1 and T2 to respective
`supply voltages VCCO and ground by turning on a pair of
`transistors 506 and 508. Thus, terminals T1 and T2 do not
`change in response to changes on input terminal DiIN
`when differential signaling is disabled. In the case where
`amplifier 400 is implemented using IOBs in a programmable
`logic device, amplifier 400 may be disabled to allow the
`IOBs to perform some other input or output function.
`Amplifier 400 is active when signals ENiDS and
`ENiDS/ are high and low, respectively. These logic levels
`cause tristate drivers 500 and 502 to connect input terminal
`DiIN to respective tristate output terminals T1 and T2.
`Signal ENiDS and its complementary signal ENiDS/ also
`disconnect
`terminals T1 and T2 from respective supply
`voltages VCCO and ground by turning off transistors 506
`and 508. Thus, terminals T1 and T2 change in response to
`signal DiIN when differential signaling is enabled.
`Tristate output terminals T1 and T2 connect to the respec-
`tive input terminals of an inverting predriver 510 and a
`non-inverting predriver 512. Predriver 510 includes a pair of
`conventional inverters 514 and 516. Inverter 514 produces a
`signal D, an inverted and amplified version of the signal on
`line T1; inverter 516 provides a similar signal to a test pin
`518. Predriver 512 includes three conventional inverters
`
`520, 522, and 524. Predriver 512 produces a signal D/, the
`complement of signal D. Inverter 524 provides a similar
`signal to a test pin 526.
`Each inverter within predrivers 510 and 512 is a CMOS
`inverter in which the ratios of the PMOS and NMOS
`
`transistors are as specified. These particular ratios were
`selected so that signals D and D/ transition simultaneously,
`or very nearly so. Different ratios may be appropriate,
`depending upon the process used to produce amplifier 400.
`Adjusting layout and process parameters to produce syn-
`chronized complementary signals is within the skill of those
`in the art.
`
`As discussed above in connection with FIG. 4, amplifier
`400 can be extended to include additional drive circuitry,
`which may be needed to drive some loads while remaining
`in compliance with the LVDS Standard. Returning to FIG.
`5A, a pair of NOR gates 528 and 530 facilitates this
`extension by producing a pair of complimentary extended-
`data signals DX and DX/ when signal XiDS/ is a logic zero,
`indicating the extended driver is enabled. Extended-data
`signal DX is substantially the same as signal D, and
`extended data signal DX/ is substantially the same as signal
`D/. Signals DX and DX/ are conveyed to extended driver
`410, the operation of which is detailed below in connection
`with FIG. 5C.
`
`FIG. 5B is a schematic diagram of driver 415 of FIG. 4.
`Driver 415 is similar to driver stage 205 of FIG. 2, like-
`numbered elements being the same. Unlike driver 205,
`however, driver 415 includes a programmable termination
`load 540. Further, load transistors 207 and 209 of FIG. 2 are
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`5
`replaced with pairs of parallel transistors, so that transistors
`211 and 215 connect to VCCO via respective PMOS tran-
`sistor 532 and 533, instead of via a single transistor 207, and
`transistors 213 and 217 connect to ground via respective
`NMOS transistors 534 and 535,
`instead of via a single
`transistor 209.
`
`Employing pairs of load transistors allows driver 415 to
`be separated into two similar parts 536 and 538, each
`associated with a respective one of terminals TXiA and
`TXiB. Such a configuration is convenient, for example,
`when driver 415 is implemented on a PLD in which termi-
`nals TXiA and TXiB connect to neighboring I/O pins.
`Each part 536 and 538 can be implemented as a portion of
`the IOB (not shown) associated with the respective one of
`terminals TXiA and TXiB. Termination load 540 can be
`part of either IOB, neither IOB, or can be split between the
`two. In one embodiment, transistor 542 is included in the
`IOB that includes part 536, and transistor 543 is included in
`the IOB that includes part 538.
`Programmable termination load 540 includes a pair of
`transistors 542 and 543,
`the gates of which connect
`to
`terminal ENiT. As shown in FIG. 4, the signal ENiT is
`controlled through AND gate 430 by configuration bits 420
`and 425. Termination load 540 is active (conducting) only
`when differential signaling is enabled in the non-extended
`mode. This condition is specified when configuration bit 420
`is set to a logic one and configuration bit 425 is set to a logic
`zero.
`
`Driver 415 includes a number of terminals that provide
`appropriate bias voltages. Terminals PBIAS and NBIAS
`provide respective bias levels establish the gain driver 415,
`and common terminals PCOM and NCOM conventionally
`establish the high and low voltage levels on output terminals
`TXiA and TXiB. Driver 415 shares the bias and common
`terminals with extended driver 410 (See FIG. 5C).
`in
`The bias levels PBIAS and NBIAS are important
`defining LVDS signal quality. In one embodiment, NMOS
`transistors 534 and 535 are biased to operate in saturation to
`sink a relatively stable current, whereas PMOS transistors
`532 and 533 are biased to operate in a linear region.
`Operating transistors 532 and 533 in a linear region reduces
`the output resistances of those devices, and the reduced
`resistance tends to dissipate signal reflections returning to
`terminals TXiA and TXiB. Reduced reflections translate
`into reduced noise, and reduced noise allows signals to be
`conveyed at higher data rates. Circuits for developing appro-
`priate bias levels for the circuits of FIGS. 5A—7B are
`discussed below in connection with FIGS. 8A and 8B.
`
`FIG. 5C is a schematic diagram of one embodiment of
`extended driver 410 of FIG. 4. Extended driver 410 includes
`
`a pair of driver stages 544 and 546 and a programmable
`termination load 548. Driver stages 544 and 546 can be
`included, for example, in respective adjacent IOBs on a
`PLD. Termination load 548 can be part of either IOB, neither
`IOB, or can be split between the two. The various terminals
`of FIG. 5C are connected to like-named terminals of FIGS.
`5A and 5B.
`
`Driver stage 544 includes a PMOS load transistor 550, a
`pair of NMOS differential-driver transistors 552 and 554
`having their gates connected to respective extended-driver
`input signals DX and DX/, a diode-connected PMOS tran-
`sistor 556, and a PMOS transistor 558 connected as a
`capacitor 14 between terminal VCCO and terminal PCOM.
`Transistors 550, 552, and 554 combined amplify the
`extended-driver signals DX and DX/ to produce an ampli-
`fied output signal on output
`terminal TXiA.
`In one
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`transistor 556 is diode-connected between
`embodiment,
`terminals PCOM and VCCO to establish the appropriate
`level for line PCOM, which is common to both drivers 410
`and 415. Finally, transistor 558 can be sized or eliminated as
`desired to minimize noise on line PCOM. Driver stage 546
`is identical to driver stage 544, except that lines DX and DX/
`are connected to the opposite differential driver transistors.
`Consequently, the signals on output terminals TXiA and
`TXiB are complementary. Driver stages 544 and 546 thus
`supplement the drive strength provided by driver stage 415.
`As shown in FIG. 4,
`the extend-differential-signaling
`signal XiDS is a logic one when CBIT 425 is programmed.
`However, programming CBIT 425 causes AND gate 430 to
`output a logic zero, disabling termination load 532 of FIG.
`5B. Thus, programming CBIT 425 substitutes termination
`load 548 for termination load 532, thereby increasing the
`termination load resistance to an appropriate level. In one
`embodiment,
`the resistance of termination load 532 is
`selected so that the resulting output signal conforms to the
`LVDS Standard.
`
`FIG. 6 depicts a multi-stage driver 600 in accordance with
`another embodiment of the invention. Driver 600 includes a
`
`multi-stage delay circuit 605, a first sequence of differential
`amplifiers 610, a second sequence of differential amplifiers
`615, and a termination load 620. For illustrative purposes,
`the amplifiers of sequences 610 and 615 are referred to as
`“high-side” and “low-side” amplifiers, respectively. In dif-
`ferent embodiments, each amplifier sequence 610 and 615
`can be implemented as a portion of the IOB (not shown)
`associated with the respective one of terminals TXiA and
`TXiB. Termination load 620 can be part of either IOB,
`neither IOB, or can be split between the two.
`Delay circuit 605 receives a pair of complementary sig-
`nals D and D/ on a like-named pair of input terminals. A
`sequence of delay elements—conventional buffers 625 in
`the depicted example—provides a first pair of delayed
`complementary signals D1 and D1/ and a second pair of
`delayed complementary signals D2 and D2/.
`Sequence 610 includes three differential amplifiers 630,
`631, and 632, the output terminals of which connect to one
`another and to output terminal TXiA. The differential input
`terminals of each of these high-side amplifiers connect to
`respective complementary terminals from delay circuit 605.
`That is, the non-inverting (+) and inverting (—) terminals of
`differential amplifier 630 connect to respective input termi-
`nals D and D/, the non-inverting and inverting terminals of
`differential amplifier 631 connect to respective input termi-
`nals D1 and D1/, and the non-inverting and inverting ter-
`minals of differential amplifier 632 connect to respective
`input terminals D2 and D2/. When the signal on terminal D
`transitions from low to high, each of amplifiers 630, 631,
`and 632 consecutively joins in pulling the voltage level on
`terminal TXiA high as the signal edges on terminals D and
`D/ propagate through delay circuit 605. Conversely, when
`the signal on terminal D transitions from high to low, each
`of amplifiers 630, 631, and 632 consecutively joins in
`pulling the voltage level on terminal TXiA low.
`Sequence 615 includes three differential amplifiers 634,
`635, and 636, the output terminals of which connect to one
`another and to terminal TXiB. Sequence 615 is similar to
`sequence 610, except that the differential input terminals of
`the various low-side differential amplifiers are connected to
`opposite ones of the complementary signals from delay
`circuit 605. Thus, when the signal on terminal D transitions
`from low to high, each of amplifiers 634, 635, and 636
`consecutively joins in pulling the voltage level on terminal
`
`ZTE/SAMSUNG 1017-0014
`
`|PR2018-00274
`
`ZTE/SAMSUNG 1017-0014
`IPR2018-00274
`
`
`
`US 6,366,128 B1
`
`7
`TXiB low as the signal edges on terminals D and D/
`propagate through delay circuit 605, and when the signal on
`terminal D transitions from high to low, each of amplifiers
`634, 635, and 636 consecutively joins in pulling the voltage
`level on terminal T'XiB high.
`Driver stage 600 is similar to driver stage 415 of FIGS. 4
`and 5A, except that driver stage 600 progressively increases
`the drive strength used to provide amplified signals across
`termination load 620, and consequently progressively
`reduces the output resistance of driver stage 600. Progres-
`sively reducing the output resistance of amplifier 600
`reduces the amplitude of reflected signals. This effect, in
`turn, reduces the noise and increases the useable data rate of
`the LVDS circuitry. While illustrated as having three driver
`stages, other embodiments of amplifier 600 include more or
`fewer stages. FIG. 7A schematically depicts a predriver 700
`in which predriver 405, detailed in FIG. 5A, is connected to
`delay circuit 605 of FIG. 6 to develop the three comple-
`mentary signal pairs (e.g., D and D/) of FIG. 6. The various
`elements of predriver 405 are described above in connection
`with FIG. 5A, like-numbed elements being identical. In one
`embodiment, each buffer 625 is an instance of non-inverting
`delay circuit 512. FIG. 7B schematically depicts differential-
`amplifier sequences 610 and 615 and termination load 620,
`all of FIG. 6. The differential amplifiers in sequences 610
`and 615 are substantially identical, except the D and D/ input
`terminals are reversed. The following description is limited
`to a single differential amplifier (630) for brevity. Differen-
`tial amplifier 630 includes a PMOS load transistor 700, an
`NMOS load transistor 705, and a pair of active transistors
`710 and 715 having their respective gates connected to data
`inputs D and D/. One embodiment of amplifier 400 of FIG.
`4 employs driver stage 600 in place of driver 415 (detailed
`in FIG. 5B). Amplifier sequence 610 may include a capacitor
`725 between PCOM and VCCO, and amplifier sequence 615
`may include a capacitor 730 connected between NCOM and
`ground. These capacitors can be sized to minimize noise.
`FIGS. 8A and 8B schematically depict a programmable
`bias-voltage generator 800 in accordance with an embodi-
`ment of the invention. A key 802 in the bottom right-hand
`corner of FIG. 8A shows the relative arrangement of FIGS.
`8A and 8B.
`
`The portion of generator 800 depicted in FIG. 8A may be
`divided into three general areas: bias-enable circuitry 804,
`NBIAS pull-up circuitry 806, and NBIAS pull-down cir-
`cuitry 808. As their respective names imply, bias-enable
`circuitry 804 determines whether bias generator 800 is
`active, NBIAS pull-up circuitry 806 can be used to raise the
`NBIAS voltage level, and NBIAS pull-down circuitry 808
`can be used to reduce the NBIAS voltage level. The NBIAS
`pull-up and pull-down circuitry are programmable to allow
`users to vary the NBIAS voltage as desired.
`Bias-enable circuitry 804 includes a configuration bit
`(CBIT) 810, an inverter 812, a PMOS transistor 814, and, in
`FIG. 8B, a PMOS transistor 815 and a pair of NMOS
`transistors 816 and 817. CBIT 810 is conventional, in one
`embodiment including an SRAM configuration memory cell
`818 connected to a level-shifter 820. Level-shifter 820 is
`
`used because bias generator 800 is a portion of the output
`circuitry of a PLD, and operates at higher voltage (e.g., 3.3
`volts) than the core circuitry (e.g., 1.5 volts) of the PLD:
`level-shifter 820 increases the output voltage of SRAM cell
`816 to an appropriate voltage level. Some embodiments that
`employ lower core voltages use thicker gate insulators in the
`transistors of the I/O circuitry. The gate insulators of differ-
`ing thickness can be formed using a conventional dual-oxide
`process. In one embodiment in which the circuits depicted in
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`FIGS. 5A—8B are part of the output circuitry of a PLD, each
`of the depicted devices employs relatively thick gate insu-
`lators.
`
`Generator 800 is activated by programming SRAM cell
`818 to include a logic one,
`thereby causing bias-enable
`circuitry 804 to output a logic one on line BIAS. This logic
`one connects high-supply-voltage line HiSUP to supply
`voltage VCCO through transistor 814 and disconnects line
`PBIAS from VCCO to enable line PBIAS to carry an
`appropriate bias voltage. The inverted signal BIAS/ from
`inverter 812, a logic zero when active, disconnects lines
`NBIAS and NGATE from ground, thereby allowing those
`lines to carry respective bias voltages. The logic levels on
`lines PBIAS and NBIAS are one and zero, respectively,
`when SRAM cell 818 is set to logic zero.
`NBIAS pull-up circuitry 806 has an input terminal VBG
`connected to a conventional band-gap reference, or some
`other suitable voltage reference. The voltage level and line
`VBG turns on a PMOS transistor 822 that, in combination
`with diode-connected transistors 824 and 826, produces bias
`voltage levels on lines NGATE and NBIAS. Terminal VBG
`also connects to a pair of transmission gates 828 and 830,
`each consisting of NMOS and PMOS transistors connected
`in parallel. The transmission gates are controlled by con-
`figuration bits similar to CBIT 810. For example, transmis-
`sion gate 828 can be turned on by programming CBITiA to
`contain a logic one. The logic one produces a logic one on
`line A and, via an inverter 834, a logic zero on line Al.
`Transmission gate 828 passes the reference voltage on line
`VBG to the gate of a PMOS transistor 836, thereby reducing
`the resistance between VCCO and line NBIAS;
`consequently, the voltage level on line NBIAS rises. Tran-
`sistor 838 can be turned on and both of transmission gate
`828 and transistor 836 can be turned off by programming
`CBITiA to contain a logic zero. Transmission gate 830
`operates in the same manner as transmission gate 828, but is
`controlled by a different CBIT (CBITiB) and an associated
`inverter. One or both of transmission gates 828 and 830 can
`be turned on to raise the voltage level on line NBIAS.
`NBIAS pull-down circuitry 808 includes a pair of pro-
`grammable pull-down circuits 840 and 842 that can be
`programmed independently or collectively to reduce the bias
`voltage on terminal NBIAS. Pull-down circuits 840 and 842
`work the same way, so only circuit 840 is described.
`Pull-down circuit 840 includes three transistors 844, 846,
`and 848. The gates of transistors 844 and 846 connect to
`terminals C and C/, respectively, from a configuration bit
`CBITiC and an associated inverter 849. When CBITiC is
`programmed to contain a logic zero, transistors 844 and 848
`are turned off, isolating line NBIAS from ground; when
`CBITiC is programmed to contain a logic one, transistors
`844 and 848 are turned on and transistor 846 turned off. The
`
`reduced resistance through transistor 848 reduces the volt-