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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`
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`ZTE (USA) Inc.,
`Samsung Electronics Co., Ltd., and
`Samsung Electronics America, Inc.,
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`Petitioner
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`v.
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`Fundamental Innovation Systems International LLC,
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`Patent Owner
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`
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`DECLARATION OF JAMES T. GEIER
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`Case No. IPR2018-00274
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`ZTE/SAMSUNG 1009-0001
`IPR2018-00274
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`I.(cid:1)
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`II.(cid:1)
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`TABLE OF CONTENTS
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`Introduction .................................................................................................... 1(cid:1)
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`Background/Qualifications ............................................................................. 1(cid:1)
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`III.(cid:1) Documents and Materials Considered ............................................................ 3(cid:1)
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`IV.(cid:1) Legal Principles .............................................................................................. 3(cid:1)
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`V.(cid:1)
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`Person of Ordinary Skill in the Art ................................................................ 9(cid:1)
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`VI.(cid:1)
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`’586 Patent Background ................................................................................. 9(cid:1)
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`A.(cid:1)
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`B.(cid:1)
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`C.(cid:1)
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`Summary .............................................................................................. 9(cid:1)
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`Priority Date ......................................................................................... 9(cid:1)
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`Prosecution History ............................................................................ 10(cid:1)
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`VII.(cid:1) Technology Background & State of the Art ................................................. 10(cid:1)
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`A.(cid:1) USB Architecture ............................................................................... 11(cid:1)
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`B.(cid:1)
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`C.(cid:1)
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`D.(cid:1)
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`USB Current and Voltage Limits ....................................................... 15(cid:1)
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`USB Signaling States ......................................................................... 17(cid:1)
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`TIA/EIA-644 ...................................................................................... 20(cid:1)
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`VIII.(cid:1) Claim Construction ...................................................................................... 21(cid:1)
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`IX.(cid:1) Ground 1: Claims 8-13 are obvious in light of Theobald and Shiga. ........... 21(cid:1)
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`A.(cid:1)
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`Theobald ............................................................................................. 21(cid:1)
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`1.(cid:1)
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`2.(cid:1)
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`Resistor embodiment ............................................................... 23(cid:1)
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`Controller embodiment ............................................................ 26(cid:1)
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`B.(cid:1)
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`C.(cid:1)
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`Shiga ................................................................................................... 29(cid:1)
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`Theobald/Shiga combination ............................................................. 32(cid:1)
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`D.(cid:1) Application of Theobald/Shiga combination to claims 8-13 ............. 41(cid:1)
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`1.(cid:1)
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`2.(cid:1)
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`3.(cid:1)
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`4.(cid:1)
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`5.(cid:1)
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`6.(cid:1)
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`Claim 8 ..................................................................................... 41(cid:1)
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`Claim 9 ..................................................................................... 52(cid:1)
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`Claim 10 ................................................................................... 53(cid:1)
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`Claim 11 ................................................................................... 55(cid:1)
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`Claim 12 ................................................................................... 60(cid:1)
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`Claim 13 ................................................................................... 60(cid:1)
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`X.(cid:1) Ground 2: Claims 10 and 13 are obvious in light of Kanamori. .................. 61(cid:1)
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`A.(cid:1) Kanamori ............................................................................................ 61(cid:1)
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`B.(cid:1)
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`Application of Kanamori to claims 10 and 13 ................................... 64(cid:1)
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`1.(cid:1)
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`2.(cid:1)
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`Claim 10 ................................................................................... 64(cid:1)
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`Claim 13 ................................................................................... 74(cid:1)
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`Geier Declaration
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`I.
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`Introduction
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`1. My name is James T. Geier. I submit this declaration on behalf of
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`ZTE (USA) Inc., Samsung Electronics Co., Ltd., and Samsung Electronics
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`America, Inc. (“Petitioner”), which I understand are challenging the validity of
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`claims 8-13 (“the challenged claims”) of U.S. Patent No. 7,834,586 B2 (“the 586
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`patent”) in a petition for inter partes review.
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`2.
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`I have been asked to provide an opinion on the validity of the
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`challenged claims. In my opinion, claims 8-13 of the 586 patent are obvious based
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`on the following grounds:
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`• U.S. Patent No. 5,925,942 (“Theobald”) and U.S. Patent No. 6,625,738
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`(“Shiga”) render obvious claims 8-13 of the ’586 patent; and
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`• U.S. Patent Application Publication No. 2008/0272741 (“Kanamori”)
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`renders obvious claims 10 and 13 of the ’586 patent.
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`II. Background/Qualifications
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`3.
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`Appendix A to this declaration is my curriculum vitae, which sets
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`forth my qualifications.
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`4.
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`I received a B.S. degree in Electrical Engineering from California
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`State University in 1985. In 1990, I received an M.S. degree in Electrical
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`Engineering from the Air Force Institute of Technology.
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`5.
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`I have 30 years’ experience in the communications industry designing,
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`analyzing, and implementing communications systems, wireless networks, and
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`mobile devices. I have authored over a dozen books on mobile and wireless topics,
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`including Designing and Deploying 802.11 Wireless Networks (Cisco Press),
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`Implementing 802.1X Security Solutions (Wiley), Wireless Networking Handbook
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`(New Riders) and Network Re-engineering (McGraw-Hill). I have been an active
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`participant within standards organizations, such as the IEEE 802.11 Working
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`Group and the Wi-Fi Alliance. I have served as Chairman of the IEEE Computer
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`Society, Dayton Section, and various conferences.
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`6.
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`I have significant experience with USB, which includes reviewing and
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`analyzing USB specifications and designing and integrating corresponding USB
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`interfaces within various applications. Since 1998, I have been analyzing the
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`operation and limitations of USB in relation to mobile devices that I have
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`designed. For example, during 1998-1999, I analyzed and tested the integration of
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`USB into Monarch Marking Systems bar code scanners and printers. Also, during
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`2008-2009, I integrated USB into a microcontroller-based monitoring and control
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`system, which involved writing software drivers to interface the microcontroller to
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`the functionality of a USB port. In addition, I have analyzed how USB impacts the
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`operation and specifications of many other devices, such as wireless IP phones and
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`patient heart monitors, which I’ve been part of designing.
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`III. Documents and Materials Considered
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`7.
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`Appendix B to this declaration lists materials that I have considered in
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`rendering the opinions that I express in this declaration. In forming my opinions, I
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`have also relied on my experience and education.
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`IV. Legal Principles
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`8.
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`I am not an attorney. I offer no opinions on the law. But counsel has
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`informed me of legal standards that apply to the issue of patent validity. I have
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`applied these standards in arriving at my conclusions.
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`9.
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`I understand that in an inter partes review the petitioner has the burden
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`of proving a proposition of unpatentability by a preponderance of the evidence. I
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`understand this standard is different from the standard that applies in a district
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`court, where I understand a challenger bears the burden of proving invalidity by
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`clear and convincing evidence.
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`10.
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`I understand that a patent claim is invalid based on anticipation if a
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`single prior art reference discloses all of the features of that claim, and does so in a
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`way that enables one of ordinary skill in the art to make and use the invention.
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`Each of the claim features may be expressly or inherently present in the prior art
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`reference. I understand that if the prior art necessarily functions in accordance
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`with, or includes a claim’s feature, then that prior art inherently discloses that
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`feature. I have relied on this understanding in expressing the opinions set forth
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`below.
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`11.
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`I understand that a prior art reference describes the claimed invention
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`if it either expressly or inherently describes each and every feature set forth in the
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`claim; i.e., in determining whether a single item of prior art anticipates a patent
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`claim, one should take into consideration not only what is expressly disclosed in
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`that item, but also what is inherently present as a natural result of the practice of
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`the system or method disclosed in that item.
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`12.
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`I understand that to establish inherency, the evidence must make clear
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`that the missing descriptive matter is necessarily present in the item of prior art and
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`that it would be so recognized by persons of ordinary skill in the art. I also
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`understand that prior art use of the claimed patented invention that was accidental,
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`unrecognized, or unappreciated at the time of filing can still be an invalidating
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`anticipation.
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`13.
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`I understand that although multiple prior art references may not be
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`combined to show anticipation, additional references may be used to interpret the
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`allegedly anticipating reference and shed light on what it would have meant to
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`those skilled in the art at the time of the invention. These additional references
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`must make it clear that the missing descriptive matter in the patent claim is
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`necessarily present in the allegedly anticipating reference, and that it would be so
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`recognized by persons of ordinary skill in the art.
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`14.
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`I understand that a patent may not be valid even though the invention
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`is not identically disclosed or described in the prior art if the differences between
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`the subject matter sought to be patented and the prior art are such that the subject
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`matter as a whole would have been obvious to a person having ordinary skill in the
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`art in the relevant subject matter at the time the invention was made.
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`15. To determine if a claim is obvious, the following factors should be
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`considered: (1) the level of ordinary skill in the art at the time the invention was
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`made; (2) the scope and content of the prior art; (3) the differences between the
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`claimed invention and the prior art; and (4) secondary considerations, including
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`evidence of commercial success, long-felt but unsolved need, unsuccessful
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`attempts by others, copying of the claimed invention, unexpected and superior
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`results, acceptance and praise by others, independent invention by others, and the
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`like.
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`16. For example, I understand that the combination of familiar elements
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`according to known methods is likely to be obvious when it does no more than
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`yield predictable results. I also understand that an obviousness analysis need not
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`seek out precise teachings directed to the specific subject matter of the challenged
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`claim because a court can take account of the inferences and/or creative steps that a
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`person of ordinary skill in the art would employ.
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`17.
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`I understand that the obviousness determination of an invention turns
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`on whether a hypothetical person with ordinary skill and full knowledge of all the
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`pertinent prior art, when faced with the problem to which the claimed invention is
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`addressed, would be led naturally to the solution adopted in the claimed invention
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`or would naturally view that solution as an available alternative. Facts to be
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`evaluated in this analysis include:
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`• The scope and contents of the prior art;
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`• Differences between the prior art and the claims at issue;
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`• The level of ordinary skill in the pertinent art; and
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`• Evidence of objective factors suggesting or negating obviousness.
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`• I understand that the following rationales may be used to determine whether
`a piece of prior art can be combined with other prior art or with other
`information within the knowledge of one of ordinary skill in the art:
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`• Combining prior art elements according to known methods to yield
`predictable results;
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`• Simple substitution of one known element for another to obtain predictable
`results;
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`• Use of known techniques to improve similar devices (methods, or products)
`in the same way;
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`• Applying a known technique to a known device (method, or product) ready
`for improvement to yield predictable results;
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`• “Obvious to try” - choosing from a finite number of identified, predictable
`solutions, with a reasonable expectation of success;
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`• Known work in one field of endeavor may prompt variations of it for use in
`either the same field or a different one based on design incentives or other
`market forces if the variations would have been predictable to one of
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`ordinary skill in the art; or
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`• Some teaching, suggestion, or motivation in the prior art that would have led
`one of ordinary skill to modify the prior art reference or to combine prior art
`reference teachings to arrive at the claimed invention.
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`18.
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`I understand that when a work is available in one field of endeavor,
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`design incentives and/or other market forces, for example, can prompt variations of
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`it, either in the same field or a different one. Moreover, if a person of ordinary skill
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`can implement a predictable variation, I understand that that likely bars its
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`patentability.
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`19.
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`I understand that obviousness must be tested as of the time the
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`invention was made. I understand that the test for obviousness is what the
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`combined teachings of the prior art references would have suggested, disclosed, or
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`taught to one of ordinary skill in the art. In particular, it is my understanding that a
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`patent claim is invalid based upon obviousness if it does nothing more than
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`combine familiar elements from one or more prior art references or products
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`according to known methods to yield predictable results. For example, I understand
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`that where a technique has been used to improve one device, and a person of
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`ordinary skill in the art would have recognized that it would improve similar
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`devices in the same way, using that technique is obvious. I understand that
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`obviousness can be proved by showing that a combination of elements was
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`obvious to try, i.e.: that it does no more than yield predictable results; implements a
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`predictable variation; is no more than the predictable use of prior art elements
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`according to their established functions; or when there is design need or market
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`pressure to solve a problem and there are a finite number of identified, predictable
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`solutions. I have been further informed that when a patent claim simply arranges
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`old elements with each element performing the same function it had been known to
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`perform and yields results no more than one would expect from such an
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`arrangement, the combination is obvious.
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`20.
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`I understand that another factor to be considered is common sense.
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`For example, I understand that common sense teaches that familiar items may have
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`obvious uses beyond their primary purposes, and, in many cases, a person of
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`ordinary skill will be able to fit the teachings of multiple patents together like
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`pieces of a puzzle.
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`21.
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`I understand that the Supreme Court articulated additional guidance
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`for obviousness in its KSR decision. My understanding is that the Supreme Court
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`said that technical people of ordinary skill look for guidance in other solutions to
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`problems of a similar nature, and that the obviousness inquiry must track reality,
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`and not legal fictions. I have relied on these understandings in expressing the
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`opinions set forth below.
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`22.
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`I understand that a new use of an old product or material cannot be
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`claimed as a new product; the apparatus or system itself is old and cannot be
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`patented. I further understand that, in general, merely discovering and claiming a
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`new benefit to an old process cannot render the process newly patentable.
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`V.
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`Person of Ordinary Skill in the Art
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`23. For purposes of this declaration, I have been asked to apply the
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`following standard for a person of ordinary skill in the art (POSITA) of the subject
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`matter of the ’586 patent: the POSITA would have had a master’s degree in
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`electrical engineering, computer science, or a related field, plus 2-3 years of
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`experience with Universal Serial Bus (“USB”).
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`VI.
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`’586 Patent Background
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`A.
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`Summary
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`24. The ’586 patent “relates generally to power adapters.”1 The ’586
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`patent has 13 claims.
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`B.
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`Priority Date
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`25. The ’586 patent issued from U.S. Patent Application No. 12/714,204,
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`which was filed on February 26, 2010.2 That application claims priority through a
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`series of continuations to two provisional applications: (1) U.S. Provisional
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`Application No. 60/273,021 (“the ’021 provisional”), filed March 1, 2001; and
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`(2) U.S. Provisional Application No. 60/330,486 (“the ’486 provisional”), filed
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`October 23, 2001.
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`1 ’586 patent at 1:34.
`2 ’586 file history at 48.
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`26. However, none of the ’586 patent’s priority applications discloses that
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`the identification signal is a result of using a resistance between the D+ and D- data
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`lines (which is the claim element that claims 10 and 13 add). Specifically, neither
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`the ’021 provisional nor the ’486 provisional nor any of the other priority
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`applications teaches or suggests that the identification signal is a result of using a
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`resistance between the D+ and D- data lines.
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`27. Therefore, the earliest possible priority date for claims 10 and 13 is
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`February 26, 2010, the ’586 patent’s actual filing.
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`C.
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`Prosecution History
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`28. During prosecution, the examiner issued a non-final office action,
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`rejecting every pending claim on the ground of nonstatutory obviousness-type
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`double patenting over claims 1-12 of U.S. Patent No. 7,737,657.3 In response, the
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`applicant filed a terminal disclaimer.4 In response, the examiner issued a notice of
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`allowance,5 leading to the issuance of the ’586 patent.6
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`VII. Technology Background & State of the Art
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`29. As of March 1, 2001 (the ’586 patent’s claimed priority date),
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`POSITAs would have had the following background knowledge of the state of the
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`3 ’586 file history at 153-157.
`4 ’586 file history at 169-178.
`5 ’586 file history at 184-187.
`6 ’586 file history at 201.
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`art.
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`A. USB Architecture
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`30. Since its inception in 1995, the USB Implementers Forum, Inc.
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`(“USB-IF”) has been responsible for the advancement and adoption of USB
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`technology. As of December 2000, USB-IF had more than 900 member companies
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`that helped facilitate the development of USB.
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`31. USB-IF standardized USB technology in the USB specification and
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`its various revisions. On September 23, 1998, USB-IF released Universal Serial
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`Bus Specification, Revision 1.1 (“USB 1.1”), which was widely adopted by
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`industry leaders and consumers. On April 27, 2000, USB-IF released USB
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`Revision 2.0 (“USB 2.0”).7 Among USB 2.0’s improvements were faster speeds
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`and additional functionality. Like USB 1.1, USB 2.0 was widely adopted by the
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`industry.
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`32. USB 1.1 and 2.0 specified the architecture for a USB system.
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`Generally, a USB system includes a USB host, one or more USB devices, and a
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`USB interconnect.8 A USB host (e.g., a laptop computer system) interacts with
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`USB devices and is responsible for tasks such as (i) detecting the attachment and
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`removal of USB devices; (ii) managing control and data flow between the host and
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`7 USB 2.0 at 1.
`8 USB 2.0 at 15; USB 1.1 at 15.
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`USB devices; (iii) collecting status and activity statistics; and (iv) providing power
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`to attached USB devices.9 A USB device connects to the USB host, and falls into
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`one of two categories: (i) a hub, which has the ability to provide additional USB
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`attachment points, or (ii) a function, which is a device that is able to transmit or
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`receive data or control information over the USB bus (e.g., a peripheral device,
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`such as a keyboard, mouse, or mobile phone).10 A USB interconnect is the manner
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`in which USB devices are connected and communicate with the host.11 The
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`following figure depicts a typical USB architectural configuration of a USB host,
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`interconnect, and devices:12
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`USB 2.0 at Figure 4-4.
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`9 USB 2.0 at 24; USB 1.1 at 24.
`10 USB 2.0 at 22-24; USB 1.1 at 21-24.
`11 USB 2.0 at 15; USB 1.1 at 15.
`12 USB 2.0 at Figure 4-4.
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`33. USB 1.1 and 2.0 also specified the USB cable structure.13 The USB
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`cable “consist[ed] of four conductors, two power conductors, and two signal
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`conductors.”14 The following figure from USB 2.0 depicts the four wires within a
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`USB cable.15
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`USB 2.0 at Figure 4-2.
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`
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`VBUS and GND deliver power, and D+ and D- carry signals for communication
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`between a USB host and the connected device.16
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`34. USB 1.1 and 2.0 also specified the USB connector structure.17 For
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`example, USB 1.1 and USB 2.0 specified Series “A” and Series “B” connectors.
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`“Table 6-1 provides the standardized contact terminating assignments by numbers
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`and electrical value for Series ‘A’ and Series ‘B’ connectors.”18
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`13 USB 2.0 at 86; USB 1.1 at 74.
`14 USB 2.0 at 86; USB 1.1 at 74.
`15 USB 2.0 at Figure 4-2.
`16 USB 2.0 at 17-18; USB 1.1 at 17.
`17 USB 2.0 at 85, 94; USB 1.1 at 73, 82.
`18 USB 2.0 at 94; USB 1.1 at 82.
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`USB 2.0 at Figure 4-2.
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`According to USB 1.1 and USB 2.0, “[a]ll USB devices must have the standard
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`
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`Series ‘A’ connector.”19 “The ‘B’ connector allows device vendors to provide a
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`standard detachable cable.”20
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`USB 2.0 at Figure 6-1.
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`35. USB 2.0 also specified how the USB host is to configure a USB
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`
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`19 USB 2.0 at 85; USB 1.1 at 73.
`20 USB 2.0 at 85; USB 1.1 at 73.
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`device. For example, USB 2.0 stated that “[w]hen a USB device is attached to or
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`removed from the USB, the host uses a process known as bus enumeration to
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`identify and manage the device state changes necessary.”21 In its “Bus
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`Enumeration” section, USB 2.0 specified the bus-enumeration requirements,
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`including eight actions taken “[w]hen a USB device is attached to a powered port.”
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`B. USB Current and Voltage Limits
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`36. USB 2.0 also imposed certain current and voltage limits on VBUS.
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`For example, USB 2.0 limited a USB device’s current draw on VBUS to “one unit
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`load [i.e., 100 mA] or less until configured.”22 USB 2.0 also stated that
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`“[d]epending on the power capabilities of the port to which the device is attached,
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`a USB device may be able to draw up to five unit loads [i.e., 500 mA] from VBUS
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`after configuration.” As shown below, USB 2.0 also imposed a 5.25 V limit on the
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`VBUS line.23
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`USB 2.0 at Table 7-7 (in part).
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`21 USB 2.0 at 243.
`22 USB 2.0 at 245.
`23 USB 2.0 at 175, 178.
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`37. Soon after USB was released, practitioners recognized that the USB
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`limit of 500 mA posed problems in many contexts requiring more power. For
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`example, Amoni discloses:
`
`“One problem with the universal serial bus is that it
`provides only one voltage. Devices that operate at
`different voltages or have high power requirements are
`required to supply their own voltage sources and power
`sources. In some environments, for instance, the retail
`point-of-sale environment, this additional cabling for
`power creates a non-aesthetic appearance at the store
`front.”24
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`Similarly, in the context of a USB speakerphone system, Rogers discloses:
`
`“One difficulty with the existing USB is that it has only a
`limited capability to provide power to a connected
`device. As it is generally known, USB has two wires in
`the cable, which supply 5 VDC. Current is limited to 0.5
`Amp. Additionally, any given device can only use 0.1
`Amp. USB allows devices to be chained, so all chained
`devices must share the same power. This means that the
`maximum power available is 2.5 Watts, with 0.5 Watt for
`each device. This is too little for many potential
`devices.”25
`
`38. Practitioners overcome the limit and created systems in which a
`
`device connected through USB to a second device drew power from the latter in
`
`excess of the 500 mA standard limit. For example, Amoni discloses that two
`
`devices connected through USB could negotiate the amount of current to be drawn
`
`
`24 Amoni at 2:19-26.
`25 Rogers at 10:67-11:8.
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`Geier Declaration
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`by one of the devices from the other, and that through such negotiation, the one
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`device could draw more than 3 A of current from the other.26 Similarly, Dougherty
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`discloses that a mobile computer connected to a docking station through USB
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`could charge its battery by drawing up to 2.5 A of current “across the USB
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`connectors.”27
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`C. USB Signaling States
`
`39. USB 2.0 also specified different signaling states on the D+ and D-
`
`lines.28 Some of these states (e.g., Differential 0, Differential 1, Data J State, and
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`Data K State) transmit data while others (e.g., Single-ended 0, Single-Ended 1) are
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`used as specific signaling conditions.29 Relevant here is the SE1 condition.
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`40. USB 2.0 defined “SE1” as “a state in which both the D+ and D- lines
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`are at a voltage above VOSE1 (min), which is 0.8 V.”30 USB 2.0 also discloses that
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`the low- and full-speed USB drivers “must never ‘intentionally’ generate an SE1
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`on the bus.”31 In other words, according to USB 2.0, an abnormal data condition
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`would occur if D+ and D- were intentionally set in a high state above 0.8 V.
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`41. Finally, POSITAs would have also known that the SE1 condition
`
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`26 Amoni at 7:16-26.
`27 Dougherty at 7:49-53.
`28 USB 2.0 at 123.
`29 USB 2.0 at 144-146, Table 7-2.
`30 USB 2.0 at 123.
`31 USB 2.0 at 123.
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`would be a logical choice for signaling information about a device without
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`interfering with USB signaling. For example, U.S. Patent No. 6,625,790
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`(“Casebolt”) discloses that SE1 could be used as a special signaling mode. As
`
`shown below, the D+ and D- lines would be connected to Vcc (+5V) to signal a
`
`PS/2 adapter.32
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`Casebolt at FIG. 2C (annotated).
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`Casebolt at Table (annotated).
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`32 Casebolt at FIG. 2C (annotated), 7:41-54, Table 1.
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`Indeed, knowledge of SE1 was so common that Cypress Semiconductor integrated
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`it into their enCoRe product, stating “USB D+ and D- lines can also be used for
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`PS/2 SCLK and SDATA pins, respectively. With USB disabled, these lines can be
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`placed in a high impedance state that will pull up to VCC.”33 As yet another
`
`example, U.S. Patent No. 6,531,845 (“Kerai”) used a high state on USB D+ and D-
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`for charging.34 As shown below, both USB D+ and D- (yellow) are brought to a
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`high state in cooperation with the charging system (green) for a special charging
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`mode.35
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`Kerai at FIG. 3 (annotated).
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`
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`Therefore, POSITAs would have understood that a high state on USB D+ and D-
`
`lines could be used in a variety of contexts, including PS/2 (e.g., Casebolt’s PS/2
`
`adapter), standard USB (e.g., the keyboard in Shiga), and others (e.g., Kerai’s
`
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`33 Cypress datasheet at 21, 22, 24, 25, 41.
`34 Kerai at FIG. 3 (annotated).
`35 Kerai at FIG. 3.
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`charging scheme) and was not restricted to a single application.
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`D. TIA/EIA-644
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`42. TIA/EIA-644, also known as low-voltage differential signaling
`
`(“LVDS”), is a technical standard published in March 1996. TIA/EIA-644
`
`specifies the electrical characteristics of a differential, serial communications
`
`protocol. LVDS can operate at low power and can run at high speeds despite its
`
`use of inexpensive twisted-pair copper cables as the transmission medium. As
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`shown below, LVDS discloses the use of a termination impedance ZT that
`
`connects a differential wire pair.
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`TIA/EIA-644 at FIG. 14.
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`
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`43. The technology shown in the TIA/EIA-644 standard was widely used
`
`by the late 1990s in the field of consumer electronics. For instance, in 1997,
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`equivalent technology was incorporated into the Small Computer System Interface
`
`(“LVD SCSI”) and in 2000 it was incorporated into the Serial Advanced
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`Technology Attachment Interface (“SATA”).
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`VIII. Claim Construction
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`44. For purposes of this proceeding, in which I understand the standard
`
`for claim construction is the broadest reasonable interpretation (BRI) standard, I
`
`have been asked to apply the interpretation of the claim term in the table below.
`
`Claim Term
`
`USB enumeration
`
`
`
`Interpretation that I was asked to
`apply in this proceeding (in which the
`BRI standard applies)
`the bus-enumeration procedure specified
`in the USB 2.0 specification or an
`earlier USB specification at the time of
`the alleged invention
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`45. For every other claim term, I have applied the plain meaning of the
`
`term to persons of ordinary skill in the art.
`
`IX. Ground 1: Claims 8-13 are obvious in light of Theobald and Shiga.
`
`A. Theobald
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`46. Theobald discloses the charging system shown below.36
`
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`36 Theobald at 2:17.
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`Theobald at FIG. 1 (annotated).
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`The charging system 100 includes a base station 101 (yellow) in wireless
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`
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`communication with an electronic device 102 (green).37 The device 102 is
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`connected to a battery 103 (blue) and an accessory 104 (red).38 The device 102 has
`
`a connector 122 “for physically and electrically connecting to the accessory 104.”39
`
`While shown as a J3-type accessory connector, the connector 122 “may be any
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`other suitable multiple pin accessory connector having an external power supply
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`pin and at least one information pin.”40
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`47. The accessory 104 can be a mid-rate charger (which supplies current
`
`at 340 mA), a fast-rate charger (which supplies current at 850 mA), or another
`
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`37 Theobald at 2:17-20.
`38 Theobald at 2:17-19.
`39 Theobald at 2:63-64.
`40 Theobald at 3:23-27 (emphasis added).
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`charger (which can supply current at a different amperage).41 The connector 171
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`provides external power (e.g., 110 V AC) from an outlet (e.g., a wall outlet) to the
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`transformer/regulator 172.42 The transformer/regulator 172 ou