'948 Patent Claim2
`(P.R. 3-1(a))
`
`[948.1] A method for network
`communication by a host computer
`having a network interface that is
`connected to the host by an input/output
`bus, the method comprising:4
`
`Alacritech, Inc.’s Initial Patent Disclosures For Wistron
`Exhibit 7
`
`UNITED STATES PATENT NO. 8,805,948
`
`INFRINGEMENT CHART FOR CLAIMS 1, 3, 6-9, 11, 14-17, 19, 22-231
`
`Accused Instrumentalities And Where Each Claim Element Is Found3
`(P.R. 3-1(b)-(c))
`
`Wistron’s Accused Instrumentalities:
`
`(i) any version of its server or computer products capable of providing infringing RSC functionality (e.g., Wiwynn SV320 Server
`with Intel 82599 Controller; Wiwynn SV100G2 Server (using NM10GR card with Qlogic BCM57810 Controller); Wiwynn
`SV100G2 Server (using NM10GS card with Intel X550-AT2 Controller); Wiwynn SV300G2 Server (using NM10GR card with
`Qlogic BCM57810 Controller); Wiwynn SV300G2 Server (using NM10GS card with Intel X550-AT2 Controller); Wiwynn
`SV320G2 Server (using NM10GR card with Qlogic BCM57810 Controller); Wiwynn SV320G2 Server (using NM10GS card with
`Intel X550-AT2 Controller); Wiwynn SV324G2 Server (using NM10GR card with Qlogic BCM57810 Controller); Wiwynn
`SV324G2 Server (using NM10GS card with Intel X550-AT2 Controller); Wiwynn SV5270G2-R Server (using NM10GR card
`with Qlogic BCM57810 Controller); Wiwynn SV5270G2-R Server (using NM10GS card with Intel X550-AT2 Controller);
`Wiwynn SV5270G2-S Server (using NM10GR card with Qlogic BCM57810 Controller); Wiwynn SV5270G2-S Server (using
`NM10GS card with Intel X550-AT2 Controller); Wiwynn SV7110 Server (using NM10GR card with Qlogic BCM57810
`Controller); Wiwynn SV7110 Server (using NM10GS card with Intel X550-AT2 Controller); Wiwynn SV7220G2-N Server (using
`NM10GR card with Qlogic BCM57810 Controller); Wiwynn SV7220G2-N Server (using NM10GS card with Intel X550-AT2
`Controller); Wiwynn SV7220G2-P Server (using NM10GR card with Qlogic BCM57810 Controller); Wiwynn SV7220G2-P
`Server (using NM10GS card with Intel X550-AT2 Controller); Wiwynn SV7220G2-S Server (using NM10GR card with Qlogic
`
`
`1 The infringement contentions provided herein are based on information obtained to date and may not be exhaustive. Alacritech's investigation of Wistron's infringement is ongoing. Alacritech reserves the right to
`supplement and/or amend these disclosures to identify additional Asserted Claims (P.R. 3-1(a)), to identify additional Accused Instrumentalities (P.R. 3-1(b)), and to further identify where each element of each
`Asserted Claim is found in each Accused Instrumentality (P.R. 3-1(c)), including on the basis of discovery obtained from Wistron and from third-parties during the course of this litigation.
`
`2 All infringement contentions set forth herein for any independent patent claims are hereby incorporated by reference into the infringement contentions alleged for any dependent patent claims that depend on such
`independent claims, as if fully set forth therein.
`
`3 The Accused Instrumentalities and associated exhibits discussed and/or cited for any claim herein are representative in all material respects of all other Accused Instrumentalities identified for that claim (e.g.,
`although various servers may have immaterial differences in their hardware, firmware, and/or software configuration, the cited references are believed to be illustrative of all such accused server models).
`
`4 Alacritech's inclusion of any claim preamble in this claim chart should not be interpreted as an admission that the preamble is limiting. Alacritech reserves the right to take the position that the claim preambles are
`limiting or not limiting on a claim-by-claim basis.
`
`
`RESTRICTED – ATTORNEYS' EYES ONLY
`
`1
`
`
`Alacritech, Inc. v. Wistron Corporation, et al.,
`(EDTX, Case No. 2:16-cv-00692-JRG)
`
`

`

`'948 Patent Claim2
`(P.R. 3-1(a))
`
`Accused Instrumentalities And Where Each Claim Element Is Found3
`(P.R. 3-1(b)-(c))
`
`Alacritech, Inc.’s Initial Patent Disclosures For Wistron
`Exhibit 7
`
`BCM57810 Controller); Wiwynn SV7220G2-S Server (using NM10GS card with Intel X550-AT2 Controller); Wiwynn
`SV7220G2-V Server (using NM10GR card with Qlogic BCM57810 Controller); Wiwynn SV7220G2-V Server (using NM10GS
`card with Intel X550-AT2 Controller));
`
`(ii) any version of its server or computer products, including but not limited to those identified above, combined with any version
`of its card or adapter products capable of providing, or configured to provide, infringing RSC functionality in combination with
`such server or computer products (e.g., Wiwynn NM10GR Network Card with Qlogic BCM57810 Controller; Wiwynn NM10GS
`Network Card with Intel X550-AT2 Controller); and
`
`(iii) any of its other activities, products and/or services that use server or computer products to practice and/or support
`infringing RSC functionality.
`
`Wistron has committed and continues to commit acts of infringement of claim 1 under 35 U.S.C. § 271 in connection with Wistron's
`Accused Instrumentalities.
`
`To the extent that the Court determines that the preamble of this claim is limiting, Wistron's Accused Instrumentalities perform the
`claimed method for network communication by a host computer having a network interface that is connected to the host by an
`input/output bus, in connection with infringing RSC functionality. See [948.1a]-[948.1g], infra.
`
`Each of the Wistron Accused Instrumentalities comprises a host computer (e.g., a server) that has at least one RSC-capable network
`controller, such as the Intel 82599 10 GbE Controller. See, e.g., "CA AppLogic and Wiwynn SV320 Equipment Validation," Bates
`ALA00011043-52, describing the network controller of a Wistron Accused Instrumentality.5
`
`
`5 See also Wiwynn SV320 Server with Intel 82599 Controller (ALA00011043-ALA00011052, ALA00002071-ALA00003136); Wiwynn SV100G2 Server (using NM10GR card
`with Qlogic BCM57810 Controller) (ALA00013557-ALA00013562, ALA00007589-ALA00007591); Wiwynn SV100G2 Server (using NM10GS card with Intel X550-AT2
`Controller) (ALA00013557-ALA00013562, ALA00011157-ALA00012272); Wiwynn SV300G2 Server (using NM10GR card with Qlogic BCM57810 Controller)
`(ALA00013577-ALA00013578, ALA00007589-ALA00007591); Wiwynn SV300G2 Server (using NM10GS card with Intel X550-AT2 Controller) (ALA00013577-
`ALA00013578, ALA00011157-ALA00012272); Wiwynn SV320G2 Server (using NM10GR card with Qlogic BCM57810 Controller) (ALA00013581-ALA00013582,
`ALA00007589-ALA00007591); Wiwynn SV320G2 Server (using NM10GS card with Intel X550-AT2 Controller) (ALA00013581-ALA00013582, ALA00011157-
`ALA00012272); Wiwynn SV324G2 Server (using NM10GR card with Qlogic BCM57810 Controller) (ALA00013557-ALA00013562, ALA00007589-ALA00007591); Wiwynn
`
`
`RESTRICTED – ATTORNEYS' EYES ONLY
`
`2
`
`
`Alacritech, Inc. v. Wistron Corporation, et al.,
`(EDTX, Case No. 2:16-cv-00692-JRG)
`
`

`

`'948 Patent Claim2
`(P.R. 3-1(a))
`
`
`
`Alacritech, Inc.’s Initial Patent Disclosures For Wistron
`Exhibit 7
`
`Accused Instrumentalities And Where Each Claim Element Is Found3
`(P.R. 3-1(b)-(c))
`
`
`SV324G2 Server (using NM10GS card with Intel X550-AT2 Controller) (ALA00013557-ALA00013562, ALA00011157-ALA00012272); Wiwynn SV5270G2-R Server (using
`NM10GR card with Qlogic BCM57810 Controller) (ALA00013583-ALA00013584, ALA00007589-ALA00007591, ALA00009725-ALA00009726); Wiwynn SV5270G2-R
`Server (using NM10GS card with Intel X550-AT2 Controller) (ALA00013583-ALA00013584, ALA00011157-ALA00012272, ALA00009725-ALA00009726); Wiwynn
`SV5270G2-S Server (using NM10GR card with Qlogic BCM57810 Controller) (ALA00013583-ALA00013584, ALA00007589-ALA00007591, ALA00009725-ALA00009726);
`Wiwynn SV5270G2-S Server (using NM10GS card with Intel X550-AT2 Controller) (ALA00013583-ALA00013584, ALA00011157-ALA00012272, ALA00009725-
`ALA00009726); Wiwynn SV7110 Server (using NM10GR card with Qlogic BCM57810 Controller) (ALA00013585-ALA00013586, ALA00007589-ALA00007591); Wiwynn
`SV7110 Server (using NM10GS card with Intel X550-AT2 Controller) (ALA00013585-ALA00013586, ALA00011157-ALA00012272); Wiwynn SV7220G2-N Server (using
`NM10GR card with Qlogic BCM57810 Controller) (ALA00013589-ALA00013590, ALA00007589-ALA00007591); Wiwynn SV7220G2-N Server (using NM10GS card with
`Intel X550-AT2 Controller) (ALA00013589-ALA00013590, ALA00011157-ALA00012272); Wiwynn SV7220G2-P Server (using NM10GR card with Qlogic BCM57810
`Controller) (ALA00013589-ALA00013590, ALA00007589-ALA00007591); Wiwynn SV7220G2-P Server (using NM10GS card with Intel X550-AT2 Controller)
`(ALA00013589-ALA00013590, ALA00011157-ALA00012272); Wiwynn SV7220G2-S Server (using NM10GR card with Qlogic BCM57810 Controller) (ALA00013589-
`ALA00013590, ALA00007589-ALA00007591); Wiwynn SV7220G2-S Server (using NM10GS card with Intel X550-AT2 Controller) (ALA00013589-ALA00013590,
`ALA00011157-ALA00012272); Wiwynn SV7220G2-V Server (using NM10GR card with Qlogic BCM57810 Controller) (ALA00013589-ALA00013590, ALA00007589-
`ALA00007591); Wiwynn SV7220G2-V Server (using NM10GS card with Intel X550-AT2 Controller) (ALA00013589-ALA00013590, ALA00011157-ALA00012272); Wiwynn
`NM10GR Network Card with Qlogic BCM57810 Controller (ALA00013557-ALA00013562, ALA00007589-ALA00007591); Wiwynn NM10GS Network Card with Intel X550-
`AT2 Controller (ALA00013557-ALA00013562, ALA00011157-ALA00012272).
`
`
`RESTRICTED – ATTORNEYS' EYES ONLY
`
`3
`
`
`Alacritech, Inc. v. Wistron Corporation, et al.,
`(EDTX, Case No. 2:16-cv-00692-JRG)
`
`

`

`'948 Patent Claim2
`(P.R. 3-1(a))
`
`Accused Instrumentalities And Where Each Claim Element Is Found3
`(P.R. 3-1(b)-(c))
`
`Alacritech, Inc.’s Initial Patent Disclosures For Wistron
`Exhibit 7
`
`
`The RSC-capable network controller of each of the Wistron Accused Instrumentalities is connected to the host computer by an
`input/output bus (e.g., a PCIe Bus) that enables network communication in connection with infringing RSC functionality. See, e.g., the
`Intel 82599 10 GbE Controller Datasheet, Revision 3.3 (March 2016), BATES ALA00002071-3136 ("82599 Datasheet"), at Sections
`1.2.3, 1.2.4, describing PCIe Bus for interfacing with a host computer.6
`
`
`
`
`6 See also Intel X550 Controller (ALA00011157-ALA00012272) at Section 1.3, Section 1.3.1; Q-Logic 57840S-k quad port 10GbE blade KR NDC (ALA00007598-
`ALA00007600); Q-Logic 57840S quad port 10G SFP+ rack NDC (ALA00007601-ALA00007603); Q-Logic 57810S dual-port 10GbE SFP+ converged network adapter
`(ALA00007592-ALA00007594); Q-Logic 57810S dual-port 10GbE KR blade converged mezzanine card (ALA00007586-ALA00007588); Q-Logic 57810S dual-port 10GbE
`blade converged NDC (ALA00007589-ALA00007591); Q-Logic 57810S Dual-port 10GbE BASE-T converged network adapter (ALA00007595-ALA00007597); Q-Logic
`
`
`RESTRICTED – ATTORNEYS' EYES ONLY
`
`4
`
`
`Alacritech, Inc. v. Wistron Corporation, et al.,
`(EDTX, Case No. 2:16-cv-00692-JRG)
`
`

`

`'948 Patent Claim2
`(P.R. 3-1(a))
`
`
`
`Alacritech, Inc.’s Initial Patent Disclosures For Wistron
`Exhibit 7
`
`Accused Instrumentalities And Where Each Claim Element Is Found3
`(P.R. 3-1(b)-(c))
`
`
`1.2.3 External Interfaces
`
`
`
`
`
`57800S quad-port SFP+/ BASE-T (2x10GbE + 2x1GbE) rack converged NDC (ALA00007583-ALA00007585); Q-Logic 57800S quad-port BASE-T (2x10GbE + 2x1GbE) rack
`converged NDC (ALA00007580-ALA00007582); Q-Logic Quark dual-port 10Gb SFP+ and Base-T adapter Controller (ALA00007595-ALA00007597).
`
`
`RESTRICTED – ATTORNEYS' EYES ONLY
`
`5
`
`
`Alacritech, Inc. v. Wistron Corporation, et al.,
`(EDTX, Case No. 2:16-cv-00692-JRG)
`
`

`

`'948 Patent Claim2
`(P.R. 3-1(a))
`
`Accused Instrumentalities And Where Each Claim Element Is Found3
`(P.R. 3-1(b)-(c))
`
`Alacritech, Inc.’s Initial Patent Disclosures For Wistron
`Exhibit 7
`
`
`1.2.4 PCI-Express* (PCIe*) Interface
`The 82599 supports PCIe V2.0 (2.5GT/s or 5GT/s). See Section 2.1.2 for full pin
`description and Section 11.4.3 for interface timing characteristics.
`
`
`
`
`[948.1a] running, on the host computer,
`a protocol processing stack including an
`Internet Protocol (IP) layer and a
`Transmission Control Protocol (TCP)
`
`The Wistron Accused Instrumentalities are capable of running, on the host computer, a protocol processing stack including an Internet
`Protocol (IP) layer and a Transmission Control Protocol (TCP) layer, with an application layer running above the TCP layer.
`
`The host computer of each of the Wistron Accused Instrumentalities runs a protocol processing stack (e.g., the TCP/IP stack of the host
`
`
`RESTRICTED – ATTORNEYS' EYES ONLY
`
`6
`
`
`Alacritech, Inc. v. Wistron Corporation, et al.,
`(EDTX, Case No. 2:16-cv-00692-JRG)
`
`

`

`'948 Patent Claim2
`(P.R. 3-1(a))
`
`layer, with an application layer running
`above the TCP layer;
`
`Alacritech, Inc.’s Initial Patent Disclosures For Wistron
`Exhibit 7
`
`Accused Instrumentalities And Where Each Claim Element Is Found3
`(P.R. 3-1(b)-(c))
`
`operating system) that includes an IP layer and a TCP layer, with an application layer running above the TCP layer. See, e.g., Next
`Generation TCP/IP Stack in Windows Vista and Windows Server 2008, BATES ALA00009427-29 ("Microsoft Stack"), depicting a
`Windows TCP/IP stack with an IP and TCP layer, and an application layer running above the TCP layer.
`
`
`Architecture of the Next Generation TCP/IP Stack
`
`The following figure shows the architecture of the Next Generation TCP/IP stack.
`
`
`See also, e.g., Sections 1.4.4.1, 7.11, 82599 Datasheet, BATES ALA00002071-3136, describing interaction between the network
`
`
`
`
`RESTRICTED – ATTORNEYS' EYES ONLY
`
`7
`
`
`Alacritech, Inc. v. Wistron Corporation, et al.,
`(EDTX, Case No. 2:16-cv-00692-JRG)
`
`

`

`'948 Patent Claim2
`(P.R. 3-1(a))
`
`Accused Instrumentalities And Where Each Claim Element Is Found3
`(P.R. 3-1(b)-(c))
`
`Alacritech, Inc.’s Initial Patent Disclosures For Wistron
`Exhibit 7
`
`controller and the host computer's protocol stack in connection with infringing RSC functionality.7
`
`1.4.4.1 Receive Side Coalescing (RSC)
`RSC coalesces incoming TCP/IP packets into larger receive segments. It is the inverse
`operation to TSO on the transmit side. It has the same motivation, reducing CPU
`utilization by executing the TCP/IP stack only once for a set of received Ethernet packets.
`
`The 82599 can handle up to 32 flows per port at any given time. See Section 7.11 for
`more details on RSC.
`
`7.11 Receive Side Coalescing (RSC)
`The 82599 can merge multiple received frames from the same TCP/IP connection
`(referred to as flow in this section) into a single structure. The 82599 does this by
`coalescing the incoming frames into a single or multiple buffers (descriptors) that share a
`single accumulated header. This feature is called RSC. Note that the term Large Receive
`is used to describe a packet construct generated by RSC.
`
`The 82599 digests received packets and categorizes them by their TCP/IP connections
`(flows). For each flow, hardware coalesces the packets as shown in Figure 7-41 and
`Figure 7-42 (the colored parameters are explained in the RSC context table and receive
`descriptor sections). The 82599 can handle up to 32 concurrent flows per LAN port at any
`given time. Each flow handled by RSC offload has an associated context. The 82599
`opens and closes the RSC contexts autonomously with no need for any software
`intervention. Software needs only to enable RSC in the selected receive queues.
`
`Figure 7-41 shows a top level flow diagram that is used for RSC functionality. The
`
`
`7 See also Intel X550 Controller (ALA00011157-ALA00012272) at Section 1.4 (Table 1-5), Section 7.10.
`
`
`RESTRICTED – ATTORNEYS' EYES ONLY
`
`8
`
`
`Alacritech, Inc. v. Wistron Corporation, et al.,
`(EDTX, Case No. 2:16-cv-00692-JRG)
`
`

`

`'948 Patent Claim2
`(P.R. 3-1(a))
`
`Accused Instrumentalities And Where Each Claim Element Is Found3
`(P.R. 3-1(b)-(c))
`
`Alacritech, Inc.’s Initial Patent Disclosures For Wistron
`Exhibit 7
`
`following sections provide a detailed explanation of this flow as well as the memory
`structures and device settings that support the RSC functionality.
`
`
`
`See also, e.g., Receive Segment Coalescing, BATES ALA00009425-26 ("Microsoft RSC"), describing RSC functionality, which is
`enabled by default in Windows Server.
`
`
`
`
`
`RSC is a stateless offload technology that helps reduce CPU utilization for network processing on the receive
`side by offloading tasks from the CPU to an RSC-capable network adapter. CPU saturation due to
`networking-related processing can limit server scalability. This problem in turn reduces the transaction rate,
`raw throughput, and efficiency. RSC enables an RSC-capable network interface card to do the following:
`
`
`• Parse multiple TCP/IP packets and strip the headers from the packets while preserving the payload of
`each packet.
`• Join the combined payloads of the multiple packets into one packet.
`• Send the single packet, which contains the payload of multiple packets, to the network stack for
`subsequent delivery to applications.
`
`
`The network interface card performs these tasks based on rules that are defined by the network stack
`subject to the hardware capabilities of the specific network adapter. This ability to receive multiple TCP
`segments as one large segment significantly reduces the per-packet processing overhead of the network
`stack. Because of this, RSC significantly improves the receive-side performance of the operating system (by
`reducing the CPU overhead) under network I/O intensive workloads.
`
`Here are some key facts about RSC:
`
`
`
`RESTRICTED – ATTORNEYS' EYES ONLY
`
`9
`
`
`Alacritech, Inc. v. Wistron Corporation, et al.,
`(EDTX, Case No. 2:16-cv-00692-JRG)
`
`

`

`'948 Patent Claim2
`(P.R. 3-1(a))
`
`Accused Instrumentalities And Where Each Claim Element Is Found3
`(P.R. 3-1(b)-(c))
`
`Alacritech, Inc.’s Initial Patent Disclosures For Wistron
`Exhibit 7
`
`[948.1b] initializing, by the host
`computer, a TCP connection that is
`defined by source and destination IP
`addresses and source and destination
`TCP ports;
`
`• RSC is enabled by default for clean installations of all editions of Windows Server 2012 on computers
`that have RSC-capable network adapters. You do not need to take any action to enable RSC when you
`have an RSC-capable network interface card installed in your physical computer or used by a virtual
`machine that is running Windows Server 2012. In addition, you can track RSC status and usage by
`using relevant Performance Monitor counters.
`
`
`
`The Wistron Accused Instrumentalities are capable of initializing, by the host computer, a TCP connection that is defined by source and
`destination IP addresses and source and destination TCP ports.
`
`The host computer of each of the Wistron Accused Instrumentalities initializes a TCP connection that is defined by source and
`destination IP addresses and source and destination TCP ports. For example, the TCP/IP stack of the host computer establishes the TCP
`connection defined by source and destination IP addresses and TCP ports, which are included in the IP and TCP headers of each packet
`sent or received pursuant to the connection. See, e.g., Microsoft Stack, BATES ALA00009427-29, depicting a Windows TCP/IP stack
`and associated architecture that initialize a TCP connection defined by source and destination IP addresses and TCP ports.
`
`
`Architecture of the Next Generation TCP/IP Stack
`
`The following figure shows the architecture of the Next Generation TCP/IP stack.
`
`
`RESTRICTED – ATTORNEYS' EYES ONLY
`
`10
`
`
`Alacritech, Inc. v. Wistron Corporation, et al.,
`(EDTX, Case No. 2:16-cv-00692-JRG)
`
`

`

`'948 Patent Claim2
`(P.R. 3-1(a))
`
`Accused Instrumentalities And Where Each Claim Element Is Found3
`(P.R. 3-1(b)-(c))
`
`Alacritech, Inc.’s Initial Patent Disclosures For Wistron
`Exhibit 7
`
`
`See also, e.g., Sections 7.11, 7.11.1, 7.11.2, A.1.2, 82599 Datasheet, BATES ALA00002071-3136, describing supported packet format
`containing IP and TCP headers with source and destination IP addresses and TCP ports, which are processed in connection with
`infringing RSC functionality.8
`
`7.11 Receive Side Coalescing (RSC)
`
`
`
`
`8 See also Intel X550 Controller (ALA00011157-ALA00012272) at Section 7.10, Section 7.10.1, Table 7-71, Section 7.10.2, Section A.1.2.
`
`
`RESTRICTED – ATTORNEYS' EYES ONLY
`
`11
`
`
`Alacritech, Inc. v. Wistron Corporation, et al.,
`(EDTX, Case No. 2:16-cv-00692-JRG)
`
`

`

`'948 Patent Claim2
`(P.R. 3-1(a))
`
`Accused Instrumentalities And Where Each Claim Element Is Found3
`(P.R. 3-1(b)-(c))
`
`Alacritech, Inc.’s Initial Patent Disclosures For Wistron
`Exhibit 7
`
`The 82599 can merge multiple received frames from the same TCP/IP connection
`(referred to as flow in this section) into a single structure. The 82599 does this by
`coalescing the incoming frames into a single or multiple buffers (descriptors) that share a
`single accumulated header. This feature is called RSC. Note that the term Large Receive
`is used to describe a packet construct generated by RSC.
`
`The 82599 digests received packets and categorizes them by their TCP/IP connections
`(flows). For each flow, hardware coalesces the packets as shown in Figure 7-41 and
`Figure 7-42 (the colored parameters are explained in the RSC context table and receive
`descriptor sections). The 82599 can handle up to 32 concurrent flows per LAN port at any
`given time. Each flow handled by RSC offload has an associated context. The 82599
`opens and closes the RSC contexts autonomously with no need for any software
`intervention. Software needs only to enable RSC in the selected receive queues.
`
`Figure 7-41 shows a top level flow diagram that is used for RSC functionality. The
`following sections provide a detailed explanation of this flow as well as the memory
`structures and device settings that support the RSC functionality.
`
`7.11.1 Packet Viability for RSC Functionality
`
`***
`
`The supported packet format is as follows:
`
`
`
`RESTRICTED – ATTORNEYS' EYES ONLY
`
`12
`
`
`Alacritech, Inc. v. Wistron Corporation, et al.,
`(EDTX, Case No. 2:16-cv-00692-JRG)
`
`

`

`'948 Patent Claim2
`(P.R. 3-1(a))
`
`Accused Instrumentalities And Where Each Claim Element Is Found3
`(P.R. 3-1(b)-(c))
`
`Alacritech, Inc.’s Initial Patent Disclosures For Wistron
`Exhibit 7
`
`
`7.11.2 Flow Identification and RSC Context Matching
`TCP/IP packet’s flow is identified by its four tuples: Source / Destination IP addresses and
`Source / Destination TCP port numbers. These tuples are compared against the Flow
`Identification fields stored in the active RSC contexts (listed in Table 7-79). Comparison
`
`
`
`
`RESTRICTED – ATTORNEYS' EYES ONLY
`
`13
`
`
`Alacritech, Inc. v. Wistron Corporation, et al.,
`(EDTX, Case No. 2:16-cv-00692-JRG)
`
`

`

`'948 Patent Claim2
`(P.R. 3-1(a))
`
`Accused Instrumentalities And Where Each Claim Element Is Found3
`(P.R. 3-1(b)-(c))
`
`Alacritech, Inc.’s Initial Patent Disclosures For Wistron
`Exhibit 7
`
`is done in two phases:
`
`
`• Hash Compare — Hardware computes a hash value of the four tuples for each flow.
`The hash value is stored in the RSC context table. It is used for silicon optimization of
`the compare logic. The hash value of the incoming packet is compared against the
`hash values of all RSC contexts. No match between the two hash values means that
`there is no valid context of the same flow.
`• Perfect Match — Hardware checks the four tuples of the RSC context that passed the
`first step with the received frame.
`— A match between the two means that an active RSC context is found.
`— Mismatch between the two indicates a hash collision, which causes a completion
`of the collided RSC.
`• In any case of context mismatch, a new context might be opened as described in
`Section 7.11.3.
`• If the packet’s flow matches an active RSC context then the packet might be
`appended to the existing RSC as described in Section 7.11.4.
`
`
`A.1.2 IP and TCP/UDP Headers for TSO
`
`***
`
`
`
`RESTRICTED – ATTORNEYS' EYES ONLY
`
`14
`
`
`Alacritech, Inc. v. Wistron Corporation, et al.,
`(EDTX, Case No. 2:16-cv-00692-JRG)
`
`

`

`'948 Patent Claim2
`(P.R. 3-1(a))
`
`Accused Instrumentalities And Where Each Claim Element Is Found3
`(P.R. 3-1(b)-(c))
`
`Alacritech, Inc.’s Initial Patent Disclosures For Wistron
`Exhibit 7
`
`
`***
`
`
`
`
`
`
`
`
`
`RESTRICTED – ATTORNEYS' EYES ONLY
`
`15
`
`
`Alacritech, Inc. v. Wistron Corporation, et al.,
`(EDTX, Case No. 2:16-cv-00692-JRG)
`
`

`

`'948 Patent Claim2
`(P.R. 3-1(a))
`
`Accused Instrumentalities And Where Each Claim Element Is Found3
`(P.R. 3-1(b)-(c))
`
`Alacritech, Inc.’s Initial Patent Disclosures For Wistron
`Exhibit 7
`
`[948.1c] receiving, by the network
`interface, first and second packets,
`wherein the first packet has a first TCP
`header and contains first payload data
`for the application, and the second
`packet has a second TCP header and
`contains second payload data for the
`application;
`
`
`Each of the Wistron Accused Instrumentalities that includes a non-Intel network controller also supports RSC functionality.9 On
`information and belief, each of the non-Intel controllers performs infringing RSC functionality in substantially the same manner as the
`Intel controllers, including with respect to supporting packets containing IP and TCP headers with source and destination IP addresses
`and TCP ports, which are processed in connection with the RSC functionality.
`
`
`The Wistron Accused Instrumentalities are capable of receiving, by the network interface, first and second packets, wherein the first
`packet has a first TCP header and contains first payload data for the application, and the second packet has a second TCP header and
`contains second payload data for the application.
`
`In connection with infringing RSC functionality, the network controller of each of the Wistron Accused Instrumentalities receives first
`and second packets pursuant to the same TCP connection. The first and second packets each contain a TCP header (a first and a second
`TCP header, respectively) and payload data (first and second payload data, respectively) for the application corresponding to the TCP
`connection. See, e.g., Sections 7.1, 7.11, 7.11.1, 82599 Datasheet, BATES ALA00002071-3136, describing receiving packets each
`containing a TCP header and payload data for an application in connection with infringing RSC functionality.10
`
`7.1 Receive Functionality
`Packet reception consists of:
`
`
`• Recognizing the presence of a packet on the wire
`
`
`9 See Q-Logic 57840S-k quad port 10GbE blade KR NDC (ALA00007598-ALA00007600); Q-Logic 57840S quad port 10G SFP+ rack NDC (ALA00007601-ALA00007603);
`Q-Logic 57810S dual-port 10GbE SFP+ converged network adapter (ALA00007592-ALA00007594); Q-Logic 57810S dual-port 10GbE KR blade converged mezzanine card
`(ALA00007586-ALA00007588); Q-Logic 57810S dual-port 10GbE blade converged NDC (ALA00007589-ALA00007591); Q-Logic 57810S Dual-port 10GbE BASE-T
`converged network adapter (ALA00007595-ALA00007597); Q-Logic 57800S quad-port SFP+/ BASE-T (2x10GbE + 2x1GbE) rack converged NDC (ALA00007583-
`ALA00007585); Q-Logic 57800S quad-port BASE-T (2x10GbE + 2x1GbE) rack converged NDC (ALA00007580-ALA00007582); Q-Logic Quark dual-port 10Gb SFP+ and
`Base-T adapter Controller (ALA00007595-ALA00007597).
`
`10 See also Intel X550 Controller (ALA00011157-ALA00012272) at Section 7.1, Section 7.10, Section 7.10.1, Table 7-71.
`
`
`
`RESTRICTED – ATTORNEYS' EYES ONLY
`
`16
`
`
`Alacritech, Inc. v. Wistron Corporation, et al.,
`(EDTX, Case No. 2:16-cv-00692-JRG)
`
`

`

`'948 Patent Claim2
`(P.R. 3-1(a))
`
`Accused Instrumentalities And Where Each Claim Element Is Found3
`(P.R. 3-1(b)-(c))
`
`Alacritech, Inc.’s Initial Patent Disclosures For Wistron
`Exhibit 7
`
`• Performing address filtering
`• DMA queue assignment
`• Storing the packet in the receive data FIFO
`• Transferring the data to assigned receive queues in host memory
`• Updating the state of a receive descriptor.
`
`
`7.11 Receive Side Coalescing (RSC)
`The 82599 can merge multiple received frames from the same TCP/IP connection
`(referred to as flow in this section) into a single structure. The 82599 does this by
`coalescing the incoming frames into a single or multiple buffers (descriptors) that share a
`single accumulated header. This feature is called RSC. Note that the term Large Receive
`is used to describe a packet construct generated by RSC.
`
`The 82599 digests received packets and categorizes them by their TCP/IP connections
`(flows). For each flow, hardware coalesces the packets as shown in Figure 7-41 and
`Figure 7-42 (the colored parameters are explained in the RSC context table and receive
`descriptor sections). The 82599 can handle up to 32 concurrent flows per LAN port at any
`given time. Each flow handled by RSC offload has an associated context. The 82599
`opens and closes the RSC contexts autonomously with no need for any software
`intervention. Software needs only to enable RSC in the selected receive queues.
`
`Figure 7-41 shows a top level flow diagram that is used for RSC functionality. The
`following sections provide a detailed explanation of this flow as well as the memory
`structures and device settings that support the RSC functionality.
`
`7.11.1 Packet Viability for RSC Functionality
`
`***
`
`
`
`RESTRICTED – ATTORNEYS' EYES ONLY
`
`17
`
`
`Alacritech, Inc. v. Wistron Corporation, et al.,
`(EDTX, Case No. 2:16-cv-00692-JRG)
`
`

`

`Alacritech, Inc.’s Initial Patent Disclosures For Wistron
`Exhibit 7
`
`'948 Patent Claim2
`(P.R. 3-1(a))
`
`Accused Instrumentalities And Where Each Claim Element Is Found3
`(P.R. 3-1(b)-(c))
`
`The supported packet format is as follows:
`
`
`
`Each of the Wistron Accused Instrumentalities that includes a non-Intel network controller also supports RSC functionality.11 On
`
`
`
`
`11 See Q-Logic 57840S-k quad port 10GbE blade KR NDC (ALA00007598-ALA00007600); Q-Logic 57840S quad port 10G SFP+ rack NDC (ALA00007601-ALA00007603);
`Q-Logic 57810S dual-port 10GbE SFP+ converged network adapter (ALA00007592-ALA00007594); Q-Logic 57810S dual-port 10GbE KR blade converged mezzanine card
`
`
`RESTRICTED – ATTORNEYS' EYES ONLY
`
`18
`
`
`Alacritech, Inc. v. Wistron Corporation, et al.,
`(EDTX, Case No. 2:16-cv-00692-JRG)
`
`

`

`'948 Patent Claim2
`(P.R. 3-1(a))
`
`Accused Instrumentalities And Where Each Claim Element Is Found3
`(P.R. 3-1(b)-(c))
`
`Alacritech, Inc.’s Initial Patent Disclosures For Wistron
`Exhibit 7
`
`[948.1d] checking, by the network
`interface, whether the packets have
`certain exception conditions, including
`checking whether the packets are IP
`fragmented, checking whether the
`packets have a FIN flag set, and
`checking whether the packets are out of
`order;
`
`information and belief, each of the non-Intel controllers of the Wistron Accused Instrumentalities performs infringing RSC functionality
`in substantially the same manner as the Intel controllers, including with respect to receiving packets containing a TCP header and
`payload data for an application.
`
`
`The Wistron Accused Instrumentalities are capable of checking, by the network interface, whether the packets have certain exception
`conditions, including checking whether the packets are IP fragmented, checking whether the packets have a FIN flag set, and checking
`whether the packets are out of order.
`
`In connection with infringing RSC functionality, the network controller in each of the Wistron Accused Instrumentalities checks whether
`the packets have certain exception conditions, including whether the packets are IP fragmented, have a FIN flag set, or are out of order
`(e.g., have an unexpected TCP sequence number). For example, the network controller checks each packet for these exception conditions
`when determining whether the packet can be RSC coalesced with an active RSC flow. See, e.g., Sections 7.11, 7.11.1, 7.11.4, 82599
`Datasheet,