UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`
`INTEL CORP. and CAVIUM, INC.,
`Petitioner,
`
`v.
`
`ALACRITECH, INC.,
`Patent Owner.
`______________________
`
`Case IPR2018-002341
`U.S. Patent No. 8,805,948
`Title: INTELLIGENT NETWORK INTERFACE SYSTEM AND METHOD
`FOR PROTOCOL PROCESSING
`______________________
`
`DECLARATION OF ROBERT HORST, PH.D.,
`IN SUPPORT OF PETITIONER’S REPLY TO PATENT OWNER’S
`RESPONSE TO PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 8,805,948
`
`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`1 Cavium, Inc., which filed a Petition in Case IPR2018-00403, has been joined as a
`
`petitioner in this proceeding.
`
`INTEL EX. 1399.001
`
`
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`
`INTEL CORP. and CAVIUM, INC.,
`Petitioner,
`
`v.
`
`ALACRITECH, INC.,
`Patent Owner.
`______________________
`
`Case IPR2018-002341
`U.S. Patent No. 8,805,948
`Title: INTELLIGENT NETWORK INTERFACE SYSTEM AND METHOD
`FOR PROTOCOL PROCESSING
`______________________
`
`DECLARATION OF ROBERT HORST, PH.D.,
`IN SUPPORT OF PETITIONER’S REPLY TO PATENT OWNER’S
`RESPONSE TO PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 8,805,948
`
`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`1 Cavium, Inc., which filed a Petition in Case IPR2018-00403, has been joined as a
`
`petitioner in this proceeding.
`
`INTEL EX. 1399.001
`
`
`
`U.S. Patent No. 8,805,948
`Ex. 1399 (“Horst Reply Decl.”)
`
`TABLE OF CONTENTS
`
`Page
`
`I.
`
`INTRODUCTION .......................................................................................... 1
`
`II. MATERIALS RELIED UPON IN FORMING MY OPINION ................ 3
`
`III. UNDERSTANDING OF THE GOVERNING LAW ................................. 4
`
`A.
`
`B.
`
`Invalidity by Anticipation ................................................................... 4
`
`Invalidity by Obviousness ................................................................... 5
`
`IV. LEVEL OF ORDINARY SKILL IN THE ART ......................................... 7
`
`V. ANALYSIS AND OPINIONS ...................................................................... 7
`
`A. A POSA Would Know How to Implement Thia’s Teachings ......... 9
`
`B.
`
`C.
`
`D.
`
`Tanenbaum96 ..................................................................................... 14
`
`Checking Packets Is Not Limited to Checking the IP Network
`Layer Header ...................................................................................... 15
`
`The Prior Art Combination Discloses Storing Data Portions
`Together on the Host Without TCP Headers ................................... 18
`
`E. Motivations to Combine Thia, Tanenbaum96, and Stevens2 ........ 25
`
`
`
`
`i
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`INTEL EX. 1399.002
`
`
`
`U.S. Patent No. 8,805,948
`Ex. 1399 (“Horst Reply Decl.”)
`
`I, Robert Horst, hereby declare as follows:
`
`I.
`
`INTRODUCTION
`1. My name is Robert Horst. I have been retained on behalf of Petitioner
`
`Intel Corporation (“Intel”) to provide this Declaration concerning technical subject
`
`matter relevant to the petition for inter partes review (“Petition”) concerning U.S.
`
`Patent No. 8,805,948 (Ex. 1001, the “948 Patent”). I reserve the right to supplement
`
`this Declaration in response to additional evidence that may come to light.
`
`2.
`
`I am over 18 years of age. I have personal knowledge of the facts stated
`
`in this Declaration and could testify competently to them if asked to do so.
`
`3.
`
`I am being compensated for my time at the rate of $550 per hour. My
`
`compensation is not based on the resolution of this matter. My findings are based
`
`on my education, experience, and background in the fields discussed below.
`
`4.
`
`I am an independent consultant with more than 30 years of expertise in
`
`the design and architecture of computer systems. My latest curriculum vitae is
`
`submitted as (Ex. 1004), and some highlights follow.
`
`5.
`
`Currently, I am an independent consultant at HT Consulting where my
`
`work includes consulting on technology and intellectual property. I also have an
`
`appointment as an adjunct research professor at the University of Illinois in the
`
`Department of Electrical and Computer Engineering. I have testified as an expert
`
`1
`
`INTEL EX. 1399.003
`
`
`
`U.S. Patent No. 8,805,948
`Ex. 1399 (“Horst Reply Decl.”)
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`witness and consultant in patent and intellectual property litigation as well as inter
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`partes reviews and re-examination proceedings.
`
`6.
`
`I earned my M.S. (1978) in electrical engineering and Ph.D. (1991) in
`
`computer science from the University of Illinois at Urbana-Champaign after earning
`
`my B.S. (1975) in electrical engineering from Bradley University. During my
`
`master’s program, I designed, constructed and debugged a shared memory parallel
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`microprocessor system. During my doctoral program, I designed and simulated a
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`massively parallel, multi-threaded task flow computer.
`
`7.
`
`After receiving my bachelor’s degree and while pursuing my master’s
`
`degree, I worked for Hewlett-Packard Co. While at Hewlett-Packard, I designed the
`
`micro-sequencer and cache of the HP3000 Series 64 processor. From 1980 to 1999,
`
`I worked at Tandem Computers, which was acquired by Compaq Computers in
`
`1997. While at Tandem, I was a designer and architect of several generations of
`
`fault-tolerant computer systems and was the principal architect of the NonStop
`
`Cyclone superscalar processor. The system development work at Tandem also
`
`included development of the ServerNet System Area Network and applications of
`
`this network to fault tolerant systems and clusters of database servers.
`
`8.
`
`Since leaving Compaq in 1999, I have worked with several technology
`
`companies, including 3Ware, Network Appliance, Tibion, and AlterG in the areas
`
`of network-attached storage and biomedical devices. From 2012 to 2015, I was Chief
`
`2
`
`INTEL EX. 1399.004
`
`
`
`U.S. Patent No. 8,805,948
`Ex. 1399 (“Horst Reply Decl.”)
`
`Technology Officer of Robotics at AlterG, Inc., where I worked on the design of
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`anti-gravity treadmills and battery-powered orthotic devices to assist those with
`
`impaired mobility.
`
`9.
`
`In 2001, I was elected an IEEE Fellow “for contributions to the
`
`architecture and design of fault tolerant systems and networks.” I have authored over
`
`30 publications, have worked with patent attorneys on numerous patent applications,
`
`and I am a named inventor on 82 issued U.S. patents.
`
`10. My patents include those directed to networks (e.g., U.S. Pat. No.
`
`6,157,967: Method of data communication flow control in a data processing system
`
`using busy/ready commands), storage (e.g., U.S. Pat. No. 6,549,977: Use of deferred
`
`write completion interrupts to increase the performance of disk operations), and
`
`multi-processor systems (e.g., U.S. Pat. No. 5,751,932: Fail-fast, fail-functional,
`
`fault-tolerant multiprocessor system). My publications include a conference paper
`
`that examined the performance and efficacy of protocol offload engines. Ex. 1004.
`
`11. My Curriculum Vitae, which is filed as a separate Exhibit (Ex. 1004),
`
`contains further details on my education, experience, publications, and other
`
`qualifications to render this opinion as expert.
`
`II. MATERIALS RELIED UPON IN FORMING MY OPINION
`12.
`In addition to reviewing U.S. Patent No. 8,805,948 (Ex. 1001), I also
`
`reviewed and considered the prosecution history of the 948 Patent (Ex. 1002). I also
`
`3
`
`INTEL EX. 1399.005
`
`
`
`U.S. Patent No. 8,805,948
`Ex. 1399 (“Horst Reply Decl.”)
`
`reviewed Thia, A Reduced Operation Protocol Enginer (ROPE) for a multiple-layer
`
`bypass architecture (“Thia”) (Ex. 1015), A. Tanenbaum, 3rd ed. (1996) (Ex. 1006),
`
`and Stevens, TCP/IP Illustrated, Vol.2 (“Stevens2”) (Ex. 1013). I also considered
`
`the background materials cited in my original declaration, Ex. 1003.
`
`13.
`
`I also reviewed the Institution Decision, Patent Owner’s Preliminary
`
`Response (and exhibits provided therewith), and Patent Owner’s Response (and
`
`exhibits provided therewith, including Dr. Almeroth’s declaration). In addition, I
`
`have reviewed paragraphs 6-13 (Thia overview), 14-15 (Tanenbaum overview), 22-
`
`31 (re-assembly), 32-41 (motivation to combine) of Dr. Bill Lin’s reply declaration
`
`in IPR2017-01410 (Ex. 1223), as further discussed below.
`
`14.
`
`I have also considered the additional background materials cited herein.
`
`III. UNDERSTANDING OF THE GOVERNING LAW
`15.
`I understand that a patent claim is invalid if it is anticipated or rendered
`
`obvious in view of the prior art. I further understand that invalidity of a patent claim
`
`requires that the claim be anticipated or obvious from the perspective of a person of
`
`ordinary skill in the relevant art at the time the invention was made.
`
`A.
`16.
`
`Invalidity by Anticipation
`I have been informed that a patent claim is invalid as anticipated under
`
`35 U.S.C. § 102 if each and every element of a claim, as properly construed, is found
`
`either explicitly or inherently in a single prior art reference.
`
`4
`
`INTEL EX. 1399.006
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`
`
`U.S. Patent No. 8,805,948
`Ex. 1399 (“Horst Reply Decl.”)
`
`17.
`
`I have been informed that a claim is invalid under 35 U.S.C. § 102(a) if
`
`the claimed invention was patented or published anywhere, before the applicant's
`
`invention. I further have been informed that a claim is invalid under 35 U.S.C. §
`
`102(b) if the invention was patented or published anywhere more than one year prior
`
`to the first effective filing date of the patent application (critical date). I further have
`
`been informed that a claim is invalid under 35 U.S.C. § 102(e) if an invention
`
`described by that claim was disclosed in a U.S. patent granted on an application for
`
`a patent by another that was filed in the U.S. before the date of invention for such a
`
`claim.
`
`B.
`18.
`
`Invalidity by Obviousness
`I have been informed that a patent claim is invalid as obvious under 35
`
`U.S.C. § 103 if it would have been obvious to a person of ordinary skill in the art,
`
`taking into account (1) the scope and content of the prior art, (2) the differences
`
`between the prior art and the claims, (3) the level of ordinary skill in the art, and (4)
`
`any so called “secondary considerations” of non-obviousness, which include: (i)
`
`“long felt need” for the claimed invention, (ii) commercial success attributable to
`
`the claimed invention, (iii) unexpected results of the claimed invention, and (iv)
`
`“copying” of the claimed invention by others. I further understand that it is improper
`
`to rely on hindsight in making the obviousness determination. I have been informed
`
`that Patent Owner claims a filing priority date no later than October 14, 1997 for
`
`5
`
`INTEL EX. 1399.007
`
`
`
`U.S. Patent No. 8,805,948
`Ex. 1399 (“Horst Reply Decl.”)
`
`claims 1-7 of the 036 Patent. Accordingly my analysis of the prior art for the claims
`
`of the 036 Patent is based on the prior art and knowledge of a person having ordinary
`
`skill in the art (“POSA”) as of October 14, 1997.
`
`19.
`
`I have been informed that a claim can be obvious in light of a single
`
`prior art reference or multiple prior art references. I further understand that
`
`exemplary rationales that may support a conclusion of obviousness include:
`
`(A) Combining prior art elements according to known methods to yield
`predictable results;
`
`(B) Simple substitution of one known element for another to obtain
`predictable results;
`
`(C) Use of known technique to improve similar devices (methods, or
`products) in the same way;
`
`(D) Applying a known technique to a known device (method, or
`product) ready for improvement to yield predictable results;
`
`(E) “Obvious to try” - choosing from a finite number of identified,
`predictable solutions, with a reasonable expectation of success;
`
`(F) Known work in one field of endeavor may prompt variations of it
`for use in either the same field or a different one based on design
`incentives or other market forces if the variations are predictable to one
`of ordinary skill in the art;
`
`(G) Some teaching, suggestion, or motivation in the prior art that would
`have led one of ordinary skill to modify the prior art reference or to
`combine prior art reference teachings to arrive at the claimed invention.
`
`6
`
`INTEL EX. 1399.008
`
`
`
`U.S. Patent No. 8,805,948
`Ex. 1399 (“Horst Reply Decl.”)
`
`IV. LEVEL OF ORDINARY SKILL IN THE ART
`20. The definition of a POSA is set forth in my prior declaration. Ex. 1003,
`
`Horst Decl., ¶¶ 18-20. While it would be rare to find all of these skills in a single
`
`individual, it is my opinion that a POSA is a person with at least the equivalent of a
`
`B.S. degree in computer science, computer engineering or electrical engineering
`
`with at least five years of industry experience including experience in computer
`
`architecture, network design, network protocols, software development, and
`
`hardware development. Ex. 1003, Horst Decl., ¶ 19.
`
`21.
`
`I understand that Patent Owner contends that a POSA would be a
`
`person with a Bachelor’s degree in computer science, computer engineering, or the
`
`equivalent, and several years’ experience in the fields of computer networking
`
`and/or networking protocols. Paper No. 18 (“POR”) at 23. While I disagree with this
`
`proposed level of ordinary skill, my opinions in this declaration would remain the
`
`same even if Patent Owner’s opinion concerning the level of ordinary skill in the art
`
`were applied.
`
`22. The statements that I make in this declaration when I refer to a POSA
`
`are from the perspective of October 14, 1997.
`
`V. ANALYSIS AND OPINIONS
`23.
`I am aware that Inter Partes Reviews were instituted for U.S. Patent
`
`No. 8,131,880 (the “880 Patent”), which belongs to the same family as the 948 Patent
`
`7
`
`INTEL EX. 1399.009
`
`
`
`U.S. Patent No. 8,805,948
`Ex. 1399 (“Horst Reply Decl.”)
`
`and concerns substantially the same technology. I am also aware that the Patent Trial
`
`and Appeal Board issued Final Written Decisions finding that the challenged claims
`
`of the 880 Patent are invalid for being obvious over the combination of Thia and
`
`Tanenbaum96. I understand that Dr. Bill Lin provided declarations in the Inter
`
`Partes Reviews for the 880 Patent, including a declaration in support of Petitioner’s
`
`Reply in IPR2017-01410 (“1410 Lin Reply Decl.”). Counsel has directed me to
`
`review paragraphs 6-13 (Thia overview), 14-15 (Tanenbaum overview), 22-31 (re-
`
`assembly), 32-41 (motivation to combine) of the 1410 Lin Reply Decl. I have
`
`reviewed those paragraphs and agree with Dr. Lin’s opinions in those paragraphs as
`
`they relate to the teachings of Thia, Tanenabum96, and the motivation to combine
`
`these references.2 Based on my review of paragraphs 6-15 and 22-41 of the 1410 Lin
`
`Reply Decl., it appears that Dr. Lin’s opinions address the same arguments made by
`
`
`2 Note that I did not review any other paragraphs of the 1410 Lin Reply Decl., nor
`
`did I review any other declarations or submissions of Dr. Lin. I therefore do not have
`
`any opinions on any of the unreviewed paragraphs in the 1410 Lin Reply Decl., nor
`
`do I have any opinions of any other declarations or submissions of Dr. Lin. I also do
`
`not have any opinions relating to the meaning, scope, unpatentability, or alleged
`
`infringement of the 880 Patent. I also did not assist Dr. Lin with the 1410 Lin Reply
`
`Decl., and he did not assist me with my declaration here.
`
`8
`
`INTEL EX. 1399.010
`
`
`
`U.S. Patent No. 8,805,948
`Ex. 1399 (“Horst Reply Decl.”)
`
`Dr. Almeroth in this proceeding. I have therefore adopted and incorporated (with his
`
`permission3) language from these paragraphs into my declaration in paragraphs 26-
`
`29, 32, 39, 41, 43, 44, 48-50, and 52 below, adjusting only for slight differences in
`
`language, citations, and patent numbers.
`
`A. A POSA Would Know How to Implement Thia’s Teachings
`24.
`In my prior declaration, I provided my opinions on Thia and its
`
`disclosures. See Ex. 1003, Horst Decl.
`
`25.
`
`I disagree with many of Dr. Almeroth’s characterizations of Thia in his
`
`declaration. He opines that “one of ordinary skill would not have been able to
`
`construct a working device based on Thia’s disclosures.” Ex. 2026, Almeroth Decl.,
`
`¶ 85. I disagree.
`
`26. First, as explained in the 1410 Lin Reply Decl. (¶ 8), Thia is more than
`
`an allegedly “inoperative device” or theorized “potential processor architecture.”
`
`See POR at 12-13. Thia clearly states “[t]he VHSIC Hardware Description
`
`Language (VHDL) [6, 27] was used to model and synthesize the chip.” Ex. 1015,
`
`Thia at .006. To “synthesize the chip” means to compile the VHDL specification
`
`
`3 Counsel informed me that Dr. Lin has given me permission to use the same exact
`
`statements, paragraphs, and figures from the 1410 Lin Reply Decl. in this declaration
`
`and to modify those statements, paragraphs, and figures as I see fit.
`
`9
`
`INTEL EX. 1399.011
`
`
`
`U.S. Patent No. 8,805,948
`Ex. 1399 (“Horst Reply Decl.”)
`
`into an implementable design at the logic gate level. Thia also discloses that “[t]here
`
`were three stages, a behavioral model, a structural or RTL model, and a gate level
`
`design. These gave us two kinds of feasibility check, that the logic we specified will
`
`execute the protocol within the environment we envisage, and that the design is
`
`technically feasible, for instance in a reasonable chip area.” Ex. 1015, Thia at .008.
`
`This further confirms that the design was down to a “gate level design.” Thia further
`
`discloses that “[t]he structural model was then passed through the SYNOPSYS
`
`synthesis tool [31] for gate level generation with the 0.8 µm BiCMOS macro library
`
`from Texas Instruments [32].” Id. SYNOPSYS was and still is one of primary
`
`vendors of synthesis design tools used in the semiconductor industry to design
`
`semiconductor chips. A POSA would know that a gate-level design can be
`
`fabricated into a chip using well-known software tools and chip fabrication facilities.
`
`A POSA would have understood the teachings of Thia without the need for Thia to
`
`create a final chip.
`
`27. Second, as explained in the 1410 Lin Reply Decl. (¶ 9), a POSA would
`
`have in fact been able to understand and implement Thia’s teachings. As explained
`
`in my prior declaration, Thia describes offloading a bypass stack for a multi-layer
`
`protocol onto a network interface device. See, e.g., Ex. 1003, Horst Decl., ¶¶ 99-104.
`
`In the fourteen pages of its disclosure, Thia details this bypass offload sufficient for
`
`a POSA to implement Thia’s teachings into a working device. For example, Thia
`
`10
`
`INTEL EX. 1399.012
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`
`
`U.S. Patent No. 8,805,948
`Ex. 1399 (“Horst Reply Decl.”)
`
`explains that its bypass stack is a generalization of the well-known “Header
`
`Prediction” algorithm for TCP/IP. See Ex. 1015, Thia at .002 (“It is based on the
`
`‘protocol bypass concept’ [37] which is a generalization of Jacobson’s ‘Header
`
`Prediction’ algorithm [20] for TCP/IP.”); see also Ex. 1003, Horst Decl., ¶¶ 58-63
`
`(describing header prediction, including that it was incorporated into the publicly
`
`available BSD releases of the TCP/IP protocol). Thia explains that this bypass stack
`
`“performs all the relevant protocol processing in the data transfer phase,” such as
`
`when a connection is in an established state. Ex. 1015, Thia at .003. More
`
`specifically, Thia states that “[a] multiple-layer bypass path is a concatenation of
`
`processing procedures performed by the adjacent layers [of a standard protocol
`
`stack] when they are simultaneously in the data transfer phase.” Id. at .004
`
`(emphasis added). See also id. (“The finite state machine of the protocol is now
`
`reduced to only the ‘OPEN’ state, for as long as processing remains in the bypass
`
`path. The state of the system does not change during the entire data transfer phase
`
`and the protocol processing is reduced to ensuring reliable transfer of data across
`
`the communications network.”) (emphasis added). This concept, again, is the basis
`
`of the well-known header prediction algorithm for TCP/IP, on which Thia’s bypass
`
`stack is based, because header prediction is used to apply streamlined processing via
`
`a TCP fast-path for packets in the “established” state (i.e., the data transfer phase).
`
`See, e.g., Ex. 1006, Tanenbaum96 at .585 (explaining that the TCP fast-path
`
`11
`
`INTEL EX. 1399.013
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`
`
`U.S. Patent No. 8,805,948
`Ex. 1399 (“Horst Reply Decl.”)
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`“computes the checksum,” “updates the connection record and copies the data to the
`
`user,” and “an acknowledgement is sent back.”). As shown in Table 1, Thia further
`
`explains that the bypass processing includes computing the checksum, updating the
`
`connection record (required for “resequencing”) and acknowledgements, as well as
`
`other protocol processing that would be needed for other layers in the data transfer
`
`phase. Ex. 1015, Thia at .006. Thia also explains that the addition of the bypass stack
`
`only requires “minimal changes to the original software”—i.e., the standard protocol
`
`stack. See id. at .002; see also id. at .014 (“An existing implementation of the OSI
`
`stack can be adapted for bypassing with only a small modification of the original
`
`software, thus providing an easy migration path for current systems.”). These
`
`disclosures and others would have provided sufficient detail to enable a POSA to
`
`implement Thia’s teachings regarding a bypass stack.
`
`28. As explained in the 1410 Lin Reply Decl. (¶ 10), Thia also teaches
`
`procedures for segregating bypassable packets from non-bypassable packets. For
`
`example, Thia explains that “[t]he receive bypass test matches the incoming PDU
`
`headers with a template that identifies the predicted bypassable headers.” Ex. 1015,
`
`Thia at .003 (emphasis added). Because the bypass stack handles packets in the
`
`OPEN, or data transfer, state (see id. at .004), a POSA would know that the template
`
`would have the same connection identifiers for a given flow in the OPEN state. See
`
`also id. at .003 (“Shared data for access by the two tests …” and “The shared data
`
`12
`
`INTEL EX. 1399.014
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`
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`U.S. Patent No. 8,805,948
`Ex. 1399 (“Horst Reply Decl.”)
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`are used to maintain state consistency between the SPS and the bypass stack,
`
`including window flow control parameters and connection identifiers.”). A POSA
`
`would also have known that the predictable template must filter out packets that
`
`would require processing not handled by the bypass stack, which would be processed
`
`normally. Thus, Thia’s receive bypass test is like the well-known header prediction
`
`algorithm for TCP/IP, of which Thia’s bypass stack is a generalization. See Ex. 1006,
`
`Tanenbaum96 at .585 (“The TPDU is then checked to see if it is a normal one: the
`
`state is ESTABLISHED, neither side is trying to close the connection, the TPDU is a
`
`full one ….”). I therefore disagree with Dr. Almeroth’s statement that “Thia does
`
`not address or disclose how the bypass test is implemented,” as well as his opinion
`
`that a POSA would have been unable to implement Thia’s teachings in this regard.
`
`See Ex. 2026, Almeroth Decl., ¶ 90.
`
`29. As explained in the 1410 Lin Reply Decl. (¶ 11), it is important to keep
`
`in mind that, as explained in my prior declaration, a POSA would have had a
`
`bachelor’s degree in a relevant field and 5 years of experience, including experience
`
`in computer architecture, network design, network protocols, software development,
`
`and hardware development. See Ex. 1003, Horst Decl., ¶ 19. Even Dr. Almeroth
`
`agrees that a POSA would have “several years’ experience in the fields of computer
`
`networking and/or networking protocols.” Ex. 2026, Almeroth Decl., ¶ 33.
`
`Therefore, a reference need not explicitly disclose every detail in order for a POSA
`
`13
`
`INTEL EX. 1399.015
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`
`
`U.S. Patent No. 8,805,948
`Ex. 1399 (“Horst Reply Decl.”)
`
`to have known how to implement its teachings. Given the years of experience that a
`
`POSA would have had in networking protocols and computer networking, a POSA
`
`certainly would have understood Thia’s teachings and been able to implement them.
`
`Indeed, Thia provides sufficient details of the ROPE chip hardware, which Dr.
`
`Almeroth does not appear to dispute, and explains that its bypass stack only “requires
`
`minimal changes to the original software” of a multi-layer protocol. Ex. 1015, Thia
`
`at .002; see also id. at .004.
`
`30. Dr. Almeroth also opines that there is “no disclosure of reassembly of
`
`the PDUs being performed on the ROPE chip” in Thia and that Thia discloses
`
`reassembly only on the host. See Ex. 2026, Almeroth Decl., ¶ 93. I disagree for the
`
`reasons explained below in paragraphs 37-45.
`
`31. Dr. Almeroth also opines that Thia’s teachings are limited to the OSI
`
`protocol, that there is no suggestion to apply Thia’s teachings to TCP/IP, and that a
`
`POSA would not have understood Thia to be applicable to TCP/IP. Ex. 2026,
`
`Almeroth Decl., ¶¶ 94-97. I disagree with these statements for the reasons explained
`
`below in paragraphs 52-54.
`
`B. Tanenbaum96
`32.
`In his declaration, Dr. Almeroth seems to suggest that Tanenbaum96’s
`
`disclosure of header prediction only requires looking at the transport layer header of
`
`an incoming packet to determine whether the packet is a candidate for TCP fast-path
`
`14
`
`INTEL EX. 1399.016
`
`
`
`U.S. Patent No. 8,805,948
`Ex. 1399 (“Horst Reply Decl.”)
`
`processing. See Ex. 2026, Almeroth Decl., ¶ 101. But as noted by Dr. Lin in the 1410
`
`Lin Reply Decl. (¶ 14), Tanenbaum96 very clearly states that the IP header must
`
`also be examined in order to look up a connection. See Ex. 1006, Tanenbaum96 at
`
`.584-.585 (explaining that for TCP, the first step is looking up the connection record
`
`for an incoming packet, which includes using the two IP addresses from the IP
`
`header and the two ports from the TCP header as a key).
`
`33. Dr. Almeroth also opines that Tanenbaum96 “teaches away from
`
`performing any TCP/IP protocol processing on anything other than the host CPU.”
`
`Ex. 2026, Almeroth Decl., ¶102. He also states that “Tanenbaum identifies myriad
`
`difficulties with implementing TCP header bypass in a chip separate from the host
`
`CPU and advises against attempting such an implementation.” Id. I disagree with
`
`Dr. Almeroth. As I explain below in paragraphs 48-50, a POSA would not interpret
`
`Tanenbaum96’s disclosure in this way.
`
`C. Checking Packets Is Not Limited to Checking the IP Network
`Layer Header
`In its Response to the Petition, Patent Owner seems to argue that
`
`34.
`
`checking a “packet” according to the claims requires checking the IP layer header of
`
`a packet. POR at 31. I disagree. A POSA would understand that checking the
`
`characteristics of a packet is not limited to checking the characteristics of, or
`
`processing, the network layer header, and the claims do not require that the network
`
`layer be checked to examine the characteristics of a packet.
`15
`
`INTEL EX. 1399.017
`
`
`
`U.S. Patent No. 8,805,948
`Ex. 1399 (“Horst Reply Decl.”)
`
`35. Rather, a characteristic of a packet can be checked by examining a TCP
`
`header. As I explained in my prior declaration, the transport header and payload are
`
`encapsulated within the network header. Ex. 1003, Horst Decl., ¶¶ 29-30. Therefore,
`
`the TPDU, or segment, is nested within an IP packet as Tanenbaum96 illustrates
`
`(“Packet header” is the IP packet header and its payload includes the transport layer
`
`(“TPDU”) header and payload):
`
`Ex. 1006, Tanenbaum96 at .503 (red shading showing a “packet” portion of a frame,
`
`which also includes a TPDU portion).
`
`As illustrated below, packets include an IP and TCP header.
`
`
`
`16
`
`
`
`INTEL EX. 1399.018
`
`
`
`U.S. Patent No. 8,805,948
`Ex. 1399 (“Horst Reply Decl.”)
`
`Ex. 1006, Tanenbaum96 at .542.
`
`As I explained in my prior declaration (Ex. 1003, Horst Decl., ¶ 36), and as
`
`depicted below, the FIN flag is part of the TCP header.
`
`
`
`Ex. 1006, Tanenbaum96 at .544 (red shading added).
`
`Thus, “checking … whether … packets have a FIN flag set,” as required for example
`
`by claim 1, means checking the TCP header of TPDUs, not the IP header.
`
`36. Moreover, I note that the term “packet” as used by the 948 Patent does
`
`not necessarily mean an IP packet. A POSA would have understood that the term
`
`“packet” is often used to refer to protocol data units at different levels, including at
`
`17
`
`INTEL EX. 1399.019
`
`
`
`U.S. Patent No. 8,805,948
`Ex. 1399 (“Horst Reply Decl.”)
`
`the network layer or the transport layer. This is confirmed by the 948 Patent, which
`
`refers to a “TCP packet” instead of a TPDU or segment. Ex. 1001 at 10:57-61. Thus,
`
`in my opinion, a POSA would not have read the challenged claims are requiring
`
`checking whether IP packets have exception conditions, but rather checking whether
`
`packets (at any protocol level) have exception conditions.
`
`D. The Prior Art Combination Discloses Storing Data Portions
`Together on the Host Without TCP Headers
`37. Dr. Almeroth opines that the combination of Thia, Tanenbaum96, and
`
`Stevens2 does not disclose storing payload data together in a host buffer in order and
`
`without the TCP headers as required by claims 1 and 17. Ex. 2026, Almeroth Decl.,
`
`¶¶ 122-128. I disagree. Dr. Almeroth’s opinion is based on interpretations of the
`
`prior art that are inconsistent with Thia’s and Tanenbaum96’s explicit teachings.
`
`38. First, Dr. Almeroth’s incorrect opinion that Thia does not disclose
`
`transferring packet data from the ROPE chip to the host without TCP headers is
`
`based on his flawed belief that Thia discloses transferring an entire packet (i.e., with
`
`headers) from the ROPE chip to the host. See id., ¶ 124 (“If Thia intended to disclose
`
`copying just the data, and not the header, to the host, then it could have easily
`
`referred to the DMA procedure setting the starting address pointer to the Data Pointer
`
`(shown in Figure 4 of Thia), as opposed to the entire PDU.”) (emphasis added), ¶
`
`125 (“… the data portion of a PDU is copied between the host and NIA, just as the
`
`header portion is) (emphasis in original), id. (“Thia expressly states that the DMA
`18
`
`INTEL EX. 1399.020
`
`
`
`U.S. Patent No. 8,805,948
`Ex. 1399 (“Horst Reply Decl.”)
`
`procedure … copies the entire PDU, not just the payload.”), ¶ 127 (“… Thia
`
`expressly taught programming the DMA to copy the entire length of the PDU.”).
`
`This flawed belief appears to stem from misconstruing the following passage of
`
`Thia4:
`
`For subsequent bypassable packets, the host processor initiates the
`BYPASS_DMA procedure which checks for free buffer space in the
`bypass chip and programs the DMA by sending the starting address
`pointer where the PDU is located, and its total length. The destination
`address is supplied by the bypass chip. Arbitration for the host
`processor bus between the host and DMA is provided by the DMAreq
`and DMAack lines. DMA transfers the PDU into the internal dual-
`ported SRAM (Static RAM). Buffers are pre-allocated in fixed sizes
`and are accessed by a simple round robin scheme using a set of buffer
`pointers.
`
`Ex. 1015, Thia at .009 (emphasis added).
`
`39. As explained by Dr. Lin in the 1410 Lin Reply Decl. (¶ 30), this
`
`disclosure is actually describing that the host computer sends an entire packet (or
`
`
`4 While Dr. Almeroth cites page .009 of Thia for his incorrect opinion that Thia
`
`discloses transferring headers from the ROPE chip to the host, he does not clearly
`
`identify the language on this page that he relies upon. I reserve the right to respond
`
`to any clarification by Dr. Almeroth regarding the basis for his opinions.
`
`19
`
`INTEL EX. 1399.021
`
`
`
`U.S. Patent No. 8,805,948
`Ex. 1399 (“Horst Reply Decl.”)
`
`PDU) to the internal dual ported memory of the ROPE chip for transmission on a
`
`network. It does not describe receiving a packet from the network and transferring
`
`data from the ROPE chip to the host. Specifically, it states that “the host” is what
`
`“initiates the BYPASS_DMA procedure” and “programs the DMA by sending the
`
`starting address pointer where the PDU is located …” In other words, the host sends
`
`the location of where the PDU is located on the host. “The destination address” for
`
`where to send the PDU from the host is “supplied by the bypass chip,” and then
`
`“DMA transfers the PDU into the internal dual-ported SRAM” of the ROPE chip.
`
`See Ex. 1015, Thia at .009; see also id. at .007, Fig. 2 (illustrating the ROPE chip’s
`
`“Internal Dual Ported Memory”). Thus, a major premise of Dr. Almeroth’s analysis
`
`in paragraphs 122 through 128 is false.
`
`40. Second, Dr. Almeroth bases his analysis on a disclosure from Thia
`
`discussing lower-layer (e.g., network layer) segmentation/fragmentation and
`
`reassembly. See Ex. 2026, Almeroth Decl., ¶ 125 (“… Thia also expressly states that
`
`packet reassembly is not performed in the bypass path, which means the headers
`
`would not be discarded by the ROPE chip.”). The statement from Thia that Dr.
`
`Almeroth appears to ref
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