UNITED STATES PATENT AND TRADEMARK OFFICE
`________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`________________
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`INTEL CORPORATION,
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`Petitioner,
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`v.
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`ALACRITECH INC.,
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`Patent Owner
`________________
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`Case IPR2018-00234
`U.S. Patent 8,805,948
`________________
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`PATENT OWNER’S PRELIMINARY RESPONSE
`PURSUANT TO 35 U.S.C. § 313 AND 37 C.F.R. § 42.107
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`Case No. IPR2018-00234
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`TABLE OF CONTENTS
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`Page
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`I.
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`II.
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`INTRODUCTION .................................................................................1
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`OVERVIEW OF THE ’948 PATENT ..................................................6
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`A.
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`B.
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`The ’948 Patent Specification .....................................................6
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`The ’948 Patent Claims ............................................................ 10
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`III.
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`PROSECUTION HISTORY OF THE ’948 PATENT ...................... 11
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`IV. OVERVIEW OF THE ALLEGED PRIOR ART .............................. 12
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`A.
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`B.
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`C.
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`Thia, A Reduced Operation Protocol Engine (ROPE) for
`a Multiple-layer Bypass Architecture (1995) (“Thia”) ............ 12
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`Tanenbaum, Computer Networks, 3rd ed. (1996)
`(“Tanenbaum”) ......................................................................... 17
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`Stevens, TCP/IP Illustrated Volume 2: The
`Implementation (“Stevens”) (Ex. 1063) ................................... 19
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`V.
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`CLAIM CONSTRUCTION ............................................................... 21
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`VI. THE BOARD SHOULD EXERCISE ITS DISCRETION
`UNDER 35 U.S.C. § 314(A) AND 37 C.F.R. § 42.108(A) TO
`DENY INSTITUTION OF ANY CLAIM OF THE ‘205
`PATENT ............................................................................................. 21
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`A. All Factors Considered by the Board in Deciding whether
`to Exercise its Discretion to Deny Institution of a Petition
`Favor Denial of This Second Petition ...................................... 22
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`1.
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`2.
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`3.
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`4.
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`First Factor: Intel Has Filed Two Petitions
`Directed to the Same Claims of the ‘948 Patent on
`the Same Ground. .......................................................... 23
`Second Factor: Intel Held Back Alleged Evidence
`and Arguments from the First Petition that it Now
`Seeks to Add in the Second Petition. ............................. 24
`Third Factor: Intel Had Alacritech’s Preliminary
`Response to the First Petition and the Board’s
`Decision Denying the First Petition at the time the
`Second Petition Was Filed. ............................................ 25
`Fourth Factor: Intel Waited Months Between First
`Learning of the Stevens reference, the Deficiencies
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`5.
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`6.
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`7.
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`in its First Petition, and the Filing of the Second
`Petition. .......................................................................... 27
`Fifth Factor: Intel Offers No Explanation for the
`Time Elapsed Between Filing the First and Second
`Petitions Directed to the Same Claims of the Same
`Patent .............................................................................. 28
`Sixth Factor: Intel’s Incremental-Petitions Waste
`Finite Resources of the Board ........................................ 28
`Seventh Factor: Intel’s Incremental-Petitions Risk
`Issuance of a Final Determination Within One
`Year ................................................................................ 29
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`B.
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`The Board Also Should Exercise its Discretion to Deny
`Institution of the Third Petition Under 35 U.S.C. § 325(d) ..... 31
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`VII. EVEN IF THE BOARD DOES NOT EXERCISE ITS
`DISCRETION TO DENY THE SECOND PETITION, THE
`BOARD HAS ALREADY FOUND THAT STEVENS IS NOT
`AVAILABLE AS PRIOR ART ......................................................... 32
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`VIII. EVEN IF THE BOARD DOES NOT EXERCISE ITS
`DISCRETION TO DENY THE SECOND PETITION AND
`REVERSES COURSE IN FINDING THAT STEVENS WAS
`PUBLICALLY AVAILABLE, INTEL’S SECOND PETITION
`IS TIME BARRED ............................................................................. 35
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`IX. PETITIONER HAS NOT SUFFICIENTLY SHOWN A
`MOTIVATION TO COMBINE THIA WITH TANENBAUM
`OR STEVENS .................................................................................... 36
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`X.
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`PETITIONER HAS NOT SHOWN A DISCLOSURE OF
`PACKET PROCESSING FOR THE "CHECKING"
`LIMITATIONS OF THE CHALLENGED CLAIMS ....................... 39
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`XI. ALACRITECH RESERVES ITS RIGHTS UNDER THE
`PENDING OIL STATES CASE AT THE UNITED STATES
`SUPREME COURT ........................................................................... 46
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`XII. CONCLUSION .................................................................................. 46
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`TABLE OF AUTHORITIES
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`Cases
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`Butamax Advanced Biofuels LLC, v. Gevo, Inc.,
`Case IPR2014-00581 (PTAB Oct. 14, 2014) ............................................ 29
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`Dynamic Drinkware LLC v. Nat’l Graphics, Inc.,
` 800 F.3d 1375 (Fed. Cir. 2015) ................................................................ 34
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`General Plastic Industrial Co., LTD. v. Canon Kabushiki Kaisha,
`Case IPR2016-01357, (PTAB September 6, 2017) ...................... 21, 23, 28
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`Nvidia Corp. v. Samsung Electronics Co., LTD.,
`Case IPR2016-00134, (PTAB May 4, 2016) ............................................ 21
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`Nvidia Corp. v. Samsung Electronics Co., LTD.,
` Case IPR2016-00134, (PTAB May 4, 2016) ............................................. 2
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`Symbol Techs. Inc. v. Opticon Inc.,
` 935 F.2d 1569, 19 USPQ2d 1241 (Fed. Cir. 1991).................................. 13
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`Statutory Authorities
`35 U.S.C. § 21 ................................................................................................. 1
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`35 U.S.C. § 102 ............................................................................. 4, 24, 25, 26
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`35 U.S.C. § 103 ............................................................................................. 13
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`35 U.S.C. § 313 ............................................................................................... 1
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`35 U.S.C. § 314(A) ................................................................................. 21, 46
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`35 U.S.C. §§ 314, 325(d) ................................................................................ 3
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`35 U.S.C. § 315(b) ........................................................................................ 35
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`35 U.S.C. § 316(a)(11) ............................................................................ 22, 29
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`35 U.S.C. § 325(d) .................................................................................. 31, 32
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`Rules and Regulations
`37 C.F.R. §42.1(b) ........................................................................................ 29
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`37 C.F.R. § 42.107(a) ..................................................................................... 1
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`37 C.F.R. § 42.108 .......................................................................................... 3
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`37 C.F.R. § 42.108(a) ............................................................................... 2, 21
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`Legislative Materials
`157 Cong. Rec. S1034, S1041 (March 1, 2011) ........................................... 36
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`PATENT OWNER’S LIST OF EXHIBITS
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`Exhibit #
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`Description
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`Ex. 2001
`
`Not used
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`Ex. 2002
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`Defendant’s Invalidity Contentions in Case Nos. 2:16-
`cv-693-RWS-RSP (lead case), 2:16-cv-692-RWS-RSP,
`and 2:16-cv-695-RWS-RSP, dated November 11, 2016.
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`I.
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`INTRODUCTION
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`Petitioner Intel Corporation (“Intel”) filed its Second Petition (Paper 2, IPR
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`2018-00234, hereinafter “Second Petition”) requesting Inter Partes Review
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`(“IPR”) of claims 1, 3, 6-8, 17, 19, and 21-22 of U.S. Patent No. 8,805,948 (“the
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`’948 patent”). This is Intel’s second incremental-petition against the ’948 patent
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`challenging the same claims based on the same references and arguments as its
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`now denied First Petition (Paper 2, IPR 2017-01395, hereinafter “First Petition”).1
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`Pursuant to 35 U.S.C. § 313 and 37 C.F.R. § 42.107(a), Patent Owner Alacritech,
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`Inc. (“Alacritech”) files this Preliminary Response with arguments and information
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`as to why the Board should not institute review on Intel’s Second Petition.
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`Intel’s Second Petition against the challenged claims was filed on November
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`22, 2017, approximately five months after Intel filed its First Petition against the
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`'948 patent, three months after Alacritech filed its Preliminary Response (Paper 7,
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`IPR 2017-01395) identifying dispositive defects in Intel’s First Petition, the same
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`day that the Board denied institution on the First Petition (Paper 8, IPR 2017-
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`01395) based on the defects Alacritech identified, and one month before Intel filed
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`two requests for rehearing (Paper 9 and 10, IPR 2017-01395) of the Board’s denial
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`1 Intel no longer challenges claims 9, 11, or 14-16 in its Second Petition. Compare
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`Second Petition with First Petition.
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`of the First Petition and the Board’s subsequent denials (Paper 12 and 13, IPR
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`2017-01395) of the requests for rehearing. The sole ground in Intel’s Second
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`Petition is based on the same references that were asserted, and rejected, in the
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`First Petition for review of the challenged claims (Paper 8, IPR 2017-01395
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`(claims 1, 3, 6-8, 17, 19, and 21-22 over Thia (Ex. 1015), Tanenbaum (Ex. 1006),
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`and Stevens (Ex. 1063)) and many of Intel’s arguments raised in the Second
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`Petition to argue that Stevens is a “printed publication” were already rejected by
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`the Board in its denial of Intel’s requests for rehearing on the First Petition
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`(Compare Paper 9 and 10 with Third Petition.)
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`The Second Petition does not justify why the Board should exercise its
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`discretion and permit a second, serial attack by Intel against the challenged claims.
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`In fact, there is no analysis or evidence whatsoever presented with respect to the
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`factors that other panels have considered in exercising their discretion to deny
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`institution. See 35 U.S.C §§ 314(a), 325(d); 37 C.F.R. § 42.108(a); Nvidia Corp. v.
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`Samsung Electronics Co., LTD., Case IPR2016-00134, slip op. at 6-12, (PTAB
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`May 4, 2016) (Paper 9); General Plastic Industrial Co., LTD. v. Canon Kabushiki
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`Kaisha, Case IPR2016-01357, slip op. at 8-11, 15-22, (PTAB September 6, 2017)
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`(Paper 19); LG Electronics, Inc. v. Core Wireless Licensing S.A.R.L., IPR2016-
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`00986, slip op. at 6-15 (PTAB August 22, 2016) (Paper 12).
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`Alacritech therefore requests that the Board exercise its discretion and deny
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`this Second Petition because it represents undesirable incremental petitioning. See
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`35 U.S.C. §§ 314, 325(d); 37 C.F.R. § 42.108. Intel has engaged in what the Board
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`has characterized as “undesirable incremental-petitioning," relying on Alacritech’s
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`Preliminary Response and the Board’s decision in the First Petition proceedings—
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`involving the same parties, patent, claims, references, and arguments—to mount a
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`second attack against the challenged claims after an unsuccessful first attack, by
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`attempting to fix deficiencies, noted by Alacritech and the Board, that should have
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`been addressed in the First Petition. In addition, Intel plainly admits that it filed its
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`Second Petition with additional evidence that it anticipated and should have filed
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`with its First Petition: “Petitioner believed … that Petitioner would be permitted to
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`respond to Patent Owner’s challenge to Stevens2’s status as prior art [in the First
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`Petition] by offering supplemental evidence … .”2 (Second Petition at 2.) The
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`Board has correctly noted in denying a related Intel petition against Alacritech that
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`there is “no rule permitting the withholding of evidence necessary to establish a
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`2 To the extent Intel intended to rely on “supplemental evidence,” that reliance was
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`misplaced as supplemental evidence is served, not offered or filed, and does not
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`become part of the record unless and until ruled upon by the Board. 37 C.F.R. §
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`42.64 (b).
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`reasonable likelihood of success, including, among other things, making a
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`threshold showing that a reference was publicly available as prior art within the
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`meaning of 35 U.S.C. §§ 102 and 311(b).” (Paper 10, IPR2017-01402, at 10.)
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`As explained in Section VI, as all factors weigh in favor of denying institution, the
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`Board should exercise its discretion to deny institution of Intel’s Second Petition.
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`Other reasons support denial here as well.3 First, Intel failed to cure the
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`deficiencies in its First Petition surrounding the Stevens reference to show that it is
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`available prior art in this Second Petition proceeding. To wit, Intel relies primarily
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`on the identical Stansbury exhibit (Ex. 1063) and identical arguments in support of
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`its alleged public availability in the Second Petition that the Board already twice
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`rejected in connection with the First Petition. See Section VII. Intel’s new
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`evidence does not remedy the problems with Stevens or the Stansbury exhibit.
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`Accordingly, Intel still has not made a sufficient threshold showing that Stevens
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`qualifies as a “printed publication” in this Second Petition proceeding.
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`3 Alacritech expressly reserves the right to challenge any grounds or facts raised
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`in the Second Petition in these proceedings in the event that the Board institutes
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`trial. Nothing in this Preliminary Response shall be construed as a waiver of any
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`such challenge, or an acknowledgement or agreement not to dispute the sufficiency
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`of Intel's representations, evidence or arguments for any claim of the '948 Patent.
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`Second, Intel’s Second Petition is time barred because it was filed more than
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`one year after the date on which Alacritech’s Complaint for infringement was
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`served on Dell Corporation, a privy of Petitioner Intel, and more than one year
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`after the date on which Intel filed its motion to formally become a party to the
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`underlying Litigation. See 35 U.S.C. § 315(b). Allowing Intel to proceed with this
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`Second Petition would therefore violate the purpose of the one-year bar and its
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`express application to privies. See 157 Cong. Rec. S1034, S1041 (March 1, 2011).
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`Third, even if the Board does not exercise its discretion to deny the Second
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`Petition, finds its timely and revisits its prior decisions relating to the Stevens
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`reference, Petitioner has not sufficiently shown a motivation to combine Thia with
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`Tanenbaum or Stevens, nor the claimed “check[ing] . . . the packets” limitations in
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`the relied-upon references. See Sections IX - X. These deficiencies infect the
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`entire Second Petition, and the appropriate remedy is to deny institution.
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`For all these reasons, the Second Petition does not give rise to a reasonable
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`likelihood that Intel will prevail with respect to any challenged claim of ‘948
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`patent, and the Board should therefore deny institution of review.4
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`4 Alacritech also reserves its rights under the Oil States case pending before the
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`U.S. Supreme Court, as set forth in Section XI of this Preliminary Response.
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`II. OVERVIEW OF THE ’948 PATENT5
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`A. The ’948 Patent Specification
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`The ’948 patent is directed to accelerated network processing using an
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`intelligent network interface card (INIC) that provides “a fast-path that avoids host
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`protocol processing for most large multipacket messages, greatly accelerating data
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`communication.” Ex. 1001 at Abstract. As explained in the patent background,
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`when a conventional NIC prepares to send data from a first host to a second host,
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`“some control data is added at each layer of the first host regarding the protocol of
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`that layer, the control data being indistinguishable from the original (payload) data
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`for all lower layers of that host.” Id. at 2:39-42. For example,
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`an application layer attaches an application header to the payload data
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`and sends the combined data to the presentation layer of the sending
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`host, which receives the combined data, operates on it and adds a
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`presentation header to the data, resulting in another combined data
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`packet. The data resulting from combination of payload data,
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`application header, and presentation header is then passed to the
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`5 The ’948 patent is assigned to Alacritech and is the subject of co-pending
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`litigation, Alacritech, Inc. v. CenturyLink, Inc., 2:16-cv-00693-JRG-RSP (E.D.
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`Tex.); Alacritech, Inc. v. Wistron Corp., 2:16-cv-00692-JRG-RSP (E.D. Tex.); and
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`Alacritech, Inc. v. Dell Inc., 2:16-cv-00695-RWS-RSP (E.D. Tex.), which were all
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`consolidated for pre-trial purposes (“the Litigations”).
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`session layer, which performs required operations including attaching
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`a session header to the data and presenting the resulting combination
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`of data to the transport layer. This process continues as the
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`information moves to lower layers, with a transport header, network
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`header, and data link header and trailer attached to the data at each of
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`those layers, with each step typically including data moving and
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`copying, before sending the data as bit packets over the network to the
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`second host.
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`Id. at 2:42-57.
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`This process of adding a layer header to the data from the preceding layer is
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`sometimes referred to as “encapsulation” because the data and layer header is
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`treated as the data for the immediately following layer, which, in turn, adds its own
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`layer header to the data from the preceding layer. Each layer is generally not
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`aware of which portion of the data from the preceding layer is the preceding layer
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`header of user data; as such, each layer treats the data it receives from the
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`preceding layer as a generic payload. Id.
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`On the receiving side, the receiving host generally performs the reverse of
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`the sending process, beginning with receiving the bit packets from the network. Id.
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`at 2:58-60. Headers are removed, one at a time, and the received data is processed,
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`in order, from the lowest (physical) layer to the highest (application) layer before
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`transmission to a destination within the receiving host (e.g., to the operating system
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`space where the received data may be used by an application running on the
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`receiving host). Id. at 2:60-63. Each layer of the receiving host recognizes and
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`manipulates only the headers associated with that layer, since to that layer the
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`higher layer header data is included with and indistinguishable from the payload
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`data. Id. at 2:63-66. “Multiple interrupts, valuable central processing unit (CPU)
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`processing time and repeated data copies may also be necessary for the receiving
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`host to place the data in an appropriate form at its intended destination.” Id. at
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`2:66-3:3.
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`The host CPU processes the data by constructing (transmit side) or
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`destructing (receive side) the packet. The host CPU must be interrupted at least
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`one time per layer and, in response, the host CPU processes each layer, which
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`typically involves a copy and data manipulation operation (for example a
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`checksum computation operation). An interrupt is a signal to the processor emitted
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`by hardware or software indicating an event that needs immediate attention. An
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`interrupt alerts the processor to a high-priority condition requiring the interruption
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`of the current code the processor is executing. Id. This process involved with
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`traditional network interface cards results in “repeated copying and interrupts to
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`the CPU” of the host computer. Id. at 3:59-62. When the host CPU is interrupted,
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`it generally must stop all other tasks it is currently working on, including tasks
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`completely unrelated to the network processing. Frequent interrupts to the host
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`CPU can be very disruptive to the host system generally and cause system
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`instability and degraded system performance. Id.
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`The invention of the ’948 patent allows “data from the message to be
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`processed via a fast-path which accesses message data directly at its source or
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`delivers it directly to its intended destination.” Id. at 3:53-57. The fast-path
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`“bypasses conventional protocol processing of headers that accompany the data”
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`and “employs a specialized microprocessor designed for processing network
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`communication, avoiding the delays and pitfalls of conventional software layer
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`processing, such as repeated copying and interrupts to the CPU.” Id. at 3:57-62.
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`One embodiment of the fast-path is shown in Figure 6 of the ’948 patent,
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`which is reproduced below. In this embodiment, the INIC performs at least the
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`network and transport layer processing (e.g., IP and TCP layer processing in
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`TCP/IP), freeing up the CPU on the host (“client”) computer to do other tasks. The
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`fast-path also reduces or eliminates the number of interrupts sent to the CPU on the
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`host/client. An embodiment of the more traditional “slow-path” is also shown,
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`where the host/client is responsible for the IP and TCP layer processing. In the
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`slow-path, the CPU on the host/client is interrupted at least one time for each layer
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`for processing.
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`Advantageously, the claimed invention allows for more efficient network
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`processing by relieving the host CPU of per-frame processing and reducing the
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`number of interrupts. Id. at 9:1-5. For fast-path communications, only one
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`interrupt occurs at the beginning and end of an entire upper-layer message
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`transaction, and “there are no interrupts for the sending or receiving of each lower
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`layer portion or packet of that transaction.” Id. at 9:5-10. As stated above, the
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`claimed arrangement allows for enhanced network and system performance, faster
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`data throughput, increased system stability, and an overall better user experience.
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`B.
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`The ’948 Patent Claims
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`The ’948 patent includes three independent claims. Notably, for this
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`Preliminary Response, both independent claims 1 and 17, which are at issue in the
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`Second Petition recite, inter alia, “checking […] whether the packets have certain
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`exception conditions, including […] whether the packets are IP fragmented, […]
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`have a FIN flag set, [and/or] […] are out of order.” Id. at 19:43-20:7, 22:1-25.
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`As explained in Section X, this claimed feature is not found in any of the
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`references cited by Petitioner. Dependent claims 3, 6-8, 19, 21 and 22, all of
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`which are also at issue in the Second Petition, incorporate the same limitation
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`missing in independent claims 1 and 17.
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`III. PROSECUTION HISTORY OF THE ’948 PATENT
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`The ’948 patent was filed on September 26, 2013 as Application No.
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`14/038,297, which was a continuation of Application No. 09/692,561, filed
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`October 18, 2000, which was a continuation of Application No. 09/067,544, filed
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`April 27, 1998, which claims the benefit of Provisional Application No.
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`60/061,809, filed on October 14, 1997.
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`The ’948 patent was subject to a thorough examination by Examiner
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`Moustafa M. Meky, who allowed the application on June 20, 2014 after
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`considering references (including Thia and Tanenbaum) disclosed by the Applicant
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`and after conducting the Examiner’s own prior art search on June 16, 2014. Ex.
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`1002 at .111-.149. In connection with the allowed claims, the Examiner stated:
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`None of the prior art of record taken singularly or in combination
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`teaches or suggests a network interface of a host computer for
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`checking whether received packets have a certain exception
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`conditions, including whether the packets are IP fragmented, have a
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`FIN flag set, or out of order; processing any of the received packet
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`that have the exception conditions, and storing payload data of the
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`received packets that do not have any of the exception conditions in
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`a buffer of the host computer and without any TCP header stored
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`between the payload data of the received packets.
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`Ex. 1002 at .117 (emphasis added). An Issue Notification was mailed on July 23,
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`2014, and the ‘948 patent issued on August 12, 2014.
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`IV. OVERVIEW OF THE ALLEGED PRIOR ART
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`As described above, Intel relies on Thia, Tanenbaum, and Stevens, which
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`Intel still has not established as prior art. These references, each alone or in
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`combination, fail to teach or suggest all the limitations recited in the claims of the
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`’948 patent. For example, the references are completely silent as to bypass
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`exception conditions that involve checking whether the packets are IP fragmented.
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`The sections below summarize the references and underscore their shortcomings.
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`A. Thia, A Reduced Operation Protocol Engine (ROPE) for a Multiple-
`layer Bypass Architecture (1995) (“Thia”)
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`Thia appears on the face of the ’948 patent under “References Cited” and
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`was initialed by the Examiner in an Information Disclosure Statement (IDS) dated
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`June 15, 2014. Ex. 1002 at .120-.144. Thia was therefore already considered and
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`allowed over by the Examiner during the prosecution of the ’948 patent.
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`As an initial matter, Thia presents a “feasibility study for a new approach to
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`hardware assistance” and the “final step of generating a chip layout for fabrication
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`and fault analysis was not performed.” Ex. 1015 at .002 and .008. Since Thia at
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`best discloses an inoperative device, it is a non-enabling reference. A non-
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`enabling reference is prior art under 35 U.S.C. § 103 only “for all that it teaches.”
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`Beckman Instruments v.LKB Produkter AB, 892 F.2d 1547, 1551, 13 USPQ2d
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`1301, 1304 (Fed. Cir. 1989); see Symbol Techs. Inc. v. Opticon Inc., 935 F.2d
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`1569, 1578, 19 USPQ2d 1241, 1247 (Fed. Cir. 1991). The feasibility study
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`discloses at a high level the idea of offloading session and transport layer
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`processing to a Reduced Operation Protocol Engine (“ROPE”) chip, but does not
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`teach many of the implementation details.
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`Thia describes a bypass stack such as the ROPE chip that provides a
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`hardware “fast path” for bulk data transfer. Id. at .002-.003.
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`Id. at .003, Fig. 1 (adapted from Second Petition). Regarding the receive bypass
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`test, Thia merely discloses a test that matches headers of incoming data packets
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`with a template using header prediction:
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`Id. at .003 (adapted from Second Petition). Thia does not address exception
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`conditions relating to the bypass test.
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`Table 1 of Thia “identifies procedures which are strong candidates for
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`implementation in the bypass chip, and those which are better handled by the host,
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`during the data transfer phase.” Id. at .006.
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`Id. As shown in the table, Thia identifies bypassable functions in the presentation
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`layer, the session layer, the transport layer, and all three of those layers. Thia,
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`however, does not address the bypass test or bypassable functions in relation to the
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`network layer, which is where fragmentation/segmentation occurs. Indeed, Thia
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`assumes that any packets that have been fragmented have been reassembled at the
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`receiver before being passed to the Transport layer. Id. at .013-.014 (stating: “In
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`an ATM system we assume that the segmentation and reassembly or SAR
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`operation would also be in hardware, since it is done frequently”; “The
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`Segmentation and Reassembly sublayer of the ATM adaption layer is a good place
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`for [segmentation/reassembly] functions”).
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`B.
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`Tanenbaum, Computer Networks, 3rd ed. (1996) (“Tanenbaum”)
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`Tanenbaum is the third edition of a textbook relating to computer networks.
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`As acknowledged by Petitioner, it too was already considered by the Examiner
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`during prosecution of the ’948 patent, which was found to be allowable over
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`Tanenbaum. Second Petition at n.5. On pages 583-586, Tanenbaum describes
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`“fast” transport protocol data unit (“TPDU”) processing. Ex. 1006 at .583-86. On
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`the sending side, Tanenbaum notes that “[i]n the normal case, the headers of
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`consecutive data TPDUs are almost the same.” Id. at .583. In view of this
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`observation, a “prototype header” is defined. Id. In order to construct a packet for
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`transmission, at the TCP layer, the TCP prototype header is copied into the output
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`buffer, the sequence number is filled in, the TCP checksum is computed, and the
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`sequence number is incremented in memory. Id. at .584. Then, the TCP header
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`and data is handed “to a special IP procedure” at the IP layer, where the IP
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`prototype header is copied into the output buffer, the “Identification” field is
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`inserted, and the IP checksum is computed. Id. The packet is then ready for
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`transmission.
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`On the receive side, a “connection record” is stored in a hash table for
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`lookup (or the last record is tried first). Id. at .585. Then conditions for a special
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`“fast path” TCP procedure are checked:
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`The TPDU is then checked to see if it is a normal one: the state is
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`ESTABLISHED, neither side is trying to close the connection, the
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`TPDU is a full one, no special flags are set, and the sequence number
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`is the one expected. These tests take just a handful of instructions. If
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`all conditions are met, a special fast path TCP procedure is called.
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`Id. at 585. The connection record is updated, and data is copied to the user. Id.
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`During the copy process, the fast path computes the checksum. Id. Tanenbaum
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`explains that this general scheme of first making a quick check to see if the header
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`is what is expected, and having a special procedure to handle that case, is called
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`“header prediction.” Id. Tanenbaum, however, discloses conditions that relate to
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`checking TPDUs, i.e. transport protocol data units, and not packets. The test is
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`performed at the transport layer and not the network layer where packets are
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`processed to generate TPDUs to be passed on to the transport layer.
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`Further, Tanenbaum teaches away from performing any TCP/IP protocol
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`processing on anything other than the host CPU. Tanenbaum is aware of the
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`possibility of a transport entity being on a network interface card:
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`The hardware and/or software within the transport layer that does the
`work is called the transport entity. The transport entity can be in the
`operating system kernel, in a separate user process, in a library
`package bound into network applications, or on the network interface
`card.
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`Id. at .498 (bold in original). Petitioner points to this to assert that Tanenbaum
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`“teaches that the transport entity may be built into the network interface card.”
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`Petition at 45. However, Tanenbaum clearly teaches away from doing so:
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`A tempting way to go fast is to build fast network interfaces in
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`hardware. The difficulty with this strategy is that unless the protocol is
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`exceedingly simple, hardware just means a plug-in board with a
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`second CPU and its own progra