(12) United States Patent
`Casebolt et al.
`
`I lllll llllllll Ill lllll lllll lllll lllll lllll lllll lllll lllll llllll llll llll llll
`
`US006625790Bl
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,625, 790 Bl
`*Sep.23,2003
`
`(54) METHOD AND APPARATUS FOR
`DETECTING THE TYPE OF INTERFACE TO
`WHICH A PERIPHERAL DEVICE IS
`CONNECTED
`
`(75)
`
`loventors: Mark W. Casebolt, Seattle, WA (US);
`Lord Nigel Featherston, Redmond,
`WA(US)
`
`(73) A5Signee: Microsoft Corporation, Redmond, WA
`(US)
`
`7/1997 Li cl al. ..................... 395/883
`5,644,790 A
`5/ 1998 Holmdah l et al. ...•...... 395/883
`5,754,890 A
`8/ 1998 Mori .......................... 395/309
`5,793,999 A
`10/1998 Rao ........................... 395/883
`5,828,905 A
`11/ 1998 Jolley et al. ................ 395/309
`5,832,244 A
`1/ 1999 Hashemi et al. ............ 395/828
`5,857,112 A
`7/1999 Jones ......................... 710/129
`5,928,347 A
`8/1999 Svancarek et al. ...•........ 710/63
`5,935,224 A
`12/1999 Jones et al. ................... 710/62
`6,006,295 A
`6,460,094 Bl * 10/2002 Hanson et al. ........... ... ... 710/8
`
`FOREIGN PATENT DOCUMENTS
`
`( *) Notice:
`
`Subject to any disclaimer, tbe term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`EP
`WO
`WO
`
`0 860 781 A2
`WO 97/3J386
`WO 97/17214
`
`2/1998
`8/ 1997
`4/1999
`
`This patent is subject to a terminal dis(cid:173)
`claimer.
`
`(21) Appl. No.: 09/409,683
`
`(22) Filed:
`
`Oct. l, 1999
`
`(63)
`
`(51)
`(52)
`
`(58)
`
`(56)
`
`Related U.S. Application Data
`
`Continuation-i n-part of application No. 09/ 112,171 , filed on
`Jul. 8, 1998, now Pal. No. 6,460,094.
`Int. Cl.7 .................................................. G06F 9/45
`U.S. C l .. ................................ 716/8; 716/9; 716/10;
`716/11
`Field of' Search .......... ... ... ... ... ....... 716/4, 8; 712/1,
`712/230; 710/8, 26, 63, 108, 262, 269,
`305, 306; 379/142.15
`
`References C ited
`
`U.S. PATENT DOCUMENTS
`
`4,500,933 A
`4,785,469 A
`5,043,938 A
`5,473,264 A
`5,481,696 A
`5,548,782 A
`5,577,213 A
`5,612,634 A
`
`2/ 1985 Chan . . . . . .. .. . . . .. . . . . . .. . . . .. . 360/69
`11/1988 Joshi et al. ................. 375/ 110
`8/199 l Ebersole ..................... 364/900
`12/ 1995 Mader ct al. ................. 326/30
`1/ 1996 Lo mp et al. ................ 395/500
`8/1996 Michael el al. ............. 395/835
`11/J 996 Avery et al. ................ 395/280
`3/ 1997 MacKenna . . . . . . . .. . ... . . . . . . 326/62
`
`OTHER PUBLIC.<X:rIONS
`
`Uoiversal Serial Bus Specification, Rev. l.J, Section 7.1.5:
`Device speed identification, pp. 113 and 114, Sep. 23, 1998.
`
`* cited by examiner
`
`Primary Exa111iner-Vull1e Siek
`Assistant Examiner-Naum Levin
`(74) Attorney, Agent, or Firm-Joseph R. Kelly; Westman,
`Champlin & Kelly, P.A.
`
`(57)
`
`ABSTRACT
`
`A peripheral device is connectable 10 a computer having one
`of a first interface and a second interface. The first interface
`commuoicates with the peripheral device over a differential
`data connection having a first data conductor and a second
`data conductor. The second interface communicates with the
`peripheral device over a clock conductor and a single ended
`data connection which includes a data conductor. The
`peripheral device includes an interface detection component
`coupled to at least o ne of first and second communication
`conductors used to communicate between the peripheral
`device and the computer. Thc interface detection component
`is configured to detect which of the first and second inter(cid:173)
`faces the peripheral device is connected lo.
`
`33 C laims, 7 Drawing Sheets
`
`142'(
`
`VCC
`
`154
`
`INTERFACE CONTROL
`SHOWN IN LOW SPEED CONFIGURATION
`
`146
`
`1~8
`
`PSl2
`COMMUNICATIONS
`
`152
`
`TO
`COMPUTER
`20
`
`ZTE/SAMSUNG 1010-0001
`IPR2018-00111
`
`

`

`U.S. Patent
`
`Sep. 23,2003
`
`Sheet 1 of 7
`
`US 6,625,790 Bl
`
`FIG. 1
`
`REMOVABLE
`STORAGE
`29
`
`OPTICAL
`DISK
`31
`
`48
`VIDEO ADAPTER
`
`____ _,
`
`MONITOR
`47
`
`COMPUTER20
`
`Optical Disk Drive
`30
`
`Magnetic Disk
`Drive 28
`
`HARO DRIVE 27
`
`23
`
`SERIAL
`PORT
`INTERFACE
`46
`
`PS2/USB
`PORT45
`
`CPU
`
`21
`
`ROM24
`BIOS26 RAM 25
`OPERATING
`SYSTEM 35
`
`MEMORY22
`
`PROGRAM
`MODULE37
`
`APPLICATION
`PROGRAMS36
`,___ ____ _. PROGRAM DATA 38
`
`NETWORK
`ADAPTER 53
`
`KEYBOARD MOUSE
`40
`42
`
`REMOTE
`COMPUTER49
`
`MEMORY50
`
`ZTE/SAMSUNG 1010-0002
`IPR2018-00111
`
`

`

`U.S. Patent
`
`Sep. 23, 2003
`
`Sheet 2 of 7
`
`US 6,625,790 Bl
`
`108
`
`USB
`INTERFACE 102
`
`COMPUTER 20
`
`21
`
`100
`
`HIGH SPEED USB
`PERIPHERAL DEVICE
`
`108
`
`118
`
`FIG. 2A
`
`108
`
`112
`
`120
`
`USB
`INTERFACE 102
`
`COMPUTER 20
`
`21
`
`LOW SPEED USB
`PERIPHERAL DEVICE
`
`HOST
`D- PROCESSOR
`r---t-t--r-~..ff--+-~..:..J
`
`106 122
`
`116
`
`FIG. 28
`
`118
`
`ZTE/SAMSUNG 1010-0003
`IPR2018-00111
`
`

`

`U.S. Patent
`
`Sep. 23,2003
`
`Sheet 3 of 7
`
`US 6,625,790 Bl
`
`<r-
`N
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`
`FIG. 3
`
`20
`COMPUTER
`TO
`
`152
`
`PS2 CLOCK/USB D+
`
`PS2 DATA/USB 0-
`
`COMMUNICATIONS
`PSfl
`
`148
`
`INTERFACE ENGINE
`USB SIE
`
`160
`
`144
`
`146
`
`SHOWN IN LOW SPEED CONFIGURATION
`
`INTERFACE CONTROL
`
`154
`
`VCC
`
`ADAPTER
`
`PS/2
`
`150
`
`vcc
`
`142\.
`
`ZTE/SAMSUNG 1010-0005
`IPR2018-00111
`
`

`

`U.S. Patent
`
`Sep.23,2003
`
`Sheet 5 of 7
`
`US 6,625,790 Bl
`
`170
`
`START silNIT
`
`COUNTING
`
`CONTACT
`BOUNCE
`DELAY
`
`FIG. 4
`
`172
`
`TERMINAL
`COUNT
`
`178
`
`COUNTING
`
`180
`
`siUNCERTfAN
`
`NOT
`SE1
`
`ANY VALID USB
`COMMUNICATION
`
`siPS2_DETECTED
`
`siUSB _DETECTED
`
`ZTE/SAMSUNG 1010-0006
`IPR2018-00111
`
`

`

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`~ •
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`
`FIG. 5
`
`20
`COMPUTER
`TO
`
`152
`
`·158
`
`PS2 CLOCK/USS D+
`
`PS2 DATA/USB 0-
`
`160
`
`188
`
`154
`
`vcc
`ADAPTER
`
`PS/2
`
`-'
`I
`J
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`I
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`
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`
`150
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`192
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`'---!
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`\.
`190
`
`-
`
`INTERFACE CONTROL
`
`182~
`
`SHOWN IN LOW SPEED CONFIGURATION
`
`COMMUNICATIONS
`PS/2
`
`148
`
`INTERFACE ENGINE
`USB SIE
`
`146
`
`PULL-UP CONTROL
`
`ZTE/SAMSUNG 1010-0007
`IPR2018-00111
`
`186 _ ___.. ______ _
`
`184
`
`

`

`U.S. Patent
`
`Sep. 23,2003
`
`Sheet 7 of 7
`
`US 6,625,790 Bl
`
`1mSec
`
`FIG. 6
`
`(COUNTING
`
`siTOGGLE _OM
`ATIACHIDETACH
`
`TOGGLE
`TEST
`FAIL
`
`204
`
`use
`TOGGLE
`PATERERN
`10101
`
`PS/2
`TOGGLE
`PATTERN
`11111
`
`ZTE/SAMSUNG 1010-0008
`IPR2018-00111
`
`

`

`US 6,625,790 Bl
`
`1
`METHOD AND APPARATUS FOR
`DETECTING THE TYPE OF INTERFACE TO
`WHICH A PERll>HERAL DEVICE IS
`CONNECTED
`
`REFERENCE TO CO-PENDLNG APPLICATION
`
`The present applicaiion is a continuation-in-part of pend(cid:173)
`ing U.S. patent application Ser. No. 09/112,171, filed Jul. 8,
`1998 now U.S. Pat. No. 6,460,094 entitled " METHOD AND
`APPARATUS FOR DETECTING THE TYPE OF INTER(cid:173)
`FACE TO WHICH A PERIPHERAL DEVICE IS CON(cid:173)
`N£CTED" a.nd assigned 10 the same assignee as the present
`applicalioa, and which is hereby incorporated by reference.
`
`BACKGROUND OF THE INVENTION
`
`10
`
`15
`
`2
`the host computer. The open-collector or open-drain circuit
`(commonly a transistor) is typically implemented inside the
`microprocessor. Another pull-up resistor is required inside
`the peripheral device as well. The peripheral device com-
`5 municating over a PS2 interface is responsible for providing
`a clock signal on the clock conductor, regardless of the
`direction of data flow on the data conductor. The host
`computer pulls the clock conductor to a logic low level to
`inhibit communication from the peripheral device, aod it can
`also pull tbe data conductor low to signal to the peripheral
`device that the host computer intends to transmit data to the
`peripheral device.
`The USB interface also uses two conductors which
`include differential data signal conductors D+ and 0-.
`In tbe USB interface at the USB port (i.e., at the host
`computer or USB hub), the two conductors are pulled to a
`logic low level via 15 k ohm resistors. In the peripheral
`device, the D+ conductor is pulled to approximately 3 .3
`volts via a 1.5 k ohm resistor if the peripheral device is a
`20 high-speed USB peripheral device. Tbe D- conductor is
`pulled to 3.3 volts via a l.5 k ohm resistor if the peripheral
`device is a low-speed USB peripheral device. When a
`peripheral device is attached to the USB port, the USB host
`determines whether it is a low-speed or high-speed device
`25 by determining which of the D+ or D- conductors is pulled
`to the logical high level.
`Thus, it can be seen that the two interfaces have different
`hardware structures, a.ad communicate using different soft(cid:173)
`ware protocols. Traditionally, separate peripheral devices
`30 have been provided, one being configured to communicate
`wilh a USB interface, and the other being configured to
`communicate with a PS2 interface. This requires the manu(cid:173)
`facturer of such peripheral devices to offer two different
`types of peripheral devices in order to suppor1 these two
`35 different interfaces.
`
`The present invention relates to a peripheral device con(cid:173)
`oectable to a computer. More particularly, the present inven(cid:173)
`tion re lates to a peripheral device configured to detect the
`type of interface LO which it is connected.
`A wide variety of peripheral devices are currently con(cid:173)
`figured to be coooectable to computers. Such peripheral
`devices commonly include user input devices, such as
`keyboards, point and click devices (traditionally referred to
`as a computer mouse) and other similar types of devices.
`The computer IO which such devices are connected com(cid:173)
`municates with the devices through one of a number of
`interfaces. Interfaces commonly used to connect to such
`peripheral devices include a serial interface (such as an
`RS232 interface) and a PS2 interface. Indeed, the PS2
`interface bas long been a standard for connecting keyboards
`and mice to computers.
`However, recently, another serial interface referred to as
`a universal serial bus (USB) interface has been introduced.
`The USB interface accommodates a wide variety of com(cid:173)
`puter peripherals, including, for example, keyboards and
`mice. However, a conventional computer is typically pro(cid:173)
`vided with only one interface (such as a PS2 or USB
`interface) for communication with peripheral devices. 40
`Therefore, if the computer is provided with a PS2 interface,
`the keyboard or mouse must be configured to support
`communication with the computer according to a protocol
`defined by the PS2 interface. Similarly, if the computer is
`provided with the USB interface, the keyboard or mouse 45
`must be configured to communicate according to a protocol
`defined by the USB interface.
`In order to do this, a conventional computer peripheral
`device contains a microprocessor which runs a software
`program to carry out the functions of that particular periph(cid:173)
`eral device. la the device such as a keyboard or mouse, the
`software program includes an interface between the peripb(cid:173)
`eral device and the host computer, through which the periph(cid:173)
`eral device communicates with the host computer. Such
`communication often includes receiving commands from
`the host computer and transmitting data and status informa(cid:173)
`tion to the host computer.
`As discussed above, the PS2 and USB interfaces have
`different hardware and software requirements, which must
`be met by the microprocessor in the peripheral device so that 60
`the peripheral device can communicate with tbe host com(cid:173)
`puter. The PS2 interface uses two conductors which include
`a separate clock conductor and a separate data conductor.
`These conductors are driven by the computer through an
`open-collector or open-drain circuit, and have a pull-up 65
`resistor (typically in lhe range of 2 k ohms to 10 k ohms)
`pulling the conductor to a rail voltage (such as VCC) inside
`
`SUMMARY OF THE INVENTION
`The present invention defines a method and apparatus in
`the peripheral device such !hat the peripheral device can
`determine which type of interface it is connected to, and
`configure itself accordingly.
`The peripheral device is connect able to a computer having
`one of a first interface and a second interface. The first
`interface communicates with a peripheral device over a
`differential data connection having a first data conductor and
`a second data conductor. The second interface communi(cid:173)
`cates with the peripheral devi.ce over a clock conductor and
`a single-ended data connection, which includes a data con(cid:173)
`ductor. The peripheral device has first and second commu-
`50 nication conductors configured for connection to the first
`and second data conductors in the differential data connec(cid:173)
`tion and to the first data conductor in the single ended data
`connection and the clock conductor. The peripheral device
`includes an interface detection component configured to
`55 detect which of the first and second interfaces the peripheral
`device is connected to. The peripheral device also includes
`a controller component configured to communicate between
`the peripheral device and the computer according to a
`protocol corresponding to the detected interface.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a block diagram of an exemplary environment
`in which an input device in accordance with the present
`invention can be used.
`FIGS. 2A-2C illustrate conventional high-speed and low(cid:173)
`speed USB peripheral devices and a PS2 peripheral device
`coupled to a USB interface and a PS2 interface, respectively.
`
`ZTE/SAMSUNG 1010-0009
`IPR2018-00111
`
`

`

`US 6,625,790 Bl
`
`10
`
`3
`FIG. 3 illustrates a peripheral device ia accordance with
`one embodiment of the present invention.
`FIG. 4 is a state diagram illustrating the operation of the
`peripheral device shown ia FIG. 3.
`FIG. 5 is a block diagram of a peripheral device in s
`accordance with another embodiment of tbe present inven(cid:173)
`tion.
`FIG. 6 is a state diagram illustrating the operation of the
`peripheral device sbowu in FIG. 5.
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIM ENTS
`Tbe present invention includes a method and apparatus,
`implemented ia a peripheral device, by which the peripheral
`device detects whether it is coupled to a PS2 interface or a
`USB interface. A peripheral device, in accordance with one
`aspect of the present invention, is configured initially to
`expect a first interface and senses the state or the interface
`to configure itself appropriately.
`FIG. 1 and the related discussion are intended to provide
`a brief, general description of a suitable computing envi(cid:173)
`ronment in which the invention may be implemented.
`Although not required, the invention will be described, at
`least in part, in the general context of computer-executable
`instructions, such as program modules, being executed by a
`personal computer or other computing device. Generally,
`program modules include routine programs, objects,
`components, data structures, etc. that perform particular
`tasks or implement particular abstract data types. Moreover,
`those skilled in the art will appreciate that tbe invention may
`be practiced with other computer system configurations,
`including hand-held devices, multiprocessor systems,
`microprocessor-based or programmable consumer
`e lectronics, network PCs, minicomputers, mainframe
`computers, and the like. The invention is also applicable in
`distributed computing environments where tasks are per(cid:173)
`formed by remote processing devices that are linked through
`a communications network. In a distributed computing
`environment, program modules may be located in both local
`and remote memory storage devices.
`With reference to FIG. 1, an exemplary environment for
`the invention includes a general purpose computing device
`in the form of a conventional personal computer 20, includ(cid:173)
`ing proces.sing unit 21, a system memory 22, and a system
`bus 23 that couples various system components including
`the system memory to the processing unit 21. The system
`bus 23 may be any of several types of bus structures
`including a memory bus or memory controller, a peripheral
`bus, and a local bus using any of a variety of bus architec(cid:173)
`tures. The system memory includes read only memory
`(ROM) 24 a random access memory (RAM) 25. A basic
`input/output 26 (BIOS), containing the basic routine that
`helps to transfer information between elements within the
`personal computer 20, such as during start-up, is stored in
`ROM 24. The personal computer 20 further includes a bard
`disk drive 27 for reading from aad writing to a hard disk (not
`shown), a magnetic disk drive 28 for reading from or writing
`to removable magnetic disk 29, and aa optical clisk drive 30
`for reading from or writing to a removable optical disk 31
`such as a CD ROM or other optical media. The bard disk
`drive 27, magnetic disk drive 28, and optical disk drive 30
`are connected to the system bus 23 by a hard disk drive
`interface 32, magnetic disk drive interface 33, and an optical
`drive interface 34, respectively. The drives and the associ(cid:173)
`ated computer-readable media provide nonvolatile storage
`of computer readable instructions, data structures, program
`modules and other data for the personal computer 20.
`
`4
`Although the exemplary environment described herein
`employs a bard disk, a removable magnetic disk 29 and a
`removable optical disk 31, it should be appreciated by those
`skilled in the art that other types of computer readable media
`wh.ich can store data tbat is accessible by a computer, such
`as magnetic casseues, flash memory cards, digital video
`disks, Bernoulli cartridges, random access memory (RAM),
`read only memory (ROM), and the like, may also be used in
`the exemplary operating environment.
`A number of program modules may be s tored oa the hard
`disk, magnetic disk 29, optical disk 31, ROM 24 or RAM 25,
`including an operating system 35, one or more application
`programs 36, other program modules 37, and program data
`38. A user may enter commands and information into the
`15 personal computer 20 through input devices such as a
`keyboard 40 and pointing device (or mouse) 42. Other input
`devices (not shown) may include a microphone, joystick,
`game pad, satellite dish, scanner, or the like. 'lnese and other
`input devices are often connected to the processing Ltnit 21
`20 through one of a plurality of ports. For instance, keyboard 40
`and mouse 42 are connected through a PS2 or USB interface
`45. Jn the illustrative embodiment, interface (or port) 45 is
`coupled to the system bus 23. User inpu.t devices may also
`be connected by other interfaces, such as a sound card, a
`25 parallel port, or a game port. A monitor 47 or other type of
`display device is also connected to the system bus 23 via an
`interface, such as a video adapter 48. In adclition to the
`monitor 47, personal computers may typically include other
`peripheral output devices such as speakers and printers (not
`30 shown).
`The personal computer 20 may operate in a networked
`environment using logic connections to one or more remote
`computers, such as a remote computer 49. The remote
`computer 49 may be another personal computer, a server, a
`35 router, a network PC, a peer device or other network node,
`and typically includes many or all of the elements described
`above relative to the personal computer 20, although only a
`memory storage device 50 has been illus trated in FIG. 1. Tbe
`logic connections depicted in FIG. 1 include a local area
`4o network (LAN) 51 and a wide area network (WAN) 52. Such
`networking environments are commonplace in offices,
`enterprise-wide computer network intranets and the Internet.
`When used in a LAN networking environment, the per(cid:173)
`sonal computer 20 is connected to the local area network 51
`45 through a network interface or adapter 53. Wben used in a
`WAN networking environment, the personal computer 20
`typically includes a modem 54 or other means for establish(cid:173)
`ing communications over the wide area network 52, such as
`the Internet. The modem 54, which may be internal or
`50 external, is connected to the system bus 23 via the serial port
`interface 46. Ta a network environment, program modules
`depicted relative to the personal computer 20, or portions
`thereof, may be stored in the remote memory storage
`devices. It will be appreciated that the network connections
`55 shown are exemplary and other means of establishing a
`communications link between the computers may be used.
`FIGS. 2A-2C illustrate conventional peripheral devices
`coupled to conventional interfaces. FIG. 2A illustrates a
`high-speed USB peripheral device 100 connected through
`60 USB interface 102 to CPU 21 of host computer 20. It should
`be noted that high-speed USB peripheral device 100 can be
`any suitable peripheral device, such as keyboard 40 or
`mouse 42 or another suitable peripheral device. Peripheral
`device 100 is connected to USB interface 102 and commu-
`65 nicates therewith over two conductors 104 and 106. Con(cid:173)
`ductors 104 and 106 are connected to corresponding con(cid:173)
`ductors 108 and 110 through USB connector 112.
`
`ZTE/SAMSUNG 1010-0010
`IPR2018-00111
`
`

`

`US 6,625,790 Bl
`
`20
`
`25
`
`6
`appropriately. This inhibits communication from peripheral
`device U4. Host processor 21 can also pull the data con(cid:173)
`ductor 108 low by manipulating transistor 138 in order to
`signal peripheral device U4 that host processor 21 intends
`s 10 transmit data.
`FIG. 3 illustrates a peripheral device 142 in accordance
`with one embodiment of the present invention. Peripheral
`device 142 includes a communication controller 144 which,
`in turn, includes a USB SIE interface engine 146 and a PS2
`l O communications controller 148. Peripheral device 142 also,
`in one illustrative embodiment, includes pull-up resistor 150
`which pulls the PS2 data/USB D- signal line lo a predeter(cid:173)
`mined voltage potential (such as VCC). Peripheral device
`142 also includes, in one illustrative embodiment, a cable
`15 with USB connector 152.
`II should be noted that, in FIG. 3 , the PS2 data and USB
`D- lines are indicated as being carried by signal line or
`conductor 160 while the PS2 clock and USS D+ signals are
`indicated as being carried by conductor 158. Of course, the
`USB D+ signal can be carried by the same conductor as the
`PS2 data signal and the USS D- signal can be carried by the
`same conductor as the PS2 clock signal. Also, while pull-up
`resistor 150 is shown coupled to conductor 160 (which
`corresponds to the USB D- signal), it could also be coupled
`to the conductor which corresponds to the USB D+ signal
`where the USB device is a high speed device, rather than a
`low speed device. However, the present discussion will
`proceed with respect to the embodiment illustrated in FIG.
`3 , for the sake of simplicity.
`FIG. 3 further illustrates a PS2 adapter 154 in accordance
`with one embodiment of the present invention. Adapter 154
`includes a USS connector 156 which mates with USB
`connector 152. Adapter 154 connects the signal lines 158
`35 and 160 to an output connector 162 which is suitable for
`being coupled 10 a connector or cable from computer 20. In
`one illustrative embodiment, connectors 152 and 156 are
`implemented as a USB series A plug and receptacle, respec(cid:173)
`tively. Connector 162 is implemented as a PS2 mini-din
`40 connector.
`Adapter 154, in the illustrative embodiment, also includes
`a pair of pull-up resistors 164 and 166. When adapter 154 is
`coupled to peripheral devi.ce 142, pull-up resistor 164 pulls
`the PS2 clock/USB D+ signal li.ne to VCC. Resistor 166
`pulls the PS2 data/USE D- signal line to VCC as well. The
`pull-ups in adapter 154 eliminate the necessity for the
`microprocessor on peripheral device 142 to control these
`dynamically. 1liis saves firmware code space and also
`reduces necessary pin count oo the microproces.sor by one or
`two pins. This provides a significant cost savings.
`Table 1 below illustrates the configuration of the two
`signals provided by both USB and PS2 devices. Table 1
`illustrates the signals for a USB low speed device.
`
`s
`Conductors 104 and 106 carry signals denoted D+ aad D(cid:173)
`in a high-speed USB device. Signals D+ and 0 - are differ(cid:173)
`ential digital data signals with which peripheral device 100
`communicates with computer 20.
`In a high-speed USB arrangement, conductor 104, which
`carries signal 0+, is pulled to a logical high level (such as
`a +5 Volt supply or other desired supply voltage potential
`hereinafter referred 10 as VCC or the VCC rail) by a pull-up
`resistor 114. Resistor 114 is preferably valued such that the
`voltage potential 10 which conductor 104 is pulled is
`approximately 3.3 volts. Therefore, resistor U4 can, for
`instance, be a 7.5 k ohm resistor connected to a 5 volt VCC
`rail.
`lo USB interface 102 on computer 20, both conductors
`108 and 110 (which correspond to ihe D+ and D- signals)
`are pulled 10 a logic low level by two 15 k ohm resistors 116
`and 118. When peripheral device 100 is initially altached lo
`computer 20 through USB interface 102, computer 20 can
`determine that peripheral device 100 is a high-speed USB
`peripheral device because the conductor 104 corresponding
`lo signal D+ is pulled 10 a logical high level, while conductor
`106 which corresponds to signal D- is not.
`FIG. 2B illustrates the connection of a low-speed USB
`peripheral device 120 to computer 20. Some items are
`similar to those s hown in FIG. 2A, and are similarly num(cid:173)
`bered. However, rather than having conductor 104
`(corresponding to signal D+) pulled to a logical high level
`with resistor 114, conductor 106 (which corresponds to
`signal D- ) is pulled to a logical high level with resistor U2 .
`Thus, computer 20 determines that peripheral device 120 is
`a low-speed USB device.
`FIG. 2C illustrates another peripheral device 124 con(cid:173)
`nected to computer 20. Peripheral device U4 is configured
`to communicate with computer 20 through a PS2 interface
`126. PS2 peripheral device 124 communicates with com(cid:173)
`puter 20 over a pair of conductors 104 and 106, which
`correspond to a data signal and a clock signal. Conductors
`104 and 106 are connected to transistors 131 and 133, which
`are configured as open-collector or open-drain switches
`controlled by the microprocessor in peripheral device 124.
`Conductors 104 and 106 are connected lo conductors 108
`and 110 through PS2 connector 128. Conductors 104 and
`106 are pulled to a logical high level at peripheral device 124
`by resistors 130 aod 132 which are typically in a 2 k-10 k 45
`ohm range.
`In PS2 interface 126, conductors 108 and 110 are also
`pulled to a logical high level by resistors 134 and 136, which
`are also typically in a 2 k-10 k ohm range. Conductors 108
`and 110 are also coupled to ground by transistors 138 and 50
`140, which are typically open-drain or open-collector and
`driven by appropriate circuitry in processor 21. It should
`also be noted that transistors 138 and 140 can typically be
`implemented inside processor 21, or discretely.
`With the open-collector configured interface, when a 55
`logical l is written 10 either conductor 108 or 110, the
`conductor is not actively driven high. Instead, it is pulled
`high, to nearly the rail voltage VCC, via the pull-up resistors
`134 and 136. lo this manner, either host processor 21 or
`peripheral device 124 can drive the conductor low without 60
`the concern of the conductor already being actively driven
`high.
`Peripheral device 124 is responsible for providing the
`clock signal over conductors 106 and 110, to host processor
`21, regardless of the direction of data flow over conductors
`104 and 108. Host processor 21 can pull the conductor 110
`carrying the clock signal low by controlling transistor 140
`
`30
`
`TABLE 1
`
`0+/CLK
`
`0-/DA'T
`
`USB
`
`L
`
`L
`
`H
`
`H
`
`L
`
`H
`
`L
`
`H
`
`SEO
`(Single
`Ended 0 )
`or Reset
`J, Idle
`
`K,Xmit
`Resume
`SEl
`
`l/0
`Stnte
`
`0
`
`2
`
`3
`
`PSP-
`
`Host
`Inhibit
`
`Host
`Inhibit
`Host Xmil
`
`Idle,
`
`ZTE/SAMSUNG 1010-0011
`IPR2018-00111
`
`65
`
`

`

`8
`computers were discovered to hold PS2 interface commu(cid:173)
`nication lines in an mhibited state for extensive periods of
`time, even on power-up. This can make it difficult to detect
`and respond to initial communication sequences in a timely
`5 manner. Similarly, where a peripheral device 142 is "hot
`plugged" i nto the host computer, the inhibition of the PS2
`communication by the bost computer can make it difficult
`for the detection system discussed above to make an imme(cid:173)
`diate detection.
`Therefore, the present invention can be implemented
`according to a second embodiment as well. FIG. 5 illustrates
`peripheral device 182 wbich is implemented in accordance
`with a second illustrative embodiment of the present inven(cid:173)
`tion. A number of the items illustrated in FIG. 5 are similar
`to those found in FIG. 3, and are similarly numbered.
`However, in tbe embodiment illustrated in FIG. 5, peripheral
`device 182 includes communication controller 184 which
`not only includes USB interface engine 146 and PS2 com(cid:173)
`munications component 148, but also includes resistor pull(cid:173)
`up control component 186. Control component 186 provides
`an output 188 to a switch 190.
`Io tbe embodiment illustrated in FIG. 5, switcb 190 is
`implemented as a bi-polar transistor 192 which is coupled
`between pull-up resistor 150 and a predetermined voltage
`25 potential (in this case VCC). This provides control compo(cid:173)
`nent 186 with tbe ability to either enable pull-up resistor 150
`by connecting pull-up resistor 150 to VCC, or to disable
`pull-up resistor 150, by effectively discoonectmg pull-up
`resistor 150 from VCC.
`FIG. 6 is a state diagram which better illustrates the
`operation of peripheral device 182 shown in FIG. 5. A
`number of the states are similar to those shown in FIG. 4,
`and are similarly numbered. Therefore, controller 184 first
`begins the initialization routine at state 170. Controller 184
`also waits, after power-up, for a predetermined time period
`in order to accommodate for contact bounce. This is indi(cid:173)
`cated by state 172. After tbe desired delay, controller 184
`enters indeterminate state 200.
`Controller 184 (and specifically pull-up control compo-
`nent 186) then perfom1s a USB attach operation by enabli ng
`pull-up resistor 150. In other words, control component 186
`provides an output to bi-polar transistor 192 which effec(cid:173)
`tively connects pull-up resistor 150 to VCC. It will be noted
`45 that this does not effect PS2 operation since, where a PS2
`interface is provided, adapter 154 is already in place which
`includes its own pull-up resistor 166 on signal line 160.
`Controller 184 then senses the logic level on botb signal
`lines 158 and 160 witb a level detector sucb as that set out
`in co-pending U.S. patent application Ser. No. 09/112,171,
`fi led Jul. 8, 1998 entitled "METHOD AND APPARAfUS
`FOR DETECTING THE TYPE OF INTERFACE TO
`WHICH A PERIPHERAL DEVICE IS CONNECTED",
`wbich is hereby fully incorporated by reference.
`As with the detection routine illustrated in FIG. 4, i(
`controller 184 detects a SEl condition, and that condition
`exists for a predetermined amount of time (such as ll1ree
`milliseconds), controller 184 determines that it bas detected
`a PS2 interface. This is indicated by states 178 and 180.
`However, if an SEl condition is not detected but an SEO
`or K state is detected, controller 184 remains in indetermi(cid:173)
`nate state 200 and simply waits for this condition to change.
`Tbis is because no determination can be made while the
`signal lines 158 and 160 are in tbe SEO or K state.
`If, on tbe otber band, while controller 184 is in indeter(cid:173)
`minate stale 200, it detects a J slate, it moves to state 202 and
`determines whether the J state exists for a predetermined
`
`40
`
`50
`
`FIG. 4 is a state diagram illustrating tbe operation of
`peripheral device 142 shown in FIG. 3 and will be described 10
`with reference to FIG. 3 and Table l. Communication
`controller 144 begins by starting the initialization process, as
`indicated by state 17