Universal Serial Bus Specification Revision 2.0
`
`Table 6-7. USB Electrical, Mechanical, and Environmental Compliance Standards (Continued)
`
`T est Description
`
`Test P rocedure
`
`Performance Requirement
`
`The manufacturer will require its
`thermoplastic resin vendor to
`supply a detailed C of C with each
`resin shipment. The C of C shall
`clearly show the resin's UL listing
`number, lot number, date code,
`etc.
`
`The manufacturer will require its
`thermoplastic resin vendor to
`supply a detailed C of C with each
`resin shipment. The C of C shall
`clearly show the resin's UL listing
`number, lot number, date code,
`etc.
`
`Impedance must be in the range
`specified in Table 7-9 (ZO).
`
`Flammability
`
`Flammability
`
`Cable Impedance
`(Only required for high-/full-speed)
`
`UL 94 V-0
`
`This procedure is to ensure
`thermoplastic resin compliance to
`UL flammability standards.
`
`UL 94 V-0
`
`This procedure is to ensure
`thermoplastic resin compliance to
`UL flammability standards.
`
`The object of this test is to insure
`the signal conductors have the
`proper impedance.
`
`1. Connect the Time Domain
`Reflectometer (TOR) outputs
`to the impedance/delay/skew
`test fixture (Note 1 ). Use
`separate 50 n cables for the
`plus (or true) and minus (or
`complement) outputs. Set the
`TDR head to differential TDR
`mode.
`
`2. Connect the Series "A" plug of
`the cable to be tested to the
`text fixture, leaving the other
`end open-circuited.
`
`3. Define a waveform composed
`of the difference between the
`true and complement
`waveforms, to allow
`measurement of differential
`impedance.
`
`4. Measure the minimum and
`maximum impedances found
`between the connector and the
`open circuited far end of the
`cable.
`
`110
`
`ZTE/SAMSUNG 1008-0138
`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`Table 6-7. USB Electrical, Mechanical, and Environmental Compliance Standards (Cont inued)
`
`Test Description
`
`Test Procedure
`
`Performance Requirement
`
`Signal Pair Attenuation
`(Only required for high-/full-speed)
`
`Refer to Section 7.1.17 for
`frequency range and allowable
`attenuation.
`
`The object of this test is to insure
`that adequate signal strength is
`presented to the receiver to
`maintain a low error rate.
`
`1. Connect the Network Analyzer
`output port (port 1) to the input
`connector on the attenuation
`test fixture (Note 2).
`
`2. Connect the Series "A" plug of
`the cable to be tested to the
`test fixture, leaving the other
`end open-circuited.
`
`3. Calibrate the network analyzer
`and fixture using the
`appropriate calibration
`standards over the desired
`frequency range.
`
`4. Follow the method listed in
`Hewlett Packard Application
`Note 380-2 to measure the
`open-ended response of the
`cable.
`
`5. Short circuit the Series "B" end
`(or bare leads end, if a captive
`cable) and measure the short-
`circuit response.
`
`6. Using the software in H-P App.
`Note 380-2 or equivalent,
`calculate the cable attenuation
`accounting for resonance
`effects in the cable as needed.
`
`Ul
`
`ZTE/SAMSUNG 1008-0139
`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`Table 6-7. USB Electrical, Mechanical, and Environmental Compliance Standa rds (Continued)
`
`Test Description
`
`Test Procedure
`
`Performance Requirement
`
`The purpose of the test is to verify
`the end to end propagation of the
`cable.
`
`High-/full-speed.
`
`See Section 7 .1. 1.1,
`Section 7.1.4, Section 7.1.16, and
`Table 7-9 (TFSCBL).
`
`1. Connect one output of the
`TDR sampling head to the D+
`and D- inputs of the
`Low-speed.
`impedance/delay/skew test
`fixture (Note 1 ). Use one 50 n See Section 7.1.1 .2,
`cable for each signal and set
`Section 7.1.16, and Table 7-9
`the TDR head to differential
`(TLSCBL).
`TDR mode.
`
`Propagation Delay
`
`2. Connect the cable to be tested
`to the test fixture. If
`detachable, plug both
`connectors in to the matching
`fixture connectors. If captive,
`plug the series "A" plug into
`the matching fixture connector
`and solder the stripped leads
`on the other end to the test
`fixture.
`
`3. Measure the propagation delay
`of the test fixture by
`connecting a short piece of
`wire across the fixture from
`input to output and recording
`the delay.
`
`4. Remove the short piece of wire
`and remeasure the
`propagation delay. Subtract
`from it the delay of the test
`fixture measured in the
`previous step.
`
`112
`
`ZTE/SAMSUNG 1008-0140
`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`Table 6-7. USB Electrical, Mechanical, and Environmental Compliance Standards (Continued)
`
`Test Description
`
`Test Procedure
`
`Performance Requi rement
`
`This test insures that the signal on
`both the D+ and 0- lines arrive at
`the receiver at the same time.
`
`Propagation skew must meet the
`requirements as listed in
`Section 7 .1.3.
`
`Propagation Delay Skew
`
`1. Connect the TOR to the fixture
`with test sample cable, as in
`the previous section.
`
`2. Measure the difference in
`delay for the two conductors in
`the test cable. Use the TOR
`cursors to find the open-
`circuited end of each
`conductor (where the
`impedance goes infinite) and
`subtract the time difference
`between the two values.
`
`The purpose of this test is to insure See Section 7.1.1.2 and Table 7-7
`the distributed inter-wire
`(CLINUA).
`capacitance is less than the
`lumped capacitance specified by
`the low-speed transmit driver.
`
`Capacitive Load
`
`Only required for low-speed
`
`1. Connect the one lead of the
`Impedance Analyzer to the D+
`pin on the
`impedance/delay/skew fixture
`(Note 1) and the other lead to
`the 0 - pin.
`
`2. Connect the series "A" plug to
`the fixture, with the series "B"
`end leads open-circuited.
`
`3. Set the Impedance Analyzer to
`a frequency of 100 kHz, to
`measure the capacitance.
`
`Note1:
`
`Impedance, propagation delay, and skew test fixture
`This fixture will be used with the TOR for measuring the time domain performance of the cable under test. The
`fixture impedance should be matched to the equipment, typically 50 n. Coaxial connectors should be provided
`on the fixture for connection from the TOR.
`
`Note 2: Attenuation text fixture
`This fixture provides a means of connection from the network analyzer to the Series "A" plug. Since USB
`signals are differential in nature and operate over balanced cable, a transformer or balun (North Hills NH13734
`or equivalent) is ideally used. The transformer converts the unbalanced (also known as single-ended) signal
`from the signal generator which is typically a 50 n output to lhe balanced (also known as differential) and likely
`different impedance loaded presented by the cable. A second transformer or balun should be used on the other
`end of the cable under test to convert the signal back to unbalanced form of the correct impedance to match the
`network analyzer.
`
`113
`
`ZTE/SAMSUNG 1008-0141
`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`6. 7 .1 Applicable Documents
`
`American National Standard/Electronic Industries Association
`
`ANSl/EIA-364-C {12/94) Electrical Connector/Socket Test Procedures
`Including Environmental Classifications
`
`American Standard Test Materials
`
`ASTM-D-4565
`
`ASTM-D-4566
`
`Physical and Environmental Performance P roperties
`of Insulation and Jacket for Telecommunication
`Wire and Cable, Test Standard Method
`
`Electrical Perfonnance Properties oflnsulation and
`Jacket for Telecommunication Wire and Cable, Test
`Standard Method
`
`Underwriters' Laboratory, Inc.
`
`UL STD-94
`
`Test for Flammability of Plastic materials for Parts
`in Devices and Appliances
`
`UL Subject-444
`
`Communication Cables
`
`6.8 USB Grounding
`The shield must be tem1inated to the connector plug for completed assemblies. The shield and chassis are
`bonded together. The user selected grounding scheme for USB devices, and cables must be consistent with
`accepted industry practices and regulatory agency standards for safety and EMJ/ESDIRFI.
`
`6.9 PCB Reference Drawings
`The drawings in Figure 6-12, Figure 6-13, and Figure 6-14 describe typical receptacle PCB interfaces.
`These drawings are included for informational purposes only.
`
`114
`
`ZTE/SAMSUNG 1008-0142
`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`6
`
`s
`
`3
`
`Reference Drawing Only
`
`H
`
`G
`
`F
`
`r - 13.1 REF__,
`
`lc
`2~
`14.3 REF L ~ ~
`
`j.--15.0 REF--1
`
`f:-12.5 + 0.10_,
`
`11--11 .1;t0.10-J1
`
`R 0.64 :t 0.13 Typical (2)
`
`e r 9.0 tEF
`"Tl
`
`H
`
`G
`
`e
`
`0
`
`c
`
`Thermoplastic Insulator UL 94-VO
`1.0 .:t 0.05 Wide - Selectively Plated Contact (4)
`
`NOTES:
`
`1. Critical Dimensions are TOLERANCED
`and should not be deviated.
`
`2. Dimensions that are labeled REF are
`typical dimensions and may vary from
`manufacturer to manufacturer.
`
`3. All dimensions are in millimeters (mm) unless
`otherwise noted.
`
`e
`
`Single Pin-Type
`
`2.50 :t o.o5 -i..J l..i-2.so + o.o5
`2.00 + 0.05~ .
`r·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·-·- ·-·---·-1
`!
`l00.92;t0.10(4}~
`.
`i
`!
`7.00 + 0.10
`j
`!
`
`2.00_!0.10
`
`I
`
`!
`!
`I
`i
`
`- -
`2.71;!:0.10
`
`I
`
`-
`
`:
`
`.
`
`.
`
`I
`
`I
`I
`
`!
`i
`i
`i
`.
`
`f
`
`·-'--
`:
`
`~
`
`D
`
`C
`
`B
`
`A
`
`i n- -$-$--$--
`. ·4:
`r-
`
`!
`!
`!
`I
`
`13.14 ;t 0.10
`
`0 2.30 .! 0.10 (2)
`~.-~~~~~~~-~~<:_U~t-~~~!.~ -~~-~~-~~~O~~-·-!
`
`Series "A" Receptacle
`REV c
`
`DRAWlNG NUMBER
`N/A
`SHEET
`
`1 of 1
`
`SIZE
`A
`SCALE:
`
`6
`
`Figure 6-12. Single Pin-type Series "A" Receptacle
`
`A
`
`115
`
`ZTE/SAMSUNG 1008-0143
`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`8
`
`6
`
`4
`
`3
`
`2
`
`IC:])
`
`@
`
`0
`
`Ea
`
`~
`
`~
`
`- -
`
`1
`
`15.60 R
`
`14.70 ± 0.10
`
`- ,_
`
`.
`
`H
`
`G
`
`13.78 :!: 0.10
`
`F
`
`!
`I E
`j
`
`I
`'
`-~·
`
`,
`
`2.50±0.10
`
`.
`
`·- I>·
`
`2.62±0.0S_Q..
`
`I i
`!
`!
`-·-·r-·-·t·-0-0~0-.. 5.68±0.10'
`! _l_!
`'
`
`10.28 ± 0.20
`
`i;~~::::.~) r r1·~1~ r:::::::-:
`r -.q;·--0--·0 ·-0 --0 -·· \::ti---. i
`' 1 02.3±0.10(4)
`i
`
`~,,.:~, 5.70REF
`
`12.50:!;0.10
`
`dJ
`
`I
`f . -16 .95 REF
`
`I_ ~11 .10REF i
`r--10·3
`i
`
`-- Connector Front Edge
`Printed Circuit Board (PCB) Layout
`- · -·-·- · - · - · - · - · - · - · - · - · - · - · - · - · - ·-· - ·)
`
`i
`
`c
`
`H
`
`G
`
`E
`
`D
`
`c
`
`NOTES:
`
`B
`
`1. Critical Dimensions are TOLERANCED
`and should not be deviated.
`
`2. Dimensions that are labeled REF are
`typical dimensions and may vary from
`manufacturer to manufacturer.
`
`A 3. All dimensions are in millimeters (mm)
`unless otherwise noted.
`
`6
`
`5
`
`Reference Drawing Only
`
`B
`
`Dual Pin-Type
`
`Series "A" Receptacle
`A
`l---------+~s1z=e~~M=Te~-~o=AA-~-NG~~-M~B=ER~........,.=ev,.,....f
`N/A
`A
`2198
`C
`SCALE: NIA
`SHEET 1 of 1
`3
`1
`
`Figure 6-13. Dual Pin-type Series" A" Receptacle
`
`116
`
`ZTE/SAMSUNG 1008-0144
`IPR2018-00111
`
`

`

`H
`
`G
`
`F
`
`E
`
`D
`
`c
`
`B
`
`L10.30 REF----f
`
`2.71;!:.0.10
`
`I
`1-----16.00 REF~
`
`Universal Serial Bus Specification Revision 2.0
`
`7
`
`6
`
`5
`
`3
`
`1.0 ;t 0.05 Wide· Selectively Plated Contacts (4)
`
`Thermoplastic Insulator UL 94-VO
`
`1 778'0.10
`11 .50 REF I T
`~n
`
`2.71:!:.0.10~3.01:!:.0.10
`2.00 + 0.10
`-
`
`4.71 ;!:.0.10
`
`3.50 REF
`
`8.45 :!:. 0.10
`
`2.50 :!:. 0.10
`
`.
`
`.
`
`12.04 :!:. 0.10
`
`2.50 :!:. 0. 10-+---~~
`4.77;!:.0.10--1---
`
`12.00 REF
`
`1 ~ ·-·-·-·-·-·- ·-·-·- ·-· -·-·- ·-·-·­
`\ l
`
`! 0.10
`2.001=
`
`.
`
`·--·-··-·-·-~-·-· ~--·-·
`I
`-i--·-·--·$-·-
`-·-
`;
`i
`
`-8-·--·-·-·--'·--·--· -·
`
`!
`
`H
`
`G
`
`F
`
`E
`
`D
`
`c
`
`NOTES:
`
`1. Critical Dimensions are TOLERANCED
`and should not be deviated.
`
`a
`
`2. Dimensions that are labeled REF are
`typical dimensions and may vary from
`manufacturer to manufacturer.
`
`A 3. All dimensions are in millimeters (mm)
`unless otherwise noted.
`
`8
`
`6
`
`0 0.92 :!:. 0.1 (4)
`
`0 2.30 :!:. 0.1 (2)
`
`.
`1 Printed Circuit Board (PCB) Layout
`.
`- -- ·- -- -- ·-· - - - ·-·- ---- ------·--~
`Reference Drawing Only
`
`Single Pin-Type
`
`Series "B" Receptacle
`1--------1-~--~----------l A
`SIZE
`DRAWING NUM3at
`REV
`N/A
`C
`A
`2/98
`SHEET 1of1
`SCALE:
`
`Figure 6-14. Single Pin-type Series "B" Receptacle
`
`117
`
`ZTE/SAMSUNG 1008-0145
`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`118
`
`ZTE/SAMSUNG 1008-0146
`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`Chapter 7
`Electrical
`
`This chapter describes the electrical specification for the USB. It contains signaling, power distribution, and
`physical layer specifications. This specification does not address regulatory compliance. It is the responsibility
`of product designers to make sure that their designs comply with all applicable regulatory requirements.
`
`The USB 2.0 specification requires hubs to support high-speed mode. USB 2.0 devices are not required to
`support high-speed mode. A high-speed capable upstream facing transceiver must not support low-speed
`signaling mode. A USB 2.0 downstream facing transceiver must support high-speed, full-speed, and low-speed
`modes.
`
`To assure reliable operation at high-speed data rates, this specification requires the use of cables that conform to
`all current cable specifications.
`
`In this chapter, there are numerous references to strings of J's and K's, or to strings of l ' s and O's. In each of
`these instances, the leftmost symbol is transmitted/received first, and the rightmost is transmitted/received last.
`
`7.1 Signaling
`The signaling specification for the USB is described in the following subsections.
`
`Overview of High-speed Signaling
`
`A high-speed USB connection is made through a shielded, twisted pair cable that conforms to all current USB
`cable specifications.
`
`119
`
`ZTE/SAMSUNG 1008-0147
`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`----,
`Rpu_Enable - -- --
`HS Current Source Enable - -----------1 '-~------.
`HS Drive -Enable ------------1
`-
`HS_Data_Driver_lnput
`A:>-----+---+-~
`
`+3.3V
`
`High Spted Current Oriver
`
`LS/FS Oriver
`
`Rs
`
`LS/FS_ Data_ Driver_ lnput - - - - - - - - - :0:-.,,... ,,.. •• -.......
`Assert_Single_Ended_Zero - - - - - - -As- ,.-05-eo---<
`FS_ Edge_Mode_Sel ---------~
`LS/FS_Driver_Output_Enable - - - - - - - - - - - '
`
`Note; The Ftpu pulklp teslstor. #nd
`the c#cultry re.quired lo eonab1e and
`dlsabh! it, art ofiy reqvlrec In
`upstream tacftg ttansceivefs
`
`I l
`
`Squelch - -- - - - - - - - ---<..
`Transmiuion Etwt>k»pe Oetettot
`
`LS/FS_ Differentiat_Receiver_Oulpul +------<
`
`LSIFS Ddft11nlitl Oata Rec.civcr
`
`HS_Disconnect
`
`L
`
`Data+
`
`Data-
`
`SE_Data+_Receiver_Oulput +--------------<... t----;
`SE_ Data._Receiver_Output +-------------<:.... i----t---;
`
`Single Endtd Rec«Vers
`
`!'k)te: The Rpd teslstors to ground
`arc only req\lifcd in downsllum
`tacing trans.celvus
`
`Rpd
`
`Rpd
`
`Figure 7-1. Example High-speed Capable Transceiver Circuit
`
`Figure 7-1 depicts an example implementation which largely utilizes USB I. I transceiver elements and adds the
`new elements required for high-speed operation.
`
`High-speed operation supports signaling at 480 Mb/s. To achieve reliable signaling at this rate, the cable is
`terminated at each end with a resistance from each wire to ground. The value of this resistance (on each wire) is
`nominally set to 1/2 the specified differential impedance of the cable, or 45 n. This presents a differential
`termination of90 n.
`For a link operating in high-speed mode, the high-speed idle state occurs when the transceivers at both ends of
`the cable present high-speed terminations to ground, and when neither transceiver drives signaling current into
`the D+ or D- lines. This state is achieved by using the low-/full-speed driver to assert a single ended zero, and to
`closely control the combined total of the intrinsic driver output impedance and the Rs resistance (to 45 n,
`nominal). The recommended practice is to make the intrinsic driver impedance as low as possible, and to Jet Rs
`contribute as much of the 45 n as possible. This will generally lead to the best termination accuracy with the
`least parasitic loading.
`
`In order to transmit in high-speed mode, a transceiver activates an internal current source which is derived from
`its positive supply voltage and directs this current into one of the two data lines via a high speed current steering
`switch. In this way, the transceiver generates the high-speed J or K state on the cable.
`
`The dynamic switching of this current into the D+ or D- line follows the same NRZI data encoding scheme used
`in low-speed or full-speed operation and also in the bit stuffing behavior. To signal a J, the current is directed
`into the D+ line, and to signal a K, the current is directed into the D- line. The SYNC field and the EOP
`delimiters have been modified for high-speed mode.
`
`120
`
`ZTE/SAMSUNG 1008-0148
`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`The magnitude of the current source and the value of the termination resistors are controlled to specified
`tolerances, and together they determine the actual voltage drive levels. The DC resistance from D+ or D- to the
`device ground is required to be 45 Q ±10% when measured without a load, and the differential output voltage
`measured across the lines (in either the J or K state) must be ±400 mV ±10% when D+ and D- are terminated
`with precision 45 Q resistors to ground.
`
`The differential voltage developed across the lines is used for three purposes:
`
`• A differential receiver at the receiving end of the cable receives the differential data signal.
`
`• A differential envelope detector at the receiving end of the cable determines when the link is in the Squelch
`state. A receiver uses squelch detection as indication that the signal at its connector is not valid.
`
`•
`
`In the case of a downstream facing hub transceiver, a differential envelope detector monitors whether the
`signal at its connector is in the high-speed state. A downstream facing transceiver operating in high-speed
`mode is required to test for this state at a particular point in time when it is transmitting a SOF packet, as
`described in Section 7.1.7.3. This is used to detect device disconnection. Jn the absence of the far end
`terminations, the differential voltage will nominally double (as compared to when a high-speed device is
`present) when a high-speed J or Kare continuously driven for a period exceeding the round-trip delay for
`the cable and board-traces between the two transceivers.
`
`USB 2.0 requires that a downstream facing transceiver must be able to operate in low-speed, full-speed, and
`high-speed signaling modes. An upstream facing high-speed capable transceiver must not operate in low-speed
`signaling mode, but must be able to operate in full-speed signaling mode. Therefore, a 1.5 kQ pull-up on the D(cid:173)
`line is not allowed for a high-speed capable device, since a high-speed capable transceiver must never signal
`low-speed operation to the hub port to which it is attached.
`
`Table 7-1 describes the required functional elements of a high-speed capable transceiver, using the diagram
`shown in Figure 7-1 as an example.
`
`121
`
`ZTE/SAMSUNG 1008-0149
`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`Table 7-1. Description of Functional Elements in the Example Shown in Figure 7-1
`
`Element
`
`Low-/full-speed Driver
`
`Description
`
`The low-/full-speed driver is used for low-speed and full-speed transmission. It
`is required to meet all specifications called out in USB 1.1 for low-speed and full(cid:173)
`speed operation, with one exception. The exception is that in high-speed
`capable transceivers, the impedance of each output, including the contribution of
`Rs, must be 45 n ±10%.
`
`The line terminations for high-speed operation are created by having this driver
`drive D+ and D- to ground. (This is equivalent to driving SEO in the full-speed or
`low-speed mode.) Because of the output impedance requirement described
`above, this provides a well-controlled high-speed termination on each data line
`to ground. This is equivalent to a 90 n differential termination.
`
`Low-/full-speed Differential
`Receiver
`
`The low-/full-speed differential receiver is used for receiving low-speed and full(cid:173)
`speed data.
`
`Single Ended Receivers
`
`The single ended receivers are used for low-speed and full-speed signaling.
`
`High-speed Current Driver
`
`The high-speed current driver is used for high-speed data transmission. A
`current source derived from a positive supply is switched into either the D+ or D(cid:173)
`lines to signal a J or a K, respectively. The nominal value of the current source
`is 17.78 mA. When this current is applied to a data line with a 45 n termination
`to ground at each end, the nominal high level voltage (VHSOH) is +400 mV. The
`nominal differential high-speed voltage (D+ - D-) is thus 400 mV for a J and
`-400 mV for a K.
`
`The current source must comply with the Transmit Eye Pattern Templates
`specified in Section 7 .1.2.2, starting with the first symbol of a packet. One
`means of achieving this is to leave the current source on continuously when a
`transceiver is operating in high-speed mode. If this approach is used, the
`current can be directed to the port ground when the transceiver is not
`transmitting (the example design in Figure 7-1 shows a control line called
`HS_Current_Source_Enable to turn the current on, and another called
`HS_Drive_Enable to direct the current into the data lines.) The penalty of this
`approach is the 17. 78 mA of standing current for every such enabled transceiver
`in the system.
`
`The preferred design is to fully turn the current source off when the transceiver
`is not transmitting.
`
`High-speed Differential Data
`Receiver
`
`The high-speed differential data receiver is used to receive high-speed data. It
`is left to transceiver designers to choose between incorporating separate high(cid:173)
`speed and low-/full-speed receivers, as shown in Figure 7-1, or combining both
`functions into a single receiver.
`
`122
`
`ZTE/SAMSUNG 1008-0150
`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`Table 7-1. Description of Functional Elements in the Example Shown in Figure 7-1 (Continued)
`
`Transmission Envelope
`Detector
`
`Disconnection Envelope
`Detector
`
`Pull-up Resistor (RPU)
`
`This envelope detector is used to indicate that data is invalid when the
`amplitude of the differential signal at a receiver's inputs falls below the squelch
`threshold (VHssa). It must indicate Squelch when the signal drops below
`100 mV differential amplitude, and it must indicate that the line is not in the
`Squelch state when the signal exceeds 150 mV differential amplitude. The
`response time of the detector must be fast enough to allow a receiver to detect
`data transmission, to achieve Dll lock, and to detect the end of the SYNC field
`within 12 bit times, the minimum number of SYNC bits that a receiver is
`guaranteed to see. This envelope detector must incorporate a filtering
`mechanism that prevents indication of squelch during the longest differential
`data transitions allowed by the receiver eye pattern specifications.
`
`This envelope detector is required in downstream facing ports to detect the high-
`speed Disconnect state on the line (VHsosc). Disconnection must be indicated
`when the amplitude of the differential signal at the downstream facing driver's
`connector ~625 mV, and it must not be indicated when the signal amplitude is
`s525 mV. The output of this detector is sampled at a specific time during the
`transmission of the high-speed SOF EOP, as described in Section 7.1 .7.3.
`
`This resistor is required only in upstream facing transceivers and is used to
`indicate signaling speed capability. A high-speed capable device is required to
`initially attach as a full-speed device and must transition to high-speed as
`described in this specification. Once operating in high-speed, the 1.5 kn
`resistor must be electrically removed from the circuit. In Figure 7-1, a control
`line called RPu_Enable is indicated for this purpose. The preferred embodiment
`is to attach rn;;itched switching devices to both the D+ and D- lines so as to keep
`the lines' parasitic loading balanced, even though a pull-up resistor must never
`be used on the D- line of an upstream facing high-speed capable transceiver.
`When connected, this pull-up must meet all the specifications called out for full-
`speed operation.
`
`Pull-down Resistors (RPo)
`
`These resistors are required only in downstream facing transceivers and must
`conform to the same specifications called out for low-speed and full-speed
`operation.
`
`7 .1.1 USB Driver Characteristics
`The USB uses a differential output driver to drive the USB data signal onto the USB cable.
`
`For low-speed and full-speed operation, the static output swing of the driver in its low state must be below VoL
`(max) of0.3 V with a 1.5 kQ load to 3.6 V, and in its high state must be above the VoH (min) of2.8 V with a
`15 kQ load to ground as listed in Table 7-7. Full-speed drivers have more stringent requirements, as described
`in Section 7 .1.1.1 . The output swings between the differential high and low state must be well-balanced to
`minimize signal skew. Slew rate control on the driver is required to minimize the radiated noise and cross talk.
`The driver's outputs must support three-state operation to achieve bi-directional half-duplex operation.
`
`Low-speed and full-speed USB drivers must never "intentionally" generate an SE I on the bus. SE 1 is a state in
`which both the D+ and D- lines are at a voltage above VosE1 (min), which is 0.8 V.
`
`High-speed drivers use substantially different signaling levels, as described in Section 7.1.1.3.
`
`USB ports must be capable of withstanding continuous exposure to the waveforms shown in Figure 7-2 while in
`any drive state. These waveforms are applied directly into each USB data pin from a voltage source with an
`
`123
`
`ZTE/SAMSUNG 1008-0151
`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`output impedance of 39 Q. The open-circuit voltage of the source shown in Figure 7-2 is based on the expected
`worst-case overshoot and undershoot.
`
`AC Stress Evaluation Setup
`
`D+ or D- pin
`on USB connector
`nearest device
`
`D~~;~, j~-
`RsRc = 39Q ±2% r
`
`The signal produced by the voltage generator may be
`distorted when observed at the data pin due to Input
`protection devices possibly incorporated In the USB
`device..
`
`4.6V
`
`4-20ns
`
`1.. .... -~--- -1.0V
`166.7ns
`(6MHz)
`
`Figure 7-2. Maximum Input Waveforms for USB Signaling
`
`Short Circuit Withstand
`
`A USB transceiver is required to withstand a continuous short circuit ofD+ and/or D- to VBUS, GND, other data
`line, or the cable shield at the connector, for a minimum of24 hours without degradation. It is recommended
`that transceivers be designed so as to withstand such short circuits indefinitely. The device must not be damaged
`under this short circuit condition when transmitting 50% of the time and receiving 50% of the time (in all
`supported speeds). The transmit phase consists of a symmetrical signal that toggles between drive high and
`drive low. This requirement must be met for max value ofVBUS (5.25 V).
`
`It is recommended that these AC and short circuit stresses be used as qualification criteria against which the
`long-term reliability of each device is evaluated.
`
`7.1.1.1 Full-speed (12 Mb/s) Driver Characteristics
`A full-speed USB connection is made through a shielded, twisted pair cable with a differential characteristic
`impedance (Zo) of90 Q ± 15%, a common mode impedance (ZCM) of30 Q ±30%, and a maximum one-way
`delay (TFSCOL) of 26 ns. When the full-speed driver is not part of a high-speed capable transceiver, the
`impedance of each of the drivers (ZoRv) must be between 28 Q and 44 Q , i.e., within the gray area in Figure 7-4.
`When the full-speed driver is part of a high-speed capable transceiver, the impedance of each of the drivers
`(ZHSDRV) must be between 40.5 Q and 49.5 Q, i.e., within the gray area in Figure 7-5.
`
`For a CMOS implementation, the driver impedance will typically be realized by a CMOS driver with an
`impedance significantly less than this resistance with a discrete series resistor making up the balance as shown in
`Figure 7-3. The series resistor Rs is included in the buffer impedance requirement shown in Figure 7-4 and
`Figure 7-5. In the rest of the chapter, references to the buffer assume a buffer with the series impedance unless
`stated otherwise.
`
`124
`
`ZTE/SAMSUNG 1008-0152
`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`TxD+
`
`OE
`
`TxD-
`
`Buffer Output Imped. (ZeuF)
`/
`Rs
`~Identical
`
`D+
`
`(28Q to 44Q Equiv. Imped.)
`
`CMOS
`/Buffers
`
`D-
`
`(28Q to 44Q Equiv. Imped.)
`
`Rs
`
`Figure 7-3. Example Full-speed CMOS Driver Circuit (non High-speed capable)
`
`Full-speed Buffers in Transceivers Which are Not High-speed Capable
`
`The buffer impedance must be measured for driving high as well as driving low. Figure 7-4 shows the
`composite VII characteristics for the full-speed drivers with included series damping resistor (Rs). The
`characteristics are normalized to the steady-state, unloaded output swing of the driver. The normalized driver
`characteristics are found by dividing the measured voltages and currents by the actual swing of the driver under
`test. The normalized V/I curve for the driver must fall entirely inside the shaded region. The V/I region is
`bounded by the minimum driver impedance above and the maximum driver impedance below. The minimum
`drive region is intersected by a constant current region of l6.1VOHI mA when driving low and -16.lVOHI mA
`when driving high. Jn the special case of a full-speed driver which is driving low, and which is part of a high(cid:173)
`speed capable transceiver, the low drive region is intersected by a constant current region of22.0 mA. This is
`the minimum current drive level necessary to ensure that the waveform at the receiver crosses the opposite
`single-ended switching level on the first reflection.
`
`When testing, the current into or out of the device need not exceed ±10.71 *YOH mA and the voltage applied to
`D+/D- need not exceed 0.3*VoH for the drive low case and need not drop below 0.7*VOH for the drive high
`case.
`
`Full-speed Buffers in High-speed Capable Transceivers
`
`Figure 7-5 shows the V /I characteristics for a Full-speed buffer which is part of a high-speed capable
`transceiver. The output impedance, ZMsoRv (including the contribution of Rs), is required to be between 40.5 Q
`and 49.5 Q. Additionally, the output voltage must be within l Om V of ground when no current is flowing in or
`out of the pin (VHSTERM).
`
`125
`
`ZTE/SAMSUNG 1008-0153
`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`drive low
`
`lour
`(mA)
`
`Slope = 1/28Q
`~
`10.71 * IVoHI ___ T_e~t.bi!!l!! __
`
`6.1 * IVoHI
`
`I
`
`I
`
`2.32 ~ :
`
`Slope= 1/44Q
`
`0
`
`I
`
`:
`I
`
`0
`
`0.3V
`
`0.27*VoH
`
`0.3*VoH
`
`Vour (Volts)
`
`drive high
`
`Slope= 1/44Q-------..
`
`-6.1*1VoHI
`
`-10.71 * IVoHI
`
`Test Limit
`
`Slope = 1/28Q
`
`lour
`(mA)
`
`0
`
`Vour (Volts)
`
`0.7*VoH 0.73*VoH
`
`VoH
`
`Figure 7-4. Full-speed Buffer V/I Characteristics
`
`126
`
`ZTE/SAMSUNG 1008-0154
`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`drive low
`
`lour
`(mA)
`
`10.71 * IVoHI
`
`-
`
`Slope= 1/40.5.Q
`~
`- _ ~§.t!:i!!li! __
`
`22.0
`
`-
`
`-
`
`-
`
`-
`
`-
`
`0
`
`0
`
`1.09V 0.434*VoH Vour (Volts)
`
`VoH
`
`drive high
`
`Slope= 1/49.5~
`
`-10.71 * IVoHI
`
`lour
`(mA)
`
`-------------------------'
`
`Test Limit
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`I
`I
`I
`I
`:slope= 1/40.5.Q
`I
`I
`I
`I
`I
`
`I
`
`0
`
`Vour (Volts)
`
`0.566*VoH 0.698*VoH
`
`Figure 7-5. Full-speed Buffer VII Characteristics for High-speed Capable Transceiver
`
`127
`
`ZTE/SAMSUNG 1008-0155
`IPR2018-00111
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`Figure 7-6 shows the full-speed driver signal waveforms.
`
`Driver
`Signal Pins
`
`One-Way
`Trip Cable
`Delay
`
`VIH {min)-r---t-- - t+ - - --t-- - t i t - - - - - - - - - - - - - t - t - -- - (cid:173)
`Signal pins pass
`Receiver
`Input spec levels
`Signal Pins
`after one cable
`delay
`
`VIL (max)
`
`vss ....:::::::=::i::=::....=======:i:::==-======================--======-
`Figure 7-6. Full-speed Signal Waveforms
`
`7.1.1.2 Low-speed (1.5 Mb/s) Driver Characteristics
`A low-speed device must have a captive cable with the Series A connector on the plug end. The combination of
`the cable and the device must have a single-ended capacitance of no less than 200 pF and no more than 450 pf
`on the D+ or D- lines.
`
`The propagation delay (TLSCBL) of a low-speed cable must be less than 18 ns. This is to ensure that the
`reflection occurs during the first half of the signal rise/fall, which allows the cable to be approximated by a
`lumped capacitance.
`
`Figure 7-7 shows the low-speed driver signal waveforms_
`
`One Bit
`
`VIH {min)-t---t--1--+-----t---1.-1-- - - (cid:173)
`
`Driver
`Signal Pins
`
`Signal pins
`pass output
`spec fevets
`with minimal
`reflections and
`ringing
`
`Figure 7-7. Lo