US006327664B1
`(10) Patent No.:
`a2) United States Patent
`US 6,327,664 B1
`Dell et al.
`(45) Date of Patent:
`Dec. 4, 2001
`
`
`(75)
`
`(54) POWER MANAGEMENT ON A MEMORY
`CARD HAVING A SIGNAL PROCESSING
`ELEMENT
`;
`os
`Inventors: Timothy J. Dell, Colchester; Bruce G.
`Hazelzet; Mark W. Kellogg, both of
`Essex Junction; Christopher P. Miller,
`nec ee
`(US)
`Underhill,
`all
`of VT (US
`International Business Machines
`Corporation, Armonk, NY (US)
`
`(73) Assignee:
`
`(*) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/302,916
`
`Filed:
`Apr. 30, 1999
`(22)
`7
`Int. C1eeeeeeenneeeeemen GO6F 1/32
`(51)
`(52) US. CU. eeeeeeeeneeeeeeees 713/323; 713/320; 713/322
`(58) Field of Search 0... 713/300, 320,
`713/322, 323, 324, 500, 600
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`5,560,024
`5,638,542
`5,689,714
`5,692,202
`5,721,933
`5,727,221
`
`9/1996 Harperet al. cece 713/322
`
`6/1997 Nikjou .........
`s+» 713/323
`11/1997 Moyer seesscssssseee
`we 713/310
`sesssssssscseeen 713/324
`11/1997 Kardach et al.
`2/1998 Walsh et al. eee 713/300
`3/1998 Walsh et al. ween 713/310
`
`5,901,103 *
`5/1999 Harris, IL et al. ceescsssscsseeoe 365/226
`* cited by examiner
`Primary Examiner—Xuan M. Thai
`(74) Attorney, Agent, or Firm—William N. Hogg
`(57)
`ABSTRACT
`An improved memory module and its use in a computer
`system is provided. The module includes a DSPfirst and
`second individually addressable banks of memory chips.
`Thefirst bank is configured to function principally under the
`control of the signal processing element and the second bank
`is configured to function principally under the control of a
`system memorycontroller, although all the portions of each
`of the memory banks is addressable by both the signal
`processing element and the system memorycontroller. Both
`:
`:
`;
`banks of memory chips can be placed in at least one higher
`powerstate and at least one lower powerstate by either the
`system memory controller or the DSP. The activity of each
`bank is sensed while in the higher powerstate, and the
`condition of each of the banksis sensed with respectto any
`activity during operation of the memory bank at the higher
`powerstate. The power state of each bank can be changed
`by either the signal processing element or
`the system
`memory controller responsive to preselected conditions of
`each bank. Each memory bank is returned to a predeter-
`mined known condition when changing from a lower power
`state to a higher powerstate. This is especially important
`when the memory bank assigned to the system controller is
`.
`Placed in another state by the DSP.
`
`14 Claims, 3 Drawing Sheets
`
`8
`2-710
`54a Sb 54c
`_-6
`
`Pramrrr rss
`C
`o
`I
`rom nnPottNTEFEne 7
`
`
`ItI
`
`5
`Naa
`
`
`||
`IRQE-—_<— 22—
`
`1
`1} TE rT
`
`
`I
`1! SYS clock
`—
`26
`1
`I
`1!
`7 CS/RAS/CAS/DQM
`
`
`
`t
`[Tt
`
`| ADOR/CNTLEy aoe ADOR/CNTL
`i
`
`|}|MEMORY} |
`
`
`
`
`BUS} 6 52
`|
`:
`
`MEMORY}
`1
`DATA Hy
`DOD?
`
`
`lt
`BUS! =
`lean nena
`eennene q
`i i.
`i
`i
`4
`28
`26
`I
`1
`I
`
`It
`1
`
`
`
`
`
`9a
`
`
`
`
`
`I
`i
`
`|
`i
`!
`I
`
`
`
`
`
`
`
`2i3 i
`
`I
`a
`>
`>
`a:
`ERE
`LE
`I
`{)
`oO
`oa
`I
`1 30
`!
`I
`64 BITS
`| _ i
`
`|
`|
`i
`
`ee eeee ad
`>——_ 32
`
`IPR2018-00047
`ASUS Computer EX 1004 Page 1
`
`IPR2018-00047
`ASUS Computer EX1004 Page 1
`
`

`

`U.S. Patent
`
`Dec. 4, 2001
`
`Sheet 1 of 3
`
`US 6,327,664 B1
`
`+—-T(49079SAS||iCyLIVIaan0¢rtOuI|IdAceqf|!ADDN*¢=|Lofonnaaa---
`e+f--\aepoeaOl"OGDSg--
`Ii1|I\Wod/svo/svy/SOFAi||apeTTTTLL,
`a0:I'|9¢
`
`LJP|20-00ONS|9|bot7iTLNOoi_4snaf|“9snboonan
`
`tuzil||Sulazi]lazeLIL|[oe92!iPOUCOUT'![efbFBo|!fo5}+>ahae9Sog!IusLbeL+£Lqég0gofLqeL|PEespon-aenentnnneeiel|aryOvHUET|eesna
`TELEaLLi’n”anomom27)
`
`bedsdecile:1II========
`
`
`
`
`—_—_——_—_—_—_——_—_—_—_—_—_———_——_—_——_——_—_——_————_—_—_——_—_—_—_——_——_—_—_—T__——_—_E—_E—_——_——_—S—E_SE—SE_EEESESEESE—_—_ —OT————e—e—v_eoeee=|1;1/9gggg8ggSLId+9!Loe|Woieileds
`
`
`614ze
`
`1I
`
`IPR2018-00047
`ASUS Computer EX 1004 Page 2
`
`IPR2018-00047
`ASUS Computer EX1004 Page 2
`
`
`

`

`U.S. Patent
`
`Dec. 4, 2001
`
`Sheet 2 of 3
`
`US 6,327,664 B1
`
`DSP ACCESS
`TO SYS MEM
`
`DSP DESIRES TO ACCESS
`SYSTEM MEMORY; ASSERTS "WAIT"
`
`
`
`BUS
`INACTIVE FOR
`
`"X” CYCLES
`
`
`
`
`YES
`
`—DEACTIVATE FET SWITCHES
`—STORE CURRENT STATE
`
`EQUIRED
`
`vES ” PRECHARGE”
`
`
`REQUIRE
`BANK ACTIVE
`
`BANK
`
`Fig.2
`
` ?
`
`INITIATE. MEMORY
`ACCESS(ES)
`
`(COLUMN or ROW/COLUMN)
`
`
`
`
`
`DSP
`
`MEMORY ACCESS
`COMPLETE
`
`
`
`?
`
`YES
`
`
`
`
`
`
`—COMPLETE CURRENT OPERATION
`—RESTORE ORIGINAL STATE
`—REACTIVATE FET’s
`—DEASSERT ”WAIT”
`
`
`
`
`IPR2018-00047
`ASUS Computer EX 1004 Page 3
`
`IPR2018-00047
`ASUS Computer EX1004 Page 3
`
`

`

`U.S. Patent
`
`Dec. 4, 2001
`
`Sheet 3 of 3
`
`US 6,327,664 B1
`
`a]DAIODap
`
`JMO
`
`/avau
`
`SLIM
`
`HS3u4gu
`
`GWodn
`34DM
`
`JDeyoaijopap
`
`INDe1DAN{OD
`
`abunyoosd
`
`a1ejduioo
`
`4Mo
`
`B|DAIjODAL
`
`4M
`
`MOO019
`
`QN4dSNS$S
`
`QIDAIVIDII
`
`4x9
`
`abinyood
`
`QW
`
`a}DAILODEp
`AAILOV
`
`ANVE
`
`ASYVHO—3ud
`
`3DAILODE
`
`4yMO
`
`QWS
`
`abupuoeid
`
`QWO
`
`ayuM/poes
`
`YSseujau
`
`GINO
`
`9}d|dwioo
`
`pois
`
`e6i4
`
`
`
`SSHOOVYOSSAOOYdNdO
`
`ANOWSWdSdOL
`
`
`
`
`
`SSS9OVSSAYISSGYOSSS00dd
`
`AYOWSWdSdOL
`
`
`
`
`
`(S3)SSIOOVANOWSNJLVILINI—-
`
`
`
`AYOWSWYOSSAD
`
`
`
`—-WOOSASSAI9OV
`
`—Od
`
`éjlald
`
`
`
`AYOWAWdSdS9YVHOSYd—
`
`IPR2018-00047
`ASUS Computer EX 1004 Page 4
`
`IPR2018-00047
`ASUS Computer EX1004 Page 4
`
`
`
`
`
`
`
`
`
`
`
`
`
`

`

`US 6,327,664 B1
`
`1
`POWER MANAGEMENT ON A MEMORY
`CARD HAVING A SIGNAL PROCESSING
`ELEMENT
`
`FIELD OF THE INVENTION
`
`This invention relates generally to memory cards andtheir
`use in computer systems, and moreparticularly to the use in
`computer systems of memory cards having signal processing
`units on board and having at least one and preferably a
`plurality (e. at least two) of addressable banks of memory
`chips wherein at least a portion of at least one memory bank
`is individually addressable or activatable.
`BACKGROUND ART
`
`Memorycards such as SIMMs and DIMMshaveincreas-
`ingly more memory and more function being addedthereto.
`Particularly,
`it has been proposed that signal processing
`elements such as digital signal processors (DSPs) be pro-
`vided on board the cards to perform various functions
`independently of the system memory controller. These DSPs
`can operate on the memory whenit is not being accessed by
`the system memory controller to perform varioustasks.
`This provides an inexpensive processor specific to each
`card to enhance the operation of the memory card.
`Additionally, as the amount of memory and the functions
`supplied on each card increase the power requirementfor the
`card with large amounts of memory and morefunctions,this
`power requirement can be substantially increased. This is
`especially critical where the system is battery operated
`and/or the heat dissipation capability is limited. While the
`system memory controller generally is programmed to
`reduce the power level of the memory system,
`this is
`generally not a completely satisfactory solution since the
`memory controller operates on all of the memory cards and
`generally does not reduce the power state of the memory
`until the period of non-use amounts to a substantial period
`of time. Also the system memory controller is not normally
`programmed to operate on individual portions of memory
`banks. Thus there is a need for a memory card and system
`for the memory card to operate in a computer to selectively
`and expeditiously reduce power to individual banks of
`memoryor portions thereof when the banks of memory or
`portion thereof are not being accessed by either the system
`memory controller or the DSP.
`
`SUMMARYOF THE INVENTION
`
`According to the present invention an improved memory
`card and its use in a computer system is provided. The card
`includes a signal processing element, preferably a DSP and
`at least one and preferably first and second individually
`addressable banks of memorychips. Thefirst bank of chips
`or optionally a portionofthe first bank of chips is configured
`to function principally under the control of the signal
`processing element and the second bank is configured to
`function principally under the control of a system memory
`controller in the computer system, although all the portions
`of each of the memory banks is addressable by both the
`signal processing element and the system memory control-
`ler. Both banks of memory chips or portion thereof can be
`placed in at least one higher powerstate and at least one
`lower powerstate by either the system memorycontroller or
`the DSP. The activity of each bank of memory and portion
`thereof is sensed while in the higher powerstate, and the
`condition of each of the banks of memoryor portion thereof
`is sensed with respect to any activity during operation of the
`memory bank of memory at the higher power state. The
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`2
`powerstate of each bank of memory can be changed by
`either the signal processing element or the system memory
`controller responsive to preselected conditions of each bank.
`Each memory bank or portion thereof is returned to a
`predetermined known condition when changing from a
`lower powerstate to a higher power state. Preferably this
`condition is that condition, in the case of the memory bank
`underthe control of the system memory controller that it was
`in following the last access by the system memory
`controller, and in the case of the memory bank or portion
`thereof under the control of the DSP, is a given preselected
`condition. This is especially important when the memory
`bank assigned to the system controller is placed in another
`state by the DSP.
`
`DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a high level diagram of a computer system with
`a memorycard according to this invention;
`FIG. 2 is a flow diagram of the DSP access to system
`controller memory;
`FIG. 3 is a flow diagram of the system CPU access to DSP
`controlled memory; and
`FIG. 4 is a state diagram of the operation of the CPU
`memory.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`
`Referring now to the drawings and for the present to FIG.
`1, one embodiment of the present invention is shown as
`embodied in a personal computer 6. A memory module 8
`such as a DIMM or SIMMis provided which includes a
`printed circuit card 10 having a plurality of synchronous
`DRAMs (SDRAMs) 12a-12h constituting a first bank of
`memory chips and 13¢-13/ constituting a second bank of
`memory chips. The synchronous DRAMs 12a-12h and
`13a—13h, are conventional SDRAMs. The SDRAMsof each
`bank 12 and 13 are divided into two sections or portions,
`12a-12d being 12 low, 12¢e-12/ being 12 high, 13a¢—13d
`being 13 low and 13e¢-13/ being 13 high. Each of these
`sections is individually addressable and will be described
`presently.
`The circuit card 10 has a memory bus which includes a
`memory data bus 14 and a memory address/control bus 16.
`A system clock line 18, a wait line 20, an interrupt request
`line 22, and a clock enable (CKE)line 24 are also provided.
`Memory data bus 14, memory 4 address/control bus 16,
`system clock 18, wait line 20, interrupt request line 22, and
`clock enable line 14 are all connected to I/O connectors
`sometimes referred to as pins 26. The I/O connectors 26
`provide an interface to a system memory controller 28,
`whichis a part of the memory subsystem of computer 6. The
`system memory controller 28 also controls a PCI bus 30 (and
`optionally other buses not shown). The PCI bus 30 has
`thereon devices such as a codec 32.
`
`The memory card 10 also has a memorybuscontroller 34
`which is connected to the memory data bus 14, the memory
`address/control bus 16, the system clock 18, the wait line 20,
`the interrupt request line 22 and the clock enable line 24. The
`bus controller 34 is connected to a signal processing element
`36 which in the preferred embodiment is a digital signal
`processor (DSP). A particularly useful DSP is any oneof the
`TMS 320C54X family manufactured by Texas Instruments,
`Inc. This particular DSP family includes an external cache
`memory 38. The bus controller 34 and DSP 36 are inter-
`connected by a chip address bus 40, a chip data bus 42 and
`
`IPR2018-00047
`ASUS Computer EX 1004 Page 5
`
`IPR2018-00047
`ASUS Computer EX1004 Page 5
`
`

`

`US 6,327,664 B1
`
`3
`control lines 44 that pass various control signals between the
`bus controller 34 and the DSP 36. This type of connection
`is well known in the art.
`The memory data bus 14 has FET switches 50 therein. (It
`is to be understood that the memory data bus 14 is comprised
`of multiple lines, one for each bit and there is an FET 50 for
`eachbit line.) The memory data bus 14 maybean 8 bit bus,
`a 16 bit bus, a 32 bit bus, or a 64 bit bus, and indeed any size
`data bus which includes whatever numberof data lines are
`required. Also there are FET switches 52 in the system
`address/control bus 16.
`The system clock line 18 is also connected to the DSP 36
`in the preferred embodiment; however,it is to be understood
`that a separate clock could be provided for the DSP if
`different timing is used on the card from the timing used in
`the CPU. However,
`the preferred embodiment for most
`instances is to use the system clock for clocking the func-
`tions and signals on the memory module. The clock enable
`line 24 has four branches 54a—54d connected to the banks of
`memory chips 12¢—12h and 13a-13/ through FET switches
`56a—-56d to provide individual clock enable signals directly
`to the chips 12a—12h and 13a—13/ without going through
`the bus controller 34 so that the chips can be addressed when
`they are in the lowest power state as will be described
`presently. The line 54a connects with the chips 12 low,the
`line 546 connects with chips 13 low,the line 54¢ connects
`with chips 13 high and line 54d connects with chips 12 high.
`Thus each of these sections memory can be individually
`accessed and controlled.
`
`Many tasks of the DSP are accomplished when the
`memory module is not being addressed for either a read or
`write function or other function by the CPU memory con-
`troller 28. Thus the FETs 50, 52 and 56a—56dare in an open
`position when these tasks are taking place to disconnect the
`memory controller 28 from access to the memory. If
`however, when the CPU wishes to access the memory
`module,
`the FET’s 50, 52, and 56a—56d are closed, the
`memory controller 28 can address the memory module 8 on
`the memory data bus 14 and memoryaddress/control bus 16
`to perform conventional read/write operations from and to
`selected SDRAMs 12a-12h and 13a-13h.
`
`The present invention accommodates several levels of
`reduced power operation for the memory card 8 and pro-
`vides for both the system memory controller 28 or the
`memory bus controller 34 to place the banks of memory
`chips 12a—12h or 13a—13h or sections thereof in one of the
`reduced power levels. Generally speaking, however,
`the
`system memorycontroller conventionally is programmed to
`require a significantly longer period of inactivity before
`placing either of the banks of chips in a reduced power mode
`than the memory buscontroller; and, moreover, the system
`memory controller conventionally is not programmed to
`place individual banks of memoryorsections thereof into a
`reduced power mode, but rather acts on all of the memory
`on the card 8.
`
`JEDEC standards define three different reduced power
`modes for conventional SDRAMs.In the preferred embodi-
`ment of the invention, all three different reduced power
`modes,i.e. 1) clock suspend mode; 2) power down mode;
`and 3) self refresh mode are supported. In the clock suspend
`modethe internal clock onall affected SDRAMSremainsin
`
`the state it was prior to entering the clock suspend mode.
`Only one clock cycle is required to bring the affected
`SDRAMSfrom the clock suspend mode to the active mode
`or from the active mode to the clock suspend mode. The
`clock suspend mode offers the least power saving of these
`three modes.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4
`In the power down modeall of the banks are maintained
`in the precharged condition butall the receivers are deacti-
`vated except for the clock enable. The internal clocks on all
`of the SDRAMSarealso frozen in this mode. The DRAMS
`must be returned to the active state from this mode for
`refresh, and thus this state can last no longer than the
`duration of the interval between refresh cycles before the
`SDRAMSmust be returned to active state for refresh. This
`is an intermediate state of power saving of these three modes
`of reduced power.
`The self refresh mode is used if it is expected that the
`duration of the reduced power requirement will last longer
`than the cycle time of a refresh cycle. In this mode, only the
`clock enable signal is active, with all the other receivers
`being turned off. The SDRAMSperform a self refresh
`function and thus the internal clocks of each of the
`
`SDRAMSare frozen, but are selectively partially activated
`to perform the self refresh function.
`As indicated above either the system memory controller
`28 or the memory bus controller 34 can place either of the
`memory banks of chips 12¢—12h or 13a—13/ in any of the
`power down modes. Additionally, since DSPs typically have
`a narrower bus width than the system bus of memory data
`bus 14,if the DSP is working only on either the high or low
`portion of each bank the other portion can be put into a
`reduced power mode. Hence a clock enable signalis sent to
`each of the high and low portions of each bank of memory
`chips.
`Since both the system memory controller and the DSP
`through the memory bus controller have access to both
`banks of memory chips and both sections thereof and can
`rewrite data and changethe condition of the SDRAM chips,
`it is necessary to accurately and precisely control the con-
`dition of the chips when they are being accessed by either
`the system memorycontroller or the DSP. This is especially
`true of the system memory controller since the system
`memory controller “expects” to find the memory in the
`condition it was in when the system memorycontrollerlast
`completed an access to the memory. If the memory is in a
`condition other than at the completion of the last access by
`the system memory controller, for example because of an
`intervening access by the DSP to place the memory in a
`powered down condition, then a command issued by the
`system memory controller may be invalid for that particular
`condition of the memory which, of course, could have
`serious consequences. Therefore in conjunction with both
`the system memory controller 28 and the memory bus
`controller 34 under the direction of the DSP 36 being able
`to reduce the power level of any bank of memory chips
`12a-12h or 13a-13h, a very rigorous protocol must be
`established for governing access to the banks of memory
`chips; and, just as importantly a protocol governing the
`specific condition of the chips after each access and entering
`a power down modeand before returning accessto either the
`system memory controller 28 or the memory buscontroller
`after a power down modeis required.
`Since both the system memory controller 28 and the DSP
`36 through the memory buscontroller 34 can access both the
`memory banks 12a—12h/ and 13a-13h and the high and low
`sections thereof and put either bank or sections thereof into
`different power down modes,
`it is necessary that certain
`conditions must prevail before either bank can be placed in
`a power down mode; and,alsoit is necessary to restore each
`bank to a predetermined or pre known condition before
`access to that bank can again be granted. Expressed another
`way, since both memory banks 12¢—12h and 13@—13h and/or
`sections thereof are shared between two or more processors
`
`IPR2018-00047
`ASUS Computer EX 1004 Page 6
`
`IPR2018-00047
`ASUS Computer EX1004 Page 6
`
`

`

`US 6,327,664 B1
`
`5
`(i.e. the DSP 36 and the system processor which controls the
`system memory controller 28) a methodology is required
`that ensures that the memory banks 12a—12h and 13a-13h
`and sections thereof are given appropriate commandsat all
`times based on the then current status of the memory.
`In the preferred embodiment,
`the wait
`line must be
`inactive, indicating that the memoryis available for access,
`and this condition is programmed to exist when all of the
`following conditions apply:
`1) both of the memory banks 12a-12/ and 13a—13h arein
`the same condition they were left
`in after the last
`system access. Thus the system will find the memory
`banks in the condition that it “expects” to find them
`based on their condition following the last system
`access. Hence, the system will pick up after its last
`access, and the command will not be an invalid com-
`mand based on the system expecting the condition to be
`different than it is;
`2) the memory banksor portions or sections thereof that
`are principally assigned to the DSPare in the inactive/
`standby (or idle) state—this being the default state
`when not fully powered down;
`3) all of the FET switches are closed to permit access by
`the system memory controller 34 to the banks of
`memory 12a—12h and 13a—13h including through the
`clock enable lines 54a—54d; and
`4) the outputs of the memory bus controller 34 to the
`system bus 14 and 16 are disabled.
`Conversely the wait line will be active, signaling the
`nonavailability of the memory for access by the system
`memory controller 28, if any one or more of the following
`conditions exist:
`
`1). the memory bank or portions thereof assigned to the
`system memory controller are not in the condition it
`wasin following the last access by the system memory
`controller 28 (this condition would occur when the DSP
`36 has initiated access to or changed the powerstate of
`the memory bank assigned to the system memory
`controller 28;
`2) the memory bank or portion thereof assigned to the
`DSPis in a state other than an inactive/standby (idle)
`state;
`3) any of the FET switches are open (inactive) preventing
`signals from the system memory controller 28 from
`accessing the memory banks; or
`4) any of the bus controller 34 outputs to the system bus
`are active.
`Since the memory bus controller 34 monitors the system
`memory controller 28 commands, it knows what commands
`are issued and canreact to them as needed. Either the system
`memory controller 28 or the system bus controller 34 may
`act on one or more portions of memory to put them in a
`reduced power mode. It is up to the memory buscontroller
`34 to monitor the condition ofall of the banks of memory at
`all timesto insure that any commandsissued byit are “legal”
`memory operations for the currentstate.
`FIG. 2 is a flow diagram of the operation of the DSP 36
`access to system memory bank 13a—13h, and FIG. 3 is a
`flow diagram of the operation of the system memory con-
`troller 28 to the DSP memory bank 12@-12h. FIG. 41s a state
`diagram of the operation of the system memory controller
`28. (The state diagram of the operation of the bus controller
`34 under control of the DSP 36 is the same, except that after
`the read/write/refresh operations are complete, the memory
`is always returned to the precharge state and not to bank
`active.)
`
`6
`EXAMPLEI
`
`Memory Module with more than one ‘physical’ memory
`banks(e.g. 12a—12h and 13a—13h), with at least one physi-
`cal bank (e.g. 12a—12h) allocated to the DSP, and the
`remaining physical bank(s) (e.g. 13a—13h) allocated to the
`system.
`This case offers the maximum flexibility to the DSP 36, as
`it has primary control over at least one physical bank of
`memory (e.g. 12a—12h).
`In this case, the system has direct control over one or more
`physical banks, and mayutilize the CKE signal to de-power
`any or all of the system memory. The memory assigned to
`the system would react immediately to this operation, unless
`the memoryis not currently available (e.g. being accessed
`by the DSP). If the memory is not available, the WAIT line
`20 would already be active, and the system would re-issue
`the command once the WAITlineis inactive. If subsequently
`activated by the DSP, the memory would be returned to its
`previous (low power) state once the operation(s) is com-
`pleted.
`The memory uniquely assigned to the DSP would gener-
`ally be under direct DSP control—and maybein anystate
`including a low power mode. When one or more unique
`physical banks are permanently allocated to the DSP, the
`DSP memory will not be directly affected by the system
`CKE operation—since the CKE signals will be sourced by
`the bus controller, not the external system.
`Local CKE control: The physical memory spaceallocated
`to the DSP, is placed in the lowest power mode possible,
`when not in use. (For this example, this is defined as one
`physical bank of memory assigned to the DSP, with any
`remaining physical banks of memory assigned to the
`system.) Accesses to all other physical memory bankson the
`memorycard 8 are still permitted (as long as those banksare
`in the appropriate state), since the bus controller will ensure
`the DSP memoryis not disturbed (CKE held inactive).
`As this physical bank is assigned to the DSP, only a
`limited set of transfers would be expected to this memory
`from the system processor/memory controller. As such, any
`attempted accesses from the system to this memory would
`result in a WAITresponse from the DSP memory—and the
`processor access would be held-off until the DSP memory is
`returned to an accessible state. In this implementation, the
`physical memory bank assigned to the DSP would ALWAYS
`be placed in an ‘Inactive/Standby”state prior to making this
`memoryaccessible to the system During any changein state
`of the DSP memory, the FET switches would be disabled to
`permit the generation and transmissionof‘local’ address and
`commandsignals.
`As such, the DSP memory can be maintained in a low
`powerstate, whenever unneeded, independent of the condi-
`tion (state) of the remaining memory on the assembly.
`EXAMPLEII
`
`Memory Module 8 with one or more physical banks of
`memory, with a portion of the memory (e.g. 12a—12h)
`assigned to the DSP (generally this will be LESS than one
`physical bank).
`Since the ‘DSP’ memoryis not physically separate from
`the ‘system’ memory on this assembly (as a unique physical
`bank), unique control of the power level of the memory
`assigned to the DSPis not possible. In this case, the DSP,
`through the memory bus controller 34, monitors busactivity
`to the memory, and can reduce the power level of the
`memory on the assembly, on a per-bank basis, based on the
`
`10
`
`15
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`IPR2018-00047
`ASUS Computer EX 1004 Page 7
`
`IPR2018-00047
`ASUS Computer EX1004 Page 7
`
`

`

`US 6,327,664 B1
`
`7
`system and DSP36 activity to that memory space. (This can
`also be done in Example I above). As in ExampleI, the DSP
`36 would maintain control over CKE 24 (or similar power
`management signals) at
`the memory devices when FET
`switches 56a—56dare turned off, and would return a ‘wait’
`response if the accessed memoryis not immediately avail-
`able. As before, during the change in memorystates, the FET
`switches 56a—56d would be disabled (turned off) to prevent
`bus contention.
`
`5
`
`In a system containing memoryofthis type, the operating
`system preferably resides in an address range not included
`on the DSP Memory Module. By so-doing, the probability
`that
`the local memory will be in an inactive state is
`increased—thereby maximizing the benefits of this inven-
`tion.
`
`Accordingly, the preferred embodiments of the present
`invention have been described. With the foregoing descrip-
`tion in mind, however, it is understood that this description
`is made only by way of example, that the invention is not
`limited to the particular embodiments described herein, and
`that various rearrangements, modifications, and substitu-
`tions may be implemented without departing from the true
`spirit of the invention as hereinafter claimed.
`Whatis claimedis:
`
`1. A method of controlling the power utilized by a
`memory card in a computer system which includes a signal
`processing element on said card and at least one bank of
`memorychips, and wherein said at least one bankhasatleast
`a first portion thereof configured to principally function
`under the control of the signal processing element and a
`second portion configured to function principally under the
`control of a system memory controller in said computer
`system, and wherein eachofsaid first and second portion of
`memory is addressable by both the signal processing ele-
`ment and said system memory controller, and wherein each
`portion of memory can be placed in at least a higher power
`state and a lower powerstate by either said system memory
`controller or said signal processing element, comprising the
`steps of;
`changing the power state of both said first portion of
`memory chips and said second portion of memory by
`either said signal processing element or said system
`controller responsive to preselected conditions of each
`portion,
`sensing the activity of each portion of memory chips
`before the power state is changed from said higher
`powerstate to said lower powerstate;
`sensing the condition of each of said portion of memory
`during any operation with respect to said memory bank;
`and
`
`always returning each memoryportion to a predetermined
`known condition when changing from said lower
`powerstate to said higher powerstate.
`2. The invention as defined in claim 1 wherein there are
`
`at least first and second memory banks, and wherein said
`first memory bank constitutes said first portion of memory
`and said second memory bank constitutes said second
`memory portion.
`3. The invention as defined in claim 2 wherein the second
`
`bank of memory chips is restored to the condition at the
`completion of the last access thereto by said system memory
`controller when said second bank of memory chips is
`accessed by the signal processing element.
`4. The invention as defined in claim 2 wherein saidfirst
`
`bank of memory chips is placed in a condition of inactive/
`standby before access thereto by said system memory con-
`troller.
`
`30
`
`35
`
`45
`
`50
`
`55
`
`60
`
`65
`
`8
`5. The invention as defined in claim 1 wherein a wait
`signal is delivered to said system memorycontroller if the
`requested bank of memory chips is unavailable.
`6. The invention as defined in claim 5 wherein said wait
`signal is generated if any of the following conditions exist:
`a) said second bank of memory chips is not
`in the
`condition of last access by the system memory con-
`troller;
`b) said first bank of memory chips is not in an inactive/
`standby condition;
`c) the system memory controller does not have physical
`access to either of said banks of memory; or
`d) either of the banks of memory chips do not have
`physical access to the system controller.
`7. The invention as defined in claim 1 wherein an interrupt
`request signal is generated when the signal processor needs
`to be serviced by said system memory controller.
`8. The invention as defined in claim 1 wherein there are
`least
`three reduced power levels including a highest
`at
`reduced power level which is a clock freeze mode, an
`intermediate reduced power level which is an inactive/
`standby mode, and a lowest reduced power level whichis a
`self refresh mode.
`
`9. In combination, a computer system including a system
`memory controller which generates clock enable signals,
`and a memory module, said module comprising a signal
`processing element, at least one bank of memory chips,
`wherein said at least one bank hasat least a first portion
`thereof configured to principally function under the control
`of the signal processing element and a second portion
`configured to function principally under the control of a
`system memorycontroller in said computer system, each of
`said first and second portion of memory being addressable
`by both the signal processing element and said system
`memorycontroller, wherein each portion of memory can be
`placed in at least a higher power state and a lower power
`state by either said system memory controller or said signal
`processing element,
`logic circuitry to change the powerstate of both said first
`portion of memory chips and said second portion of
`memory by either said signal processing element or
`said system controller responsive to preselected con-
`ditions of each portion including circuitry to deliver
`clock enable signals selectively responsive directly to
`said system controller or responsive to the signal pro-
`cessing element,
`circuitry to sense the activity of each portion of memory
`chips before the power state is changed from said
`higher powerstate to said lower powerstate;
`circuitry to sense the condition of each of said portion of
`memory during any operation with respect
`to said
`memory bank; and
`circuitry to always return each memory portion to a
`predetermined known condition when changing from
`said lower powerstate to said higher powerstate.
`10. The invention as defined in claim 9 wherein there are
`
`at least first and second memory banks, and wherein said
`first memory bank constitutes said first portion of memory
`and said second memory bank constitutes said second
`memoryportion.
`11. The invention as defined in claim 9 including logic
`circuitry to provide a wait signal to said system memory
`controller if the requested bank of memory chipsis unavail-
`able.
`12. The invention as defined in claim 11 wherein said wait
`
`signal