`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________________________
`
`
`SAMSUNG ELECTRONICS CO, LTD.,
`Petitioner
`
`v.
`
`JAMES B. GOODMAN,
`Patent Owner.
`
`__________________________
`
`U.S. Patent No. 6,243,315
`__________________________
`
`
`EXPERT DECLARATION OF DR. ANDREW WOLFE
`IN SUPPORT OF SAMSUNG ELECTRONICS CO, LTD.’S, PETITION
`FOR INTER PARTES REVIEW OF U.S. PATENT NO. 6,243,315
`
`
`
`Samsung Ex. 1002
`
`

`

`U.S. Patent No. 6,243,315
`Declaration of Dr. Andrew Wolfe
`
`
`TABLE OF CONTENTS
`
`INTRODUCTION .......................................................................................... 1
`I.
`EXPERIENCE AND QUALIFICATIONS .................................................... 1
`II.
`III. RELEVANT LEGAL STANDARDS ............................................................ 7
`IV. LEVEL OF ORDINARY SKILL IN THE ART .......................................... 11
`V.
`TECHNICAL BACKGROUND .................................................................. 12
`A. DRAM, Self Refresh Mode, and Backup Battery .............................. 12
`B. Memory Controllers and Address and Control Lines ........................ 14
`VI. OVERVIEW OF THE INVALIDATING PRIOR ART .............................. 16
`A. U.S. Patent No. 6,327,664 (“Dell”) .................................................... 16
`B. U.S. Patent No. 6,172,928 (“Ooishi”) ................................................ 17
`C. U.S. Patent No. 6,144,219 (“Palaniswami”) ...................................... 18
`D. U.S. Patent No. 5,590,082 (“Abe”) .................................................... 19
`E.
`JESD 21-C, Configurations for Solid State Memories, Release
`X (“JESD 21-C”) ................................................................................ 19
`VII. CLAIM CONSTRUCTION ......................................................................... 20
`VIII. MOTIVATION TO COMBINE THE TEACHINGS OF THE CITED
`PRIOR ART .................................................................................................. 21
`A. Ooishi and Palaniswami ..................................................................... 21
`B. Dell and Abe ....................................................................................... 28
`C. Dell and JESD21-C ............................................................................ 31
`D. Dell, Abe and JESD21-C ................................................................... 32
`E.
`Ooishi, Palaniswami, and Abe ........................................................... 32
`INVALIDITY GROUNDS ........................................................................... 33
`A.
`Claims 1 and 5 of the ’315 Patent Are Anticipated By Dell .............. 34
`B.
`Claims 1 and 5 of the ’315 Patent are Rendered Obvious by
`Ooishi in combination with Palaniswami .......................................... 46
`Claims 10 and 16 of the ’315 Patent are Rendered Obvious by
`Dell in combination with Abe ............................................................ 64
`
`IX.
`
`C.
`
`Samsung Ex. 1002 - Page i
`
`

`

`U.S. Patent No. 6,243,315
`Declaration of Dr. Andrew Wolfe
`
`
`
`
`E.
`
`F.
`
`D.
`
`Claims 10 and 16 of the ’315 Patent are Rendered Obvious by
`Ooishi in combination with Palaniswami, and further in
`combination with Abe ........................................................................ 78
`Claims 2-4, and 6-9 of the ’315 Patent are Rendered Obvious
`by Dell in combination with JESD21-C ............................................. 83
`Claims 11-15 and 17-20 of the ’315 Patent are Rendered
`Obvious by Dell in combination with Abe, and further in
`combination with JEDEC ................................................................... 90
`SECONDARY CONSIDERATIONS OF NON-OBVIOUSNESS ............. 98
`X.
`XI. CONCLUSION ............................................................................................. 98
`
`
`
`Samsung Ex. 1002 - Page ii
`
`

`

`U.S. Patent No. 6,243,315
`Declaration of Dr. Andrew Wolfe
`
`
`LIST OF EXHIBITS
`
`Description
`
`U.S. Patent No. 6,243,315
`Curriculum Vitae of Dr. Andrew Wolfe
`U.S. Patent No. 6,327,664 to Dell, issued December 4, 2001
`U.S. Patent No. 5,590,082 to Abe, issued December 31, 1996
`JESD21-C: JEDEC Configurations for Solid State Memories,
`Release 7, Published January 1997
`Declaration of John R. Kelly Regarding Records of JEDEC
`U.S. Patent No. 6,172,928 to Ooishi, issued August January 9, 2001
`U.S. Patent No. 6,144,219 to Palaniswami, issued November 7,
`2000
`Micron MT48LC4M4R1(S) Functional Specification, 1994
`Micron MT48LC4M4A1/A2 S Datasheet, 1998
`U.S. Patent No. 4,005,395 to Fosler, Jr. et al. issued January 25,
`1977
`
`
`Exhibit No.
`1001
`1003
`1004
`1005
`1006
`
`1007
`1008
`1009
`
`1010
`1011
`1012
`
`
`
`
`Samsung Ex. 1002 - Page iii
`
`

`

`I, Andrew Wolfe, declare as follows:
`
`U.S. Patent No. 6,243,315
`Declaration of Dr. Andrew Wolfe
`
`
`I.
`
`INTRODUCTION
`1.
`
`I have prepared this Declaration in connection with Samsung
`
`Electronics Co, Ltd.’s (“Samsung” or “Petitioner”) Petition for Inter Partes
`
`Review of U.S. Patent No. 6,243,315 (“the ’315 Patent”) (Ex. 1001), which I
`
`understand is to be filed concurrently with this Declaration.
`
`2.
`
`In the course of preparing this Declaration, I reviewed the ’315 Patent
`
`as well as its prosecution file history. I understand that the claims at issue in this
`
`proceeding are Claims 1-20. Claims 1 and 10 are the independent claims. In
`
`addition to the ’315 Patent, I have also reviewed the documents discussed in this
`
`Declaration.
`
`II. EXPERIENCE AND QUALIFICATIONS
`3. My professional qualifications, experience, publications and
`
`presentations, and a listing of previous cases in which I have provided expert
`
`testimony are set forth in my CV, attached as Exhibit 1003. I am being
`
`compensated at my usual rate of $550.00 per hour for work on this case. My
`
`compensation is in no way related to the outcome of this case. I have no financial
`
`interest in Samsung or the ’315 Patent.
`
`4.
`
`I am the founder and sole employee of Wolfe Consulting. Through
`
`Wolfe Consulting, I provide technical and business analysis to businesses on
`
`Samsung Ex. 1002 - Page 1
`
`

`

`processor technology, computer systems, consumer electronics, software, design
`
`U.S. Patent No. 6,243,315
`Declaration of Dr. Andrew Wolfe
`
`
`tools, data security, cryptography and intellectual property issues. I have more
`
`than thirty years' experience developing products, researching, consulting, and
`
`teaching in those fields. In that time, I have worked as a computer architect,
`
`computer system designer, and as an executive in the PC and electronics business.
`
`I have also taught at some of the world's leading institutions in those fields,
`
`including Stanford University, Princeton University, Carnegie Mellon University,
`
`and Santa Clara University.
`
`5.
`
`In 1985, I earned the B.S.E.E. degree in Electrical Engineering and
`
`Computer Science from The Johns Hopkins University. In 1987, I received the
`
`M.S. degree in Electrical and Computer Engineering from Carnegie Mellon
`
`University and in 1992, I received the Ph.D. degree in Computer Engineering from
`
`Carnegie Mellon University. My doctoral dissertation proposed a new approach
`
`for the architecture of a computer processor.
`
`6.
`
`In 1983, I began designing touch sensors, microprocessor-based
`
`computer systems, and I/O (input/output) cards for personal computers as a senior
`
`design engineer for Touch Technology, Inc. During the course of my design
`
`projects with Touch Technology, I designed I/O cards for PC-compatible computer
`
`systems, including the IBM PC-AT, to interface with interactive touch-based
`
`computer terminals that I designed for use in public information systems. I
`
`Samsung Ex. 1002 - Page 2
`
`

`

`continued designing and developing related technology as a consultant to the
`
`U.S. Patent No. 6,243,315
`Declaration of Dr. Andrew Wolfe
`
`
`Carroll Touch division of AMP, Inc., where in 1986 I designed one of the first
`
`custom touch-screen integrated circuits. I designed the touch/pen input system for
`
`the Linus WriteTop, which many believe to be the first commercial tablet
`
`computer.
`
`7.
`
`From 1986 through 1987, I designed and built a high-performance
`
`computer system as a student at Carnegie Mellon University. From 1986 through
`
`early 1988, I also developed the curriculum, and supervised the teaching
`
`laboratory, for processor design courses.
`
`8.
`
`In the latter part of 1989, I worked as a senior design engineer for
`
`ESL-TRW Advanced Technology Division. While at ESL-TRW, I designed and
`
`built a bus interface and memory controller for a workstation-based computer
`
`system, and also worked on the design of a multiprocessor system.
`
`9.
`
`At the end of 1989, I (along with some partners) reacquired the rights
`
`to the technology I had developed at Touch Technology and at AMP, and founded
`
`The Graphics Technology Company. Over the next seven years, as an officer and
`
`a consultant for The Graphics Technology Company, I managed the company's
`
`engineering development activities and personally developed dozens of touch
`
`screen sensors, controllers, and interactive touch-based computer systems.
`
`Samsung Ex. 1002 - Page 3
`
`

`

`I have consulted, formally and informally, for a number of fabless
`
`U.S. Patent No. 6,243,315
`Declaration of Dr. Andrew Wolfe
`
`
`10.
`
`semiconductor companies. In particular, I have served on the technical advisory
`
`boards for two processor design companies: BOPS, Inc., where I chaired the board,
`
`and Siroyan Ltd., where I served in a similar role for three networking chip
`
`companies—Intellon, Inc., Comsilica, Inc., and Entridia, Inc.—and one 3D game
`
`accelerator company, Ageia, Inc.
`
`11.
`
`I have also served as a technology advisor to Motorola and to several
`
`venture capital funds in the U.S. and Europe. Currently, I am a director of Turtle
`
`Beach Corporation, providing guidance in its development of premium audio
`
`peripheral devices for a variety of commercial electronic products.
`
`12. From 1991 through 1997, I served on the Faculty of Princeton
`
`University as an Assistant Professor of Electrical Engineering. At Princeton, I
`
`taught undergraduate and graduate-level courses in Computer Architecture,
`
`Advanced Computer Architecture, Display Technology, and Microprocessor
`
`Systems, and conducted sponsored research in the area of computer systems and
`
`related topics. From 1999 through 2002, I taught the Computer Architecture
`
`course to both undergraduate and graduate students at Stanford University multiple
`
`times as a Consulting Professor. At Princeton, I received several teaching awards,
`
`both from students and from the School of Engineering. I have also taught
`
`advanced microprocessor architecture to industry professionals in IEEE and ACM
`
`Samsung Ex. 1002 - Page 4
`
`

`

`sponsored seminars. I am currently a lecturer at Santa Clara University teaching
`
`U.S. Patent No. 6,243,315
`Declaration of Dr. Andrew Wolfe
`
`
`courses on Computer Organization and Architecture and Mechatronics.
`
`13. From 1997 through 2002, I held a variety of executive positions at a
`
`publicly held fabless semiconductor company originally called S3, Inc. and later
`
`called Sonicblue Inc. I held the positions of Chief Technology Officer, Vice
`
`President of Systems Integration Products, Senior Vice President of Business
`
`Development, and Director of Technology, among others.
`
`14.
`
`In the roles listed above, I worked with and managed architecture and
`
`design teams responsible for the development of SRAM and DRAM memories,
`
`graphics chip memory controllers, and CPU memory controllers. I also worked
`
`with memory vendors and memory standards bodies, directly and through my staff,
`
`on the development of memory technology and standards.
`
`15. My teams also developed the Rio MP3 players and a music delivery
`
`platform and webstore backend service for selling music. In 1999, this music
`
`delivery system was spun out as a separate company called RioPort.com. I served
`
`on the RioPort.com board of directors and became involved in their product and
`
`technology strategy. I also managed engineering and marketing for the Rio
`
`product line for a period of time as an interim general manager. During my time at
`
`SonicBlue we launched more than 30 new consumer electronics products.
`
`Samsung Ex. 1002 - Page 5
`
`

`

`I served as a board member and technical advisor at KBGear Inc.
`
`U.S. Patent No. 6,243,315
`Declaration of Dr. Andrew Wolfe
`
`
`16.
`
`from 1999-2001. KBGear Inc. designed and produced digital cameras and music
`
`players.
`
`17.
`
`I have published more than fifty peer-reviewed papers in computer
`
`architecture and computer systems design. I have also chaired IEEE and ACM
`
`conferences in microarchitecture and integrated circuit design. I am a named
`
`inventor on at least fifty-three U.S. patents and twenty-eight foreign patents.
`
`18.
`
`I have been the invited keynote speaker at the ACM/IEEE
`
`International Symposium on Microarchitecture and at the International Conference
`
`on Multimedia. I have also been an invited speaker on various aspects of
`
`technology or the PC industry at numerous industry events including the Intel
`
`Developer's Forum, Microsoft Windows Hardware Engineering Conference,
`
`Microprocessor Forum, Embedded Systems Conference, Comdex, and Consumer
`
`Electronics Show as well as at the Harvard Business School and the University of
`
`Illinois Law School. I have been interviewed on subjects related to technology and
`
`the electronics industry by publications such as the Wall Street Journal, New York
`
`Times, LA Times, Time, Newsweek, Forbes, and Fortune as well as CNN, NPR,
`
`and the BBC. I have also spoken at dozens of universities including MIT,
`
`Stanford, University of Texas, Carnegie Mellon, UCLA, University of Michigan,
`
`Rice, and Duke.
`
`Samsung Ex. 1002 - Page 6
`
`

`

`III. RELEVANT LEGAL STANDARDS
`
`U.S. Patent No. 6,243,315
`Declaration of Dr. Andrew Wolfe
`
`
`19.
`
`I am not an attorney. For the purposes of this Declaration, I have been
`
`informed about certain aspects of the law that are relevant to my opinions. My
`
`understanding of the law is summarized below.
`
`20.
`
`I have been informed and understand that claim construction is a
`
`matter of law and that the final claim constructions for this proceeding will be
`
`determined by the Patent Trial and Appeal Board.
`
`21.
`
`I understand that in the context of an inter partes review, a claim of an
`
`unexpired patent must be construed according to its broadest reasonable
`
`construction in light of the specification.
`
`22.
`
`I have been informed and understand that a patent claim is anticipated
`
`under 35 U.S.C. § 102, and is therefore invalid, if all of the elements of the claim
`
`are disclosed by a single prior art reference. I have been informed and understand
`
`that anticipation does not require that a prior art reference expressly disclose each
`
`and every claim element using the same terminology as recited by the claims. I
`
`understand that a claim is anticipated if each and every element as set forth in the
`
`claim is found, either expressly or inherently, in a single prior art reference. For
`
`example, I understand that a claim limitation is inherently disclosed if it is not
`
`explicitly present in the written description of the prior art, but would necessarily
`
`be embodied or met by an apparatus or method as taught by the prior art.
`
`Samsung Ex. 1002 - Page 7
`
`

`

`Moreover, I understand that anticipation does not require that the prior art use the
`
`U.S. Patent No. 6,243,315
`Declaration of Dr. Andrew Wolfe
`
`
`same terminology recited within the patent claims.
`
`23.
`
`I have been informed and understand that a patent claim is obvious
`
`under 35 U.S.C. § 103, and therefore invalid, if the claimed subject matter, as a
`
`whole, would have been obvious to a person of ordinary skill in the art as of the
`
`priority date of the patent based on one or more prior art references and/or the
`
`knowledge of one of ordinary skill in the art. I understand that an obviousness
`
`analysis must consider (1) the scope and content of the prior art, (2) the differences
`
`between the claims and the prior art, (3) the level of ordinary skill in the pertinent
`
`art, and (4) secondary considerations, if any, of non-obviousness (such as
`
`unexpected results, commercial success, long-felt but unmet need, failure of others,
`
`copying by others, and skepticism of experts).
`
`24.
`
`I understand that a prior art reference may be combined with other
`
`references to disclose each element of the invention under 35 U.S.C. § 103. I
`
`understand that a reference may also be combined with the knowledge of a person
`
`of ordinary skill in the art, and that this knowledge may be used to combine
`
`multiple references. I further understand that a person of ordinary skill in the art is
`
`presumed to know the relevant prior art. I understand that the obviousness analysis
`
`may take into account the inferences and creative steps that a person of ordinary
`
`skill in the art would employ.
`
`Samsung Ex. 1002 - Page 8
`
`

`

`In determining whether a prior art reference would have been
`
`U.S. Patent No. 6,243,315
`Declaration of Dr. Andrew Wolfe
`
`
`25.
`
`combined with other prior art or other information known to a person of ordinary
`
`skill in the art, I understand that the following principles may be considered:
`
`a.
`
`b.
`
`whether the combinations involve non-analogous art;
`
`whether the combinations are in different fields of endeavor
`
`than the inventions in the Patent;
`
`c.
`
`whether the combinations are reasonably pertinent to the
`
`problems to which the inventions of the Patent are directed;
`
`d.
`
`whether the combination is of familiar elements according to
`
`known methods that yields predictable results;
`
`e.
`
`whether a combination involves the substitution of one known
`
`element for another that yields predictable results;
`
`f.
`
`whether the combination involves the use of a known technique
`
`to improve similar items or methods in the same way that yields
`
`predictable results;
`
`g.
`
`whether the combination involves the application of a known
`
`technique to a prior art reference that is ready for improvement,
`
`to yield predictable results;
`
`h.
`
`whether the combination is “obvious to try”;
`
`Samsung Ex. 1002 - Page 9
`
`

`

`U.S. Patent No. 6,243,315
`Declaration of Dr. Andrew Wolfe
`
`
`whether the combination involves the known work in one field
`
`i.
`
`of endeavor prompting variations of it for use in either the same
`
`field or a different one based on design incentives or other
`
`market forces, where the variations are predictable to a person
`
`of ordinary skill in the art;
`
`j.
`
`whether the combination involves some teaching, suggestion, or
`
`motivation in the prior art that would have led one of ordinary
`
`skill in the art to modify the prior art reference or to combine
`
`prior art reference teachings to arrive at the claimed invention;
`
`k.
`
`whether the combination involves proposed modifications that
`
`render the prior art unsatisfactory for its intended use;
`
`l.
`
`whether the combination involves proposed modifications that
`
`change the principle of operation of the reference;
`
`m. whether the combination possesses a reasonable expectation of
`
`success; and
`
`n.
`
`whether the combination possesses the requisite degree of
`
`predictability at the time the invention was made.
`
`26.
`
`I understand that in determining whether a combination of prior art
`
`references renders a claim obvious, it is helpful to consider whether there is some
`
`teaching, suggestion, or motivation to combine the references and a reasonable
`
`Samsung Ex. 1002 - Page 10
`
`

`

`expectation of success in doing so. I understand, however, that a teaching,
`
`U.S. Patent No. 6,243,315
`Declaration of Dr. Andrew Wolfe
`
`
`suggestion, or motivation to combine is not required.
`
`IV. LEVEL OF ORDINARY SKILL IN THE ART
`
`27. For purposes of my analyses in connection with this Declaration, I
`
`have assumed that the priority date of the ’315 Patent is December 31, 1999. I
`
`note, however, that to the extent one or more claims of the ’315 Patent were not
`
`sufficiently disclosed as of that date, the effective filing date would be later in
`
`time. In that event, my analyses would not change, because the prior art references
`
`discussed below were available to the public prior to December 31, 1999.
`
`28. Based on my review of the ’315 Patent and my background and
`
`experience in the field of electrical engineering, it is my opinion that a person of
`
`ordinary skill in the art (“POSITA”) as of December 31, 1999 would have at least a
`
`bachelor’s degree in electrical, electronics, computer engineering, or a related
`
`discipline; or the equivalent training or experience in electrical, electronics,
`
`computer engineering, or a related discipline. The person would also have an
`
`additional two or more years of experience in computer hardware, including the
`
`use of computer memory. Additional education could substitute for work
`
`experience and vice versa. The POSITA, with this level of experience, would be
`
`capable of reading and understanding the literature (including patents) related to
`
`DRAM system design and would be able to modify an existing process based on
`
`Samsung Ex. 1002 - Page 11
`
`

`

`the teachings found in the open literature. The POSITA would also be familiar
`
`U.S. Patent No. 6,243,315
`Declaration of Dr. Andrew Wolfe
`
`
`with industry standards, including the JEDEC standards.
`
`29.
`
`In forming my opinion, I have considered the claims of the ’315
`
`Patent, which are directed to a plurality of volatile solid-state memory devices that
`
`retain information when an electrical power source is applied to the memory
`
`devices within a predetermined voltage range, and are capable of being placed in a
`
`self refresh mode.
`
`30.
`
`In forming my opinion, I have also considered the types of problems
`
`encountered in the art, the prior art solutions to those problems, the rapidity with
`
`which innovations were made, the sophistication of the technology, and the
`
`educational level of active workers in the field. Based on the foregoing
`
`considerations, I was at least a person of ordinary skill in the art as of December
`
`31, 1999.
`
`V. TECHNICAL BACKGROUND
`
`A. DRAM, Self Refresh Mode, and Backup Battery
`31. Volatile memory devices, typically used for random access memory
`
`(RAM), maintain information only when a predetermined voltage is applied to
`
`them, and they lose data when electrical power is removed. Dynamic random-
`
`access memory (DRAM), a type of RAM, stores bits of information in arrays of
`
`capacitors, each of which can be charged (1) or discharged (0) by applying or
`
`Samsung Ex. 1002 - Page 12
`
`

`

`removing a predetermined voltage. An inherent property of capacitors is that they
`
`U.S. Patent No. 6,243,315
`Declaration of Dr. Andrew Wolfe
`
`
`“leak” current, meaning the capacitors will slowly discharge over time. To prevent
`
`loss of information caused by “leakage,” capacitor charge must be refreshed
`
`periodically by re-applying the predetermined voltage.
`
`32. As “refresh” is a low-power operation, it was well-known for a
`
`secondary power source to provide the standby power required for this operation.
`
`A secondary power source also offers protection against data loss in the case of
`
`unexpected power outages. The secondary power source may be a temporary
`
`power source, an external power supply, and/or a backup battery. The use of a
`
`secondary power source for providing temporary standby power during refresh
`
`modes for DRAM was well-known in the art since at least May 8, 1975, as
`
`illustrated in U.S. Patent No. 4,005,395 to Fosler, Jr. et al. (Ex. 1012). Fosler
`
`discloses “[d]ynamic memory devices [that] are commercially available as MOS
`
`random access memory (RAM) devices” configured so that “[d]uring the refresh
`
`address mode, should the high power [be lost], low power output . . . will be
`
`sufficient to generate a refresh signal.” Ex. 1012 at 2:35-38 and 4:49-56. Fosler
`
`specifically discloses that “when operating from standby power there is very little
`
`drain on the battery or always-on power source.” Id. at 5:31-35.
`
`33. DRAM with self-refresh mode was well-known in the art at the time
`
`of filing of the ’315 Patent. As illustrated in datasheets from Micron
`
`Samsung Ex. 1002 - Page 13
`
`

`

`Semiconductor Inc.’s synchronous DRAM (SDRAM) chip MT48LC4M4, DRAM
`
`U.S. Patent No. 6,243,315
`Declaration of Dr. Andrew Wolfe
`
`
`has included self-refresh mode since at least 1994. For example, a 1994
`
`specification for this chip includes a block diagram illustrating a “self-refresh
`
`oscillator and timer” (Ex. 1011 at 2), and an 1998 datasheet for the same chip
`
`discloses that “[t]he SELF REFRESH command can be used to retain data in the
`
`SDRAM, even if the rest of the system is powered down. ” (Ex. 1012 at 1
`
`(emphasis in original)).
`
`34. The numerous references in the prior art to DRAM with self-refresh
`
`mode also establish that this concept was well-known. See, e.g., 1006 at Abstract
`
`(“Power supply voltage is provided to circuitry that is required for a self refresh
`
`operation.”); Ex. 1006 at Abstract (“For a DRAM provided with a self-refreshing
`
`function . . .”); Ex. 1004 at 3:56-60 (“JEDEC standards define three different
`
`reduced power modes for conventional SDRAMs . . . 3) self refresh mode . . .”);
`
`Ex. 1005at Abstract (“A method and apparatus for selectively causing each bank of
`
`a number of banks of DRAMs . . . to enter into the self refresh mode . . .”); Ex.
`
`1010 at Claim 9 (“. . . providing a memory data refresh circuit . . .”).
`
`B. Memory Controllers and Address and Control Lines
`35. Volatile memory devices such as DRAM are typically configured to
`
`interface with a memory controller of a host computer system for regular
`
`operation. Once connected with the memory controller of the computer system the
`
`Samsung Ex. 1002 - Page 14
`
`

`

`volatile memory devices receive power for operation and instructions and data for
`
`U.S. Patent No. 6,243,315
`Declaration of Dr. Andrew Wolfe
`
`
`various computing processes.
`
`36. Memory controllers and memory devices typically interface through
`
`address lines and control lines, among other electronic signals. Address lines carry
`
`signals that identify the memory cells to be accessed on a given cycle. Control
`
`lines include signals such as row address strobe (RAS), column address strobe
`
`(CAS) and write enable (WE) and variations thereof, among others, that control the
`
`timing and behavior of the memory device. For example the RAS signal indicates
`
`to the memory device that the signal on the address line is a row address, and the
`
`WE signal indicates that data should be written to (as opposed to read from) the
`
`corresponding memory cells. Sensing periods of inactivity and initiating self-
`
`refresh mode in response was a conventional use of a DRAM memory controller in
`
`the prior art.
`
`37. As demonstrated by the numerous references in the prior art, memory
`
`controllers, address lines, and control lines were well known at the time of filing of
`
`the ’315 Patent. See, e.g., Ex. 1004 at Fig. 1 (depicting “memory controller 28”
`
`and “address/control bus 16”); Ex. 1005 at Fig. 1 (depicting “memory controller
`
`14”) and Fig. 4 (depicting control signals “RAS,” “CAS,” and “WE,” and address
`
`signals feeding into “address register 36”); Ex. 1010 at Figs. 1 and 2 (depicting
`
`“memory controller 12”); Ex. 1009 at Fig. 1 (depicting “control signals” including
`
`Samsung Ex. 1002 - Page 15
`
`

`

`“RAS,” “CAS,” and “WE,” and “address signals A0-A12”); Ex. 1009 at Fig. 1
`
`U.S. Patent No. 6,243,315
`Declaration of Dr. Andrew Wolfe
`
`
`(depicting “DRAM control circuit 4” and “DRAM control signals” such as “RAS”
`
`(65) and “CAS” (66)).
`
`VI. OVERVIEW OF THE INVALIDATING PRIOR ART
`
`38.
`
`I have briefly summarized the prior art references that anticipate or
`
`render obvious Claims 1-20 of the ’315 Patent. None of the references discussed
`
`below were before the examiner during prosecution of the patent application that
`
`issued as the ’315 Patent.
`
`A. U.S. Patent No. 6,327,664 (“Dell”)
`39. Dell, Ex. 1004, was based on an application filed on April 30, 1999
`
`and it is my understanding that it qualifies as prior art under at least pre-AIA 35
`
`U.S.C. §§ 102(e)(2) (“A person shall be entitled to a patent unless the invention
`
`was described in … a patent granted on an application for patent by another filed in
`
`the United States before the invention by the applicant for patent [].”). Dell names
`
`four inventors and was never discussed or used in a rejection by the
`
`examiner. Dell discloses a memory module for use in a computer system with
`
`individually addressable banks of memory chips that can be placed in a higher
`
`power state or lower power state by a system memory controller or digital signal
`
`processor (“DSP”). Ex. 1004 at 1:48-52. The activity of these memory banks,
`
`and/or portions thereof, are sensed while in the higher power state, and the power
`
`Samsung Ex. 1002 - Page 16
`
`

`

`U.S. Patent No. 6,243,315
`Declaration of Dr. Andrew Wolfe
`
`state can be changed by either the DSP or memory controller. Id. at 1:63-2:3. The
`
`advantage of Dell is power savings, in that the module is able to selectively and
`
`expeditiously reduce power to individual banks of memory (or portions thereof)
`
`when they are not being accessed. Id. at 1:40-45.
`
`40. The module of Dell accommodates several levels of reduced power
`
`operation, including those conventional to SDRAMs according to the JEDEC
`
`standard, e.g. clock suspend mode, power down mode, and self refresh mode. Id.
`
`at 3:42-47; 3:56-60. Dell discloses that self-refresh mode is used whenever the
`
`reduced power requirement will last longer than it would take to refresh the
`
`memory, and that all receivers of the memory (communication pin circuits) are
`
`deactivated when in that mode:
`
`The self refresh mode is used if it is expected that the duration of the
`reduced power requirement will last longer than the cycle time of a
`refresh cycle. In this mode, only the clock enable signal is active,
`with all the other receivers being turned off. The SDRAMs perform a
`self refresh function and thus the internal clocks of each of the
`SDRAMs are frozen, but are selectively partially activated to perform
`the self refresh function.
`
`Id. at 4:11-18.
`
`B. U.S. Patent No. 6,172,928 (“Ooishi”)
`41. Ooishi, Ex. 1009, was based on an application filed on June 2, 1999
`
`and it is my understanding that it qualifies as prior art under at least pre-AIA 35
`
`U.S.C. §§ 102(e)(2) (“A person shall be entitled to a patent unless the invention
`
`Samsung Ex. 1002 - Page 17
`
`

`

`U.S. Patent No. 6,243,315
`Declaration of Dr. Andrew Wolfe
`
`was described in … a patent granted on an application for patent by another filed in
`
`the United States before the invention by the applicant for patent [].”). Ooishi
`
`discloses a memory device that reduces power consumption during a self-refresh
`
`operation. Ex. 1009 at 1:41-43. The memory device of Ooishi has both a normal
`
`mode and a power down mode, and further includes a self-refresh circuit that
`
`generates a refresh address signal when in power down mode. Id. at 1:44-50; 1:56-
`
`57. Ooishi further discloses a first power supply and second power supply, one to
`
`be used in normal mode and the other to be used in power down mode,
`
`respectively. Id. at 1:64-2:4.
`
`C. U.S. Patent No. 6,144,219 (“Palaniswami”)
`42. Palaniswami, Ex. 1010, was based on an application filed on January
`
`21, 1997, and it is my understanding that it qualifies as prior art under at least pre-
`
`AIA 35 U.S.C. §§ 102(e)(2) (“A person shall be entitled to a patent unless the
`
`invention was described in … a patent granted on an application for patent by
`
`another filed in the United States before the invention by the applicant for patent
`
`[].”). Palaniswami discloses an isolation mechanism that is situated between a
`
`DSP and a DRAM controller that serves to selectively isolate these outputs from
`
`the DRAM controller. Ex. 1010 at 2:65-3:15. The stated goal of Palaniswami’s
`
`isolation mechanism is to prevent corruption of DRAM due to faulty DSP signals
`
`and attributable to lost or depleted battery supply. Id. at 2:1-5.
`
`Samsung Ex. 1002 - Page 18
`
`

`

`U.S. Patent No. 6,243,315
`Declaration of D