Trials@uspto.gov
`571.272.7822
`
`
` Paper No. 7
`
`Filed: March 9, 2018
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`
`SAMSUNG ELECTRONICS AMERICA, INC.,
`Petitioner,
`
`v.
`
`JAMES B. GOODMAN,
`Patent Owner.
`
`Case IPR2017-02021
`Patent 6,243,315 B1
`____________
`
`
`
`Before BRIAN J. McNAMARA, PATRICK M. BOUCHER, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`McGRAW, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`571.272.7822
`
`
` Paper No. 7
`
`Filed: March 9, 2018
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`
`SAMSUNG ELECTRONICS AMERICA, INC.,
`Petitioner,
`
`v.
`
`JAMES B. GOODMAN,
`Patent Owner.
`
`Case IPR2017-02021
`Patent 6,243,315 B1
`____________
`
`
`
`Before BRIAN J. McNAMARA, PATRICK M. BOUCHER, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`McGRAW, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`
`IPR2017-02021
`Patent 6,243,315 B1
`
`
`I.
`
`INTRODUCTION
`
`Samsung Electronics America, Inc. (“Petitioner”) filed a Petition
`
`requesting an inter partes review of claims 1–20 (“the challenged claims”)
`
`of U.S. Patent No. 6,243,315 B1 (Ex. 1001, “the ’315 patent”). Paper 2
`
`(“Pet.”). James B. Goodman, (“Patent Owner”) filed a Preliminary
`
`Response. Paper 6 (“Prelim. Resp.”).
`
`We have jurisdiction under 35 U.S.C. § 314(a), which provides that an
`
`inter partes review may not be instituted unless the information presented in
`
`the Petition shows “there is a reasonable likelihood that the petitioner would
`
`prevail with respect to at least 1 of the claims challenged in the petition.”
`
`Upon consideration of the Petition, the Preliminary Response, and the
`
`evidence therein, we conclude the information presented shows there is a
`
`reasonable likelihood that Petitioner would prevail in establishing the
`
`unpatentability of claims 1–20 of the ’315 patent.
`
`Our factual findings and conclusions at this stage of the proceeding,
`
`including claim construction, are preliminary and are based on the
`
`evidentiary record developed thus far. This is not a final decision as to
`
`patentability of claims for which inter partes review is instituted. Our final
`
`decision will be based on the record as developed fully during trial.
`
`A. Related Proceedings
`
`The parties identify the following litigations as related proceedings:
`
`Goodman v. Samsung Electronics America, Inc., C.A. No. 17-CV-05539
`
`(S.D. N.Y.); Goodman v. Hewlett-Packard Co., C.A. No. 16-CV-03195
`
`(S.D. Tex.); Goodman v. ASUS Computer Int’l, Inc., Case No. 4:16-cv-
`
`03232 (S.D. Tex.); Goodman v. ASUS Computer Int’l, Inc., 3:17-cv-05542
`
`(N.D. Ca.). Pet. 2; Paper 5.
`
`2
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`IPR2017-02021
`Patent 6,243,315 B1
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`We also note that the ’315 patent is also the subject of current
`
`petitions for inter partes review by Petitioner HP Inc. (Case IPR2017-
`
`01994) and by Petitioner ASUS Computer International Inc. (IPR2018-
`
`00047).
`
`B. The ’315 Patent
`
`The ’315 patent is directed to volatile memory devices. Ex. 1001,
`
`Abstract. Volatile memory devices “retain the contents of their memory
`
`states when electrical power is provided and maintained on the devices,” but
`
`“[w]henever electrical power is removed from the devices, the memory
`
`contents of the device [are] lost and irretrievable.” Id. at 2:54–58. Figure 4
`
`of the ’315 patent is reproduced below:
`
`Figure 4, shown above, illustrates a block diagram of a non-volatile memory
`
`system according to the invention. Ex. 1001, 4:41–42.
`
`
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`3
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`IPR2017-02021
`Patent 6,243,315 B1
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`According to the ’315 patent:
`
`The invention prevents the loss of data due to unexpected power
`outages and also prevents errant control and address signals to
`the memory devices by monitoring the input electrical power
`source to the memory devices for acceptable conditions, and
`electrically isolating the memory devices from signals received
`on the control lines and address lines and switching to an
`alternate internal electrical power source, typically a battery,
`whenever the input power source is unacceptable.
`
`Id. at 3:15–24. The ’315 patent explains further that the system
`
`“maintains the integrity of the data retained by the memory devices by
`
`isolating the devices from the external power source, control lines and
`
`address lines and placing the memory devices into a power down self-
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`refresh mode which will maintain the data using a minimum of
`
`electrical power.” Id. at 3:25–30.
`
`C. Illustrative Claims
`
`
`
`Independent claims 1 and 10 are illustrative of the claims at issue and
`
`are reproduced below.1
`
`1. A memory system for use in a computer system, said
`memory system comprising:
`
`[a] a plurality of volatile solid state memory devices that
`retain information when an electrical power source is
`applied to said memory devices within a predetermined
`voltage range and capable of being placed in a self refresh
`mode; said memory devices having address lines and
`control lines;
`
`[b] a control device for selectively electrically isolating
`said memory devices from respective address lines and
`
`
`
`1 Paragraph breaks and bracketed letters have been added for ease of
`reference and for consistency with nomenclature utilized by Petitioner.
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`4
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`IPR2017-02021
`Patent 6,243,315 B1
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`respective control lines so that when said memory devices
`are electrically isolated, any signals received on said
`respective address lines and respective control lines do not
`reach said memory devices; and
`
`[c] a memory access enable control device coupled to said
`control device and to said control lines for determining
`when said memory system is not being accessed and for
`initiating a low power mode for said memory system
`wherein said control device electrically isolates said
`memory devices and places said memory devices in said
`self refresh mode, thereby reducing the amount of
`electrical energy being drawn from an electrical power
`supply for said computer system.
`
`Ex. 1001, 13:18–40.
`
`10. A memory system for use in a computer system, said
`memory system comprising:
`
`[a] a plurality of volatile solid state memory devices that
`retain information when an electrical power source having
`a voltage greater than a predetermined voltage is applied
`to said devices; said memory devices having address lines
`and control lines;
`
`[b] said computer system including a first electrical power
`source for operating said computer and being capable of
`producing a first voltage applied to said memory devices;
`
`[c] a control device for monitoring said first voltage to
`determine when said first voltage is less than said
`predetermined voltage and for selectively electrically
`isolating said memory devices from respective address
`lines and respective control lines so that when said
`memory devices are electrically isolated, any signals
`received on said respective address lines and respective
`control lines do not reach said memory devices; and
`
`[d] a second electrical power source operable for
`supplying a second voltage to said memory devices greater
`than said predetermined voltage;
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`5
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`IPR2017-02021
`Patent 6,243,315 B1
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`[e] said control device being operable for disconnecting
`said first electrical power source from said memory
`devices and connecting said second electrical power
`source to said memory devices when said first voltage is
`less than said predetermined voltage;
`
`[f] whereby, data in said memory devices is preserved by
`said second electrical power source when said first
`electrical power source fails to maintain at least said
`predetermined voltage on said memory devices, and said
`memory devices are isolated from errant signals.
`
`Id. at 13:65–14:32.
`
`D. Asserted Grounds of Unpatentability
`
`
`
`Relying upon the declaration testimony of Andrew Wolfe, Ph.D., (Ex.
`
`1002, “Wolfe Declaration”), Petitioner challenges claims 1–20 of the ’315
`
`patent based on the asserted grounds of unpatentability (“grounds”) set forth
`
`in the table below. Pet. 3, 12–72.
`
`Reference(s)
`
`Basis
`
`Challenged Claims
`
`Dell2
`
`Dell and Abe3
`
`Dell and JESD21-C4
`
`Dell, Abe, and JESD21-C
`
`§ 102
`
`§ 103
`
`§ 103
`
`§ 103
`
`1 and 5
`
`10 and 16
`
`2–4 and 6–9
`
`11–15 and 17–20
`
`
`
`2 U.S. Patent No. 6,327,664 B1, filed April 30, 1999, issued December 4,
`2001 (Ex. 1004, “Dell”).
`3 U.S. Patent No. 5,590,082, issued December 31, 1996. (Ex. 1005, “Abe”).
`4 JESD21-C: JEDEC Configurations for Solid State Memories,
`Release 7, January 1997 (Ex. 1006, “JESD21-C”).
`
`6
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`IPR2017-02021
`Patent 6,243,315 B1
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`Reference(s)
`
`Ooishi5 and Palaniswami6
`
`Basis
`
`§ 103
`
`Challenged Claims
`
`1 and 5
`
`Ooishi, Palaniswami, and Abe § 103
`
`10 and 16
`
`II. DISCUSSION
`
`A. Level of Ordinary Skill in the Art
`
`In determining whether an invention would have been obvious at the
`
`time it was made, we consider the level of ordinary skill in the pertinent art
`
`at the time of the invention. Graham v. John Deere Co, 383 U.S. 1, 17
`
`(1966). Petitioner contends a person of ordinary skill in the art at the time of
`
`the alleged invention of the ’315 patent (a “POSITA”) would have, inter
`
`alia, had a bachelor’s degree in electrical, electronics, computer engineering;
`
`or the equivalent training, and would have had approximately 2 to 3 years of
`
`experience in computer systems, circuits, electronics, or a related discipline.
`
`Pet. 9; Ex. 1002 ¶¶ 27–30.
`
`Patent Owner does not articulate a level of skill for a POSITA. For
`
`the purposes of this Decision, we determine that it is not necessary to state
`
`explicitly a specific level of skill as the prior art itself reflects an appropriate
`
`level of skill. See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir.
`
`2001).
`
`B. Claim Construction
`
`In an inter partes review, we construe claim terms in an unexpired
`
`patent according to their broadest reasonable construction in light of the
`
`
`
`5 U.S. Patent No. 6,172,928, filed January 2, 1999, issued January 9, 2001
`(Ex. 1008, “Ooishi”).
`6 U.S. Patent No. 6,144,219, filed January 21, 1997, issued November 7,
`2000 (Ex. 1009, “Palaniswami”)
`
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`IPR2017-02021
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`specification of the patent in which they appear. 37 C.F.R. § 42.100(b).
`
`Consistent with the broadest reasonable construction, claim terms are
`
`presumed to have their ordinary and customary meaning as understood by a
`
`person of ordinary skill in the art in the context of the entire patent
`
`disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir.
`
`2007).
`
`Petitioner asserts that under the broadest reasonable construction, the
`
`plain meaning of the phrase “selectively electrically isolating said memory
`
`devices from respective address lines and respective control lines,” found in
`
`independent claims 1 and 10, “in the context of conventional memory
`
`devices and signals is that such signals are inhibited from arriving at the
`
`given memory devices.” Pet. 10 (citing Ex. 1002 ¶ 47).
`
`Patent Owner does not identify any claim terms as warranting
`
`construction. Based on the current record, we conclude that no claim
`
`construction is necessary for our determination of whether to institute inter
`
`partes review of the challenged claims. Vivid Techs., Inc. v. Am. Sci. &
`
`Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999) (“[O]nly those terms need be
`
`construed that are in controversy, and only to the extent necessary to resolve
`
`the controversy.”).
`
`C. Overview of the Asserted Art
`
`1. Dell (Ex. 1004)
`
`Dell, titled “Power Management on a Memory Card Having a Signal
`
`Processing Element,” describes a memory module having individually
`
`addressable banks of memory chips that can be placed into a higher or lower
`
`power state by a system memory controller or digital signal processor
`
`(“DSP”). Ex. 1004, 1:48–63. The memory module of Dell is able to
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`8
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`IPR2017-02021
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`selectively and expeditiously reduce power to individual banks of memory
`
`(or portions thereof) when they are not being accessed. Id. at 1:40-45.
`
`2. Abe (Ex. 1005)
`
` Abe is directed to a memory control circuit for initiating a self-refresh
`
`mode for a dynamic random access memory (“DRAM”) when the power
`
`supply voltage is lowered and for the self-refresh mode to consume less
`
`power. Ex. 1005, 1:5–10, 1:48–56. Abe discloses a main power supply and
`
`an auxiliary power supply, wherein the auxiliary supply is used for self-
`
`refresh functions when the main power supply is cut off. Id. at 3:5-8.
`
`3. JESD21-C: Configurations for Solid State
`Memories
`
`As an initial matter, we must determine whether Petitioner has made a
`
`threshold showing that JESD21-C is a prior art printed publication under
`
`35 U.S.C. § 102(b). To qualify as a printed publication, a document must
`
`have been sufficiently accessible to the public interested in the art before the
`
`critical date. In re Cronyn, 890 F.2d 1158, 1160 (Fed. Cir. 1989). A
`
`reference is deemed publically accessible upon a satisfactory showing that
`
`such document has been disseminated or otherwise made available to the
`
`extent persons interested and ordinarily skilled in the subject matter or art
`
`exercising reasonable diligence can locate it. Kyocera Wireless Corp. v.
`
`ITC, 545 F.3d 1340, 1350–51 (Fed. Cir. 2008).
`
`Petitioner asserts Exhibit 1006, JESD21-C, was published January
`
`1997 and is prior art under pre-AIA 35 U.S.C. § 102(b). Pet. 37–38. As
`
`support, Petitioner relies upon the Declaration of John J. Kelley (“the Kelley
`
`Declaration”), the current President of the JEDEC Solid State Technology
`
`Association (hereinafter “JEDEC”). Ex. 1007 ¶ 2. Mr. Kelly states that
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`JEDEC specification JESD21-C, Configurations for Solid State Memories,
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`Release 7 (January 1997), a copy of which is attached to his declaration as
`
`Exhibit 17, “was made publicly available in January 1997.” Id. at ¶¶ 4, 7.
`
`Mr. Kelley testifies that in January 1997 copies of the entire JESD21-C
`
`volume “would . . . have been available for purchase by anyone in the
`
`public” and that “pages comprising the specifically updated modules would
`
`have been sent to those who subscribed to the annual updating service for
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`JESD21-C.” Id. at ¶ 6.
`
`In its Preliminary Response, Patent Owner does not dispute that
`
`JESD21-C qualifies as prior art under 35 U.S.C. § 102(b). Based on the
`
`current record, Petitioner has made a threshold showing that the JESD21-C
`
`is a prior art printed publication to the ’315 patent under § 102(b).
`
`4. Ooishi (Ex. 1008)
`
`Ooishi is directed to a semiconductor memory device that reduces
`
`power consumption during a self-refresh operation. Ex. 1008, 1:41–43. The
`
`memory device of Ooishi has both a normal mode and a power down mode,
`
`and further includes a self-refresh circuit that generates a refresh address
`
`signal when in power down mode. Id. at 1:44–50; 1:56–58. Ooishi also
`
`discloses a first power supply that is used when the device is in normal mode
`
`and second power supply that is used when the device is in a power down
`
`mode. Id. at 1:64–2:11.
`
`
`
`7 For completeness of the record, Petitioner shall file a complete copy of
`Exhibit 1 referred to in the Kelly Declaration as an exhibit in this
`proceeding.
`
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`10
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`5. Palaniswami (Ex. 1009)
`
`Palaniswami is directed to an isolation mechanism located between a
`
`digital signal processor (”DSP”) and a dynamic random access memory
`
`(“DRAM”) controller that isolates DSP outputs from a DRAM controller
`
`upon occurrence of a low power condition. Ex. 1009, Abstract, 2:65–3:15,
`
`Fig. 2. The stated goal of Palaniswami’s isolation mechanism is to prevent
`
`corruption of DRAM due to faulty DSP signals and attributable to lost or
`
`depleted battery supply. Id. at 2:1–5.
`
`D. Asserted Anticipation of Claims 1 and 5
`by Dell
`
`Petitioner contends that Dell discloses all of the limitations of, and
`
`therefore anticipates, claims 1 and 5 of the ’315 patent. Pet. 12–22. For
`
`example, in mapping claim element 1a, Petitioner states that Dell discloses a
`
`plurality SDRAMs that necessarily include a “plurality of volatile solid state
`
`memory devices that retain information when an electrical power source is
`
`applied to said memory devices within a predetermined voltage range.”
`
`Id. at 13–14. Petitioner also states that “memory address/control bus 16” has
`
`“address lines and control lines” (id. at 14–15 (citing Ex. 1004, 2:32–37;
`
`2:44–45, Fig. 1; Ex. 1002 ¶ 75)) and that the SDRAM memory devices “are
`
`capable of being placed in a self-refresh mode” (id. at 3:42–47, 3:56–60,
`
`4:11–13, 4:19–22; Ex. 1002 ¶ 74). Petitioner also asserts Dell’s bus
`
`controller 34, which controls FET switch 52, is a “control device” as recited
`
`in claim element 1b that selectively isolates memory devices from address
`
`and control lines by opening the FET switch so that address and control
`
`signals transmitted from memory controller 28 do not reach the memory
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`11
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`devices. Pet. 15–19 (citing Ex. 1004, Fig. 1, 3:42–47, 3:30–35, 5:29–57; Ex.
`
`1002 ¶¶ 78, 80–83).
`
`Petitioner also argues that Dell’s memory controller 28, which is
`
`coupled to bus controller 34 (i.e., control device) and to memory
`
`address/control bus 16, is a “memory access enable control device” as
`
`recited in claim element 1c. Id. at 19 (citing Ex. 1004, 2:57–60, Fig. 1).
`
`Petitioner explains that memory controller 28 monitors activity on the
`
`SDRAM memory devices and initiates a low power/self-refresh mode when
`
`the devices are not being accessed. Id. at 20–21 (citing Ex. 1004, 1:40–45,
`
`3:33–35, 3:42–55; 4:13–15, 4:19–22, 5:49–57, Fig. 1; Ex. 1002 ¶¶ 85–87;
`
`see also Ex. 1002 ¶¶ 32, 36 (stating that sensing inactivity and initiating self-
`
`refresh mode in response was a conventional use of DRAM memory
`
`controller in the prior art). Petitioner also states that Dell discloses the
`
`limitations of dependent claim 5, which requires the memory devices of
`
`claim 1 to be DRAM semiconductor microchips. Id. at 22; Ex. 1004 at
`
`2:32–37; Ex. 1002 ¶ 90.
`
`Patent Owner responds that Dell does not disclose the “control
`
`device” and “memory access enable control device” of claim 1 because Dell
`
`does not disclose “placing all banks in a reduced power state at the same
`
`time, in contrast to the ’315 Patent” and because Dell allows “a control line,
`
`CKE to remain connected to a memory bank even when the memory bank is
`
`in a power down state.” Prelim. Resp. 10, 11 (citing Ex. 1004, 1:40–45,
`
`1:48–60, 3:18–25, 6:11–13, 6:29–38, 6:55–7:9).
`
`On this record, we are not persuaded by Patent Owner’s arguments.
`
`Claim 1 of the ’315 patent does not recite that all memory banks be placed
`
`into a reduced power state at the same time or that all memory devices are
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`electrically isolated from respective address and control lines. Significantly,
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`the preferred embodiments of the ’315 patent do not appear to isolate the
`
`memory devices from all address and control lines. For example, the ’315
`
`patent states that the control device shown in Figure 1 electrically isolates
`
`control bus 22 and address bus 17 from the memory devices, but does not
`
`state that RAS and WE control lines 26, 28 are electrically isolated from the
`
`memory devices. Ex. 1001, Fig. 4, 5:60–67; see also id. at 9:24–26 (stating
`
`that control center 115 of Figure 4 electrically isolates memory devices 5
`
`isolated from control lines 122 and address lines 117, but not stating that the
`
`memory devices are isolated from RAS and WE Control Lines).
`
` We have reviewed the evidence and argument presented in the
`
`Petition and Preliminary Response and are persuaded that the information
`
`presented shows a reasonable likelihood that Petitioner would prevail in
`
`showing that claims 1 and 5 are anticipated by Dell.
`
`E. Asserted Obviousness of Claims 10 and 16
`over Dell and Abe
`
`Petitioner argues independent claim 10 and dependent claim 16 would
`
`have been obvious over the combined teachings of Dell and Abe. Pet. 23–
`
`37. Relying on arguments similar to those presented with respect to claim 1,
`
`Petitioner argues Dell teaches the limitations of claim 10 requiring “a
`
`plurality of volatile solid state memory devices having “address lines and
`
`control lines, “a control device” for monitoring voltage and for “selectively
`
`electrically isolating [the] memory devices from respective address lines and
`
`respective control lines” so that signals on the address and control lines do
`
`not reach the memory devices. Id. at 26–27, 30–32.
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`Petitioner also asserts that Abe teaches a “first electrical power
`
`source” (e.g., main power supply 1) and a “second electrical power source”
`
`(e.g., auxiliary power supply 2 that provides power to the DRAM when the
`
`main power supply is cut off). Id. at 23, 27–28 (citing Ex. 1005, Fig. 1,
`
`1:48–56, 2:55–62; Ex. 1002 ¶¶ 129–130); see also id. at 23 (stating Abe also
`
`teaches a memory control circuit for initiating self-refresh mode for a
`
`DRAM when the power supply voltage is lowered and for the self-refresh
`
`mode to consume less power).
`
`Petitioner further contends that the combination of Abe’s power
`
`supply monitors and diodes with the bus controller 34 and FET 52 of Dell
`
`teaches the control device of claim element 10c. Id. at 29–32. For example,
`
`Petitioner contends that Abe’s power supply monitors detect when the “first
`
`voltage is less than the predetermined voltage.” Id. at 29–30 (citing Ex.
`
`1005, 3:20–26, 3:40–57, 3:57–60; Ex. 1002 ¶ 134) and that Abe’s diodes
`
`switch between the main and auxiliary power supply (i.e., “disconnect[ the]
`
`first electrical power source . . . and connect[ the] second electrical power
`
`source to the memory devices when the first voltage is less than [a]
`
`predetermined voltage.” Id. at 34–35 (citing Ex. 1005, Fig. 1, 3:5–19).
`
`Petitioner further contends that Dell’s bus controller 34 and FDET switch 52
`
`“selectively electrically isolat[e] [the] memory devices from respective
`
`address and control lines” and that it would have been obvious to substitute
`
`the bus controller 34 and FET switch 52 of Dell into the DRAM of Abe in
`
`order to inhibit address and control signals from reaching the memory
`
`devices. Id. at 30–31 (citing Ex. 1002 ¶ 136).
`
`Patent Owner argues that Dell does not teach the limitations of claim
`
`10 for the same reasons presented in connection with claim 1, and that Abe
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`does not cure the deficiencies of Dell. Prelim. Resp. 8–11. This argument is
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`not persuasive for the same reasons stated above.
`
`On the present record, Petitioner has shown sufficiently that the
`
`combination of Dell and Abe teaches all of the limitations of independent
`
`claim 10 and has provided articulated reasoning with rational underpinning
`
`for combining the references. Pet. 23–37. Petitioner also has shown
`
`sufficiently that the combination teaches the limitations of dependent claim
`
`16, for which Patent Owner makes no additional arguments. Id. at 37;
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`Prelim. Resp. 11. Accordingly, we are persuaded that the information
`
`presented shows a reasonable likelihood that Petitioner would prevail in
`
`showing that claims 10 and 16 are unpatentable over the combined teachings
`
`of Dell and Abe.
`
`F. Asserted Obviousness of Dependent Claims
`2–4, 6–9, 11–15, and 17–20
`
`Claims 2–4 and 6–9 depend directly or indirectly from claim 1 and
`
`claims 11–15 and 17–20 depend directly or indirectly from claim 10.
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`Petitioner contends JESD21–C teaches the additional limitations of these
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`claims, and therefore, claims 2–4 and 6–9 are unpatentable under § 103 over
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`Dell and JESD21-C and that claims 11–15 and 17–20 unpatentable under §
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`103 over Dell, Abe, and JESD21-C. Specifically, Petitioner asserts JESD21-
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`C teaches the claim limitations requiring: compatibility with a JEDEC
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`industry standard 144 PIN SODIMM connector (e.g., claims 2, 6, 12, 17),
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`compatibility with a JEDEC industry standard 168 PIN DIMM connector
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`(claims 3, 8, 14, 19), JEDEC standard serial presence detect circuitry (claims
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`4, 7, 9, 13, 15, and 20) and compatibility with a JEDEC industry standard 72
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`PIN SIMM connector (claims 11, 18). Pet. 8–9, 37–48.
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`15
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`Patent 6,243,315 B1
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`Patent Owner makes no additional arguments with respect to these
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`claims. See Prelim. Resp. 12. On the present record, Petitioner has shown a
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`reasonable likelihood that it would prevail in showing that claims 2–4 and
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`6–9 are unpatentable under § 103 over Dell and JESD21-C and that claims
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`11–15 and 17–20 unpatentable under § 103 over Dell, Abe, and JESD21-C.
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`G. Asserted Obviousness of Claims 1 and 5
`over Ooishi and Palaniswami
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`Petitioner asserts that claims 1 and 5 are unpatentable under 35 U.S.C.
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`§ 103 over Ooishi and Palaniswami. Pet. 49–65. Petitioner asserts that the
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`semiconductor memory device of Ooishi can be a DRAM having a plurality
`
`of volatile solid state memory devices that are capable of being placed in a
`
`self-refresh mode, as well as address an control lines, as recited in claim
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`element 1a. Pet. 52– 55 (citing, inter alia, Ex. 1008, 1:44–50, 1:56–58,
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`3:18–26, 5:3–15, 5:38–41). Petitioner contends that Ooishi’s teaching that,
`
`in the power down mode, power is not supplied to circuitry that is not
`
`required for a self-refresh operation, renders obvious the “control device”
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`limitation of claim element 1b. Id. at 56–57. Petitioner states that a
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`POSITA would understand that because the components that connect to the
`
`address and control signals to the DRAM are not supplied with power, the
`
`address and control signals are electrically isolated from the DRAM during
`
`the self-refresh mode. Id. (citing Ex. 1002 ¶ 101–102).
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`Petitioner further states that Palaniswami’s “isolation mechanism” 20
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`is also a control device because the isolation mechanism selectively isolates
`
`DRAM 6 from output signals from digital signal processor (“DSP”) 4. Id. at
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`57–59 (citing Ex. 1009, 2:65–3:5, 3:8–14; Ex. 1002 ¶¶103–105. Petitioner
`
`contends that a POSITA would have been motivated to combine the
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`16
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`isolation mechanism of Palaniswami with the DRAM and address/control
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`signals of Ooishi given Ooishi’s explicit suggestion that the DRAM can be
`
`isolated from control and address signals in low-power situations. Id. at 59
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`(citing Ex. 1002 ¶ 107; Ex. 1008, 6:23–28, 6:38–42). Petitioner contends
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`that Ooishi’s “mode decoder” acts as the “memory access enable control
`
`device” of claim element 1c because the mode decoder “determines when
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`the memory system is not being accessed, through a clock enable signal
`
`CKE, . . . which then outputs a self-refresh set signal to initiate self-refresh
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`(i.e., low power) mode.” Id. at 63–64 (citing Ex. 1008, Fig. 1, 5:16–19,
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`6:38–44, 6:51–55, 7:34–45; Ex. 1002 ¶¶ 114–116).
`
`Patent Owner responds that Ooishi does not have a control means
`
`monitoring the memory devices to determine when there is no activity.
`
`Prelim. Resp. 12 (citing Ex. 1008, 18:6–15, 18:66–19:4, 19:18–25). We are
`
`not persuaded by Patent Owner’s argument at this stage of the proceeding
`
`based on the current record. As noted above, Petitioner argued that Ooishi’s
`
`mode decoder determines when the memory system is not being accessed
`
`through the clock enable signal CKE. Pet. 63–64.
`
`Patent Owner also contends that Petitioner has failed to provide a
`
`motivation for someone “to add Palaniswami to protect data already being
`
`protected.” Prelim. Resp. 13. This argument is not persuasive at this stage
`
`of the proceeding. Petitioner has provided evidence, supported by
`
`declaration testimony, that a person of ordinary skill in the art would have
`
`reason to interpose the “isolation mechanism” of Palaniswami between logic
`
`unit 100 and DRAM 200 of Ooishi to “ensure” that those signals did not
`
`mistakenly modify or corrupt the stored data. Pet. 59–60 (citing Ex. 1002
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`17
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`¶¶ 107–108), 51–52 (citing Ex. 1002 ¶¶ 51–59), 61 (citing Ex. 1009, 4:36–
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`38), 65–66 (citing Ex. 1002 ¶ 121).
`
`On the present record, we are persuaded Petitioner has shown
`
`sufficiently the combination of Ooishi and Palaniswami teaches or suggests
`
`the limitations of claims 10 and 16 and has provided articulated reasoning
`
`with rational underpinning for combining the references. Accordingly, the
`
`information presented shows a reasonable likelihood that Petitioner would
`
`prevail in showing that claims 10 and 16 would have been obvious over the
`
`combination of Ooishi and Palaniswami.
`
`H. Asserted Obviousness of Claims 10 and 16
`over Ooishi, Palaniswami and Abe
`
` Petitioner contends that claims 10 and 16 would have been obvious
`
`over the combined teachings of Ooishi, Palaniswami, and Abe and provided
`
`evidence and argument as where the references teach the limitations of these
`
`claims. Pet. 66–72. For example, relying on arguments similar to those
`
`presented for the unpatentability of claim 1 over Ooishi and Palaniswami,
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`Petitioner contends that Ooishi and Palaniswami teach the limitations of
`
`claim 10 requiring “a plurality of volatile solid state memory devices having
`
`address lines and control lines,” “a control device” for monitoring voltage
`
`and for “selectively electrically isolating [the] memory devices from
`
`respective address lines and respective control lines” so that signals on the
`
`address and control lines do not reach the memory devices. Id. at 67–70.
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`Petitioner also asserts that Abe teaches a “first electrical power source” (e.g.,
`
`main power supply 1) and a “second electrical power source” (e.g., auxiliary
`
`power supply 2, which provides power to the DRAM when the main power
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`supply is cut off). Id. at 68–70. Petitioner further asserts that Abe’s
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`18
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`teaching of an auxiliary power supply that powers the self-refresh mode
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`when the main power supply is shut off, teaches the limitation of claim
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`element 10f “whereby, data in said memory devices is preserved by said
`
`second electrical power source when said first electrical power source fails
`
`to maintain at least said predetermined voltage on said memory devices.”
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`Id. at 71.
`
`On the present record, we are persuaded Petitioner has shown
`
`sufficiently that the combination of Ooishi, Palaniswami, and Abe teaches or
`
`suggests the limitations of claims 10 and 16 and has provided articulated
`
`reasoning with rational underpinning for combining the references. See,
`
`e.g., Id. at 66–72. Patent Owner makes no additional arguments with respect
`
`to these claims. See Prelim. Resp. 13. Accordingly, the information
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`presented shows a reasonable likelihood that Petitioner would prevail in
`
`establishing that claims 10 and 16 would have been obvious over Ooishi,
`
`Palaniswami, and Abe.
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`III. CONCLUSION
`
`For the foregoing reasons, we determine Petitioner has demonstrated
`
`there is a reasonable likelihood it would prevail in establishing the
`
`unpatentability of claims 1–20 of the ’315 patent.
`
`At this stage of the proceeding, the Board has not made a final
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`determination as to the patentability of any challenged claim or any
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`underlying factual and legal issues, including claim construction.
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`19
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`IV. ORDER
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`Accordingly, it is:
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` ORDERED that, pursuant to 35 U.S.C. § 314(a), an inter partes
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`review is hereby instituted for the following grounds of unpatentability:
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`Claims 1 and 5 as unpatentable under 35 U.S.C. § 102(b) as
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`anticipated by Dell;
`
`Claims 10 and 16 as unpatentable under 35 U.S.C. § 103(a) over Dell
`
`and Abe;
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`Claims 2–4 and 6–9 as unpatentable under 35 U.S.C. § 103(a) over
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`Dell and JESD21-C; and
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`Claims 11–15 and 17–20 as unpatentable under 35 U.S.C. § 103(a)
`
`over Dell, Abe, and JESD21-C; and
`
`Claims 1 and 5 as unpatentable under 35 U.S.C. § 103(a) over Ooishi
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`and Palaniswami; and
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`Claims 10 and 16 as unpatentable under 35 U.S.C. § 103(a) over
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`Ooishi, Palaniswami, and Abe;
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`FURTHER ORDERED that pursuant to 35 U.S.C. § 314(c) and
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`37 C.F.R. § 42.4, inter partes review of the ’315 patent shall commence on
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`the entry date of this Order, and notice is hereby given of the institution of a
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`trial; and
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` FURTHER ORDERED that no ground other than that specifically
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`provided above is authorized.
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`20
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`IPR2017-02021
`Patent 6,243,315 B1
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`For PETITIONER:
`
`Ryan K. Yagura
`Xin-Yi Zhou
`O’MELVENY & MYERS LLP
`ryagura@
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