United States Patent [191
`Murakami et a1.
`
`[11] Patent Number:
`[45] Date of Patent:
`
`4,467,420
`Aug. 21, 1984
`
`[54] ONE-CHIP MICROCOMPUTER
`[75] Inventors: Jyoji Murakarni, Kawasaki; Tsuyoshi
`Watanabe, Yokohama, both of Japan
`[73] Assignee: Fujitsu Limited, Kawasaki, Japan
`[21] Appl. No.: 359,818
`[22] Filed:
`Mar. 19, 1982
`[30]
`Foreign Application Priority Data
`Mar. 20, 1981 [JP]
`Japan ................................ .. 56-40801
`Mar. 25, 1981 [JP]
`Japan ................................ .. 56-43503
`
`[51] Int. Cl.3 ............................................ .. G06F 13/06
`[52] US. Cl. ................................. .. 364/200
`[58] Field of Search ....................... .. 364/200 MS File
`[56]
`References Cited
`U.S. PATENT DOCUMENTS
`364/200
`4,181,938 l/l980 Suzuki et a1.
`364/200
`4,240,138 12/1980 Chauvel ....... ..
`4,348,720 9/ 1982 Blahut et al. ...................... .. 364/20)
`
`FOREIGN PATENT DOCUMENTS
`2045833 4/1971 Fed. Rep. of Germany .
`
`OTHER PUBLICATIONS
`Funatsu, S. et a1., “Digital Fault Simulation in Bidirec
`
`tional Bus Circuit Environments", IEEE Digest of Pa
`pers, Oct. 1980, pp. 155-157.
`Burton, D. et al., “Know a Microcomputer's Bus Struc
`ture", Electronic Design, vol. 26, No. 13, Jun. 1978, pp.
`78-84.
`Hann et al., “Mikroprozessoren, Mikroprozessrechner,
`und Mikroprozessrechner Systeme”, Elektrie. vol. 32,
`No. 8, 1978, pp. 429-437.
`Chow et al., “MAC-4: A Single-Chip Microcom
`puter", The Bell System Technical Journal, vol. 58, No.
`4, Apr. 1979, pp- 959-962.
`
`Primary Examiner—Raulfe B. Zache
`Attorney, Agent, or Firm-Staas & Halsey
`
`ABSTRACT
`[51]
`A one-chip microcomputer including a central process
`ing unit, a direct memory access controller and a ran
`dom-access memory. In a DMA operation mode, data
`stored in the random-access memory is transmitted
`through common terminals to the exterior by means of
`a time-division control circuit or registers for parallel
`serial conversion. The common terminals are also used
`for a CPU operation mode.
`
`12 Claims, 20 Drawing Figures
`
`Ruiz Food Products, Inc.
`Exhibit 1016
`
`

`

`U.S. Patent
`
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`Ruiz Food Products, Inc.
`Exhibit 1016
`
`

`

`U.S. Patent
`
`Aug. 21, 1984
`
`Sheet 2 of7
`
`4,467,420
`
`
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`Ruiz Food Products, Inc.
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`Exhibit 1016
`
`Ruiz Food Products, Inc.
`Exhibit 1016
`
`

`

`US. Patent Aug. 21, 1984
`
`Sheet 3 of 7
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`4,467,420
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`Ruiz Food Products, Inc.
`Exhibit 1016
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`

`

`US. Patent Aug. 21, 1984
`
`Sheet 4 of7
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`4,467,420
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`Fig. 5
`
`Ruiz Food Products, Inc.
`Exhibit 1016
`
`

`

`US. Patent
`
`Aug. 21, 1984
`
`Sheet 5 of7
`
`4,467,420
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`Ruiz Food Products, Inc.
`
`Exhibit 1016
`
`Ruiz Food Products, Inc.
`Exhibit 1016
`
`

`

`U.S. Patent Aug. 21, 1984
`
`Sheet 6 of?‘
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`4,467,420
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`Fig. 7
`
`REGISTE
`
`SHIFT
`REGISTER
`
`SERIAL
`I/ O_
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`22
`
`23
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`Ruiz Food Products, Inc.
`Exhibit 1016
`
`

`

`US. Patent Aug. 21, 1984
`
`Sheet 7 of7
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`4,467,420
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`24
`
`ADDRESS
`NTER
`
`Ruiz Food Products, Inc.
`Exhibit 1016
`
`

`

`1
`ONE-CHIP MICROCOMPUTER
`
`15
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`BACKGROUND OF THE INVENTION
`The present invention relates to a one~chip mi
`crocomputer.
`In the early seventies, a 4-bit microprocessor, such as
`Intel 4004, which was also called a microcomputer,
`comprised a central processing unit (abbreviated CPU)
`on a single chip. In recent years, however, LSI (Large
`Scale Integration) technology has been developed with
`the result that highly-integrated one-chip microcomput
`ers have been developed. A one-chip microcomputer
`generally comprises a CPU, a random-access memory
`(abbreviated RAM), a read-only memory (abbreviated
`ROM), input/output (abbreviated I/O) ports, a clock
`generator and the like on a single chip. In other words,
`such a one-chip microcomputer has full computer func
`tions on a single chip and, accordingly, cost-perfor
`mance thereof can be greatly improved.
`In a one-chip microcomputer, since the CPU and the
`RAM are connected by interconnections within the
`chip, data transfer between the CPU and RAM cannot
`generally be monitored from the exterior. As a result, it
`is difficult to test the chip and to detect a malfunction
`therein. Therefore, it is necessary to transfer data from
`the RAM to the exterior or vice versa, in order to moni
`tor the CPU operation state.
`Several approaches may be taken to meet the above
`mentioned requirement for one-chip microcomputers.
`One approach is to cause the CPU to perform data
`transfer between the RAM and the exterior. In this case,
`however, the load on the CPU becomes large and, ac
`cordingly, the throughput of the microcomputer is re
`duced. In addition, instruction sequences (programs)
`are ?xed in the ROM and, therefore, the operation state
`of the CPU is unclear. As a result, it is difficult to access
`a desired area of the RAM by the CPU. Another ap
`proach is to use direct memory access (abbreviated
`DMA). That is, under the control of a direct memory
`access controller (abbreviated DMAC) which is set by
`the CPU, the direct transfer of data is provided between
`the RAM and the I/O ports. In this case, however,
`since specialized I/O ports for the DMA operation
`mode are necessary, the number of terminals (pins)
`connected to the I/O ports is increased. For example, in
`the case of an 8-bit parallel transfer system, eight termi
`nals are necessary, which is disadvantageous in prac
`tice. In addition, such additional terminals are generally
`necessary only during the manufacture of the mi
`crocomputer.
`SUMMARY OF THE INVENTION
`It is an object of the present invention to provide a
`one-chip microcomputer which is able to provide direct
`data transfer between a RAM and I/O ports (the exte
`rior) and has a small number of I/O ports.
`According to the present invention, there is provided
`a one-chip microcomputer comprising: a central pro
`cessing unit (CPU) having arithmetic, logic and control
`units; a random-access memory (RAM) for storing in
`termediate data and instructions processed by the cen
`tral processing unit; an output buffer register for storing
`?rst data processed by the central processing unit; a
`direct memory access controller (DMAC), controlled
`by the central processing unit, for reading second data
`from a predetermined area of the random-access mem
`ory; port means for receiving the ?rst data from the
`
`4,467,420
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`output buffer register and the second data of the ran
`dom-access memory read by the direct memory access
`controller; terminals connected to the port means and
`used commonly during a CPU operation mode and a
`DMA operation mode; and time-division means, con
`trolled by the direct memory access controller, for
`transmitting the first and second data through the port
`means to the terminals.
`According to the present invention, there is also pro
`vided a one-chip microcomputer comprising: a central
`processing unit (CPU) having arithmetic, logic and
`control units; a random-access memory (RAM) for
`storing intermediate data and instructions processed by
`the central processing unit; an output buffer register for
`storing ?rst data processed by the central processing
`unit; a direct memory access controller (DMAC) con
`trolled by the central processing unit; gate means con
`trolled by the central processing unit; address port
`means for transmitting an externally applied address
`signal to the random-access memory through the gate
`means so as to read second data from the random-access
`memory; a port means for receiving the first data from
`the output buffer register and the second data of the
`random~access memory read by the address port means;
`terminals connected to the port means and used com
`monly during a CPU operation mode and a DMA oper
`ation mode; and time-division means, controlled by the
`direct memory access controller, for transmitting the
`?rst and second data through the port means to the
`terminals.
`According to the present invention, there is also pro
`vided a one-chip microcomputer comprising: a central
`processing unit (CPU) having arithmetic, logic and
`control units; a random-access memory (RAM) for
`storing intermediate data and instructions processed by
`the central processing unit; a register for storing the
`same data as that of a predetermined area of the ran
`dom-access memory, the write operation upon the reg
`ister and the predetermined area of the random-access
`memory being simultaneously performed by the central
`processing unit; a direct memory access controller
`(DMAC) controlled by the central processing unit;
`parallel-serial converter means, controlled by the cen
`tral processing unit, for converting parallel data into
`serial data, the parallel data being sent from the register
`by the direct memory access controller; and a terminal
`connected to the parallel-serial converter means and
`used commonly during a CPU operation mode and a
`DMA operation mode.
`According to the present invention, there is still fur~
`ther provided a one-chip microcomputer comprising: a
`central processing unit (CPU) having arithmetic, logic
`and control units; a random-access memory (RAM) for
`storing intermediate data and instructions processed by
`the central processing unit; a direct memory access
`controller (DMAC) controlled by the central process
`ing unit; an address counter, controlled by the direct
`memory access controller, for generating an address
`signal so as to read data from the random-access mem
`ory; parallel-serial converter means, controlled by the
`central processing unit, for converting parallel data into
`serial data, the data of the random-access memory ac
`cessed by the address counter being set in the parallel
`serial converter means; and a terminal connected to the
`parallel-serial converter means and used commonly
`during a CPU operation mode and a DMA operation
`mode.
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`Ruiz Food Products, Inc.
`Exhibit 1016
`
`

`

`3
`The present invention will now be more clearly un
`derstood from the description as set forth below with
`reference to the accompanying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a block diagram of a ?rst embodiment of a
`one-chip microcomputer according to the present in
`vention;
`FIGS. 2A and 2B are timing diagrams of signals ap
`pearing in the circuit of FIG. 1;
`FIG. 3 is a block diagram of a second embodiment of
`the one-chip microcomputer according to the present
`invention;
`FIGS. 4A through 4C are timing diagrams of signals
`appearing in the circuit of FIG. 3;
`FIG. 5 is a block diagram of a third embodiment of
`the one-chip microcomputer according to the present
`invention;
`FIGS. 6A through 6] are timing diagrams of the
`signals appearing in the circuit of FIG. 5;
`FIG. 7 is a block diagram of a fourth embodiment of
`the one-chip microcomputer according to the present
`invention, and;
`FIG. 8 is a block diagram of a ?fth embodiment of the
`one-chip microcomputer according to the present in
`vention.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`In FIG. 1, is a ?rst embodiment of the one-chip mi
`crocomputer according to the present invention, 1 is a
`central processing unit (CPU) having arithmetic, logic
`and control units; 2 is a direct memory access controller
`(DMAC) which is set by the CPU 1; 3 is a random-ac
`cess memory (RAM) for storing intermediate data and
`instructions processed by the CPU 1; 4 is a output buffer
`register for storing output data processed by the CPU 1;
`5 is a time-division control circuit controlled by the
`DMAC 2; 6-0, 6-1, .
`.
`. , 6-7 are I/O ports; 7 is a data bus;
`and 8 is an address bus. The RAM 3 has a data bus 9 for
`a direct memory access (DMA) operation mode. All the
`elements of FIG. 1 are formed on a single semiconduc
`tor chip.
`During a CPU operation mode, output data (which is
`referred to as CPU output data) is stored in the output
`buffer register 4 and, after that, the CPU output data is
`transferred through the ports 6-0, 6-1, .
`.
`.
`, 6-7 and
`terminals P0, P1, .
`.
`.
`, P7 to the exterior. However,
`during the DMA operation, output data (which is re
`ferred to as DMA output data) is read out of a predeter
`mined area of the RAM 3 to the DMA data bus 9 by the
`DMAC 2. In this case, the predetermined area is com
`prised of one word or eight bits. The DMA output data
`is also transferred through the ports 6-0, 6-1, . .
`.
`, 6-7
`and the terminals P9, P1, .
`.
`. , P7 to the exterior. Time
`division control for this type of output data is per
`formed by the time-division control circuit 5 which is
`also controlled by the DMAC 2.
`In more detail, the time-division control circuit 5,
`which is controlled by the DMAC 2, generates a clock
`signal Tl as illustrated in FIG. 2A, its inverted signal T1
`and a clock signal T2 is illustrated in FIG. 2B. In this
`case, the difference in phase between the clock signals
`T1 and T2 is about 90 degrees. Such clock signals T1 and
`T; can be easily formed by using a reference signal of a
`reference clock generator and frequency dividers (not
`shown). On the other hand, each of the ports 6-0, 6-1, .
`.
`. , 6-7 comprise two AND gates G1 and G2, and an OR
`
`4,467,420
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`gate G3. Each gate G1 transmits the CPU output data
`from the output buffer register 4 to the exterior when
`the potential of the clock signal T1 is high, while each
`gate G2 transmits the DMA output data from the RAM
`a to the exterior when the potential of the clock signal
`T1 is high. Thus, the CPU output data and the DMA
`output data are alternately transmitted through the
`ports 6-0, 6-1, . . . , 6-7 and the terminals P0, P1, . .
`.
`, P7
`to the exterior.
`It should be noted that the read operation timing of
`the DMAC 2 for the RAM 3 is in synchronization with
`the high potential of the clock signal T1.
`Next, the separation of the CPU data and the DMA
`data will be explained. In an external circuit (not
`shown), when the data at the terminals P0 through P7 is
`read based on the fall of the potential of the clock signal
`T2 output at the terminal P3, the CPU output data is
`obtained. However, when the data at the terminals P0
`through P7 is read based on the rise of the potential of
`the clock signal T2, the DMA output data is obtained.
`FIG. 3 is a block diagram illustrating a second em
`bodiment of the one-chip microcomputer according to
`the present invention. In FIG. 3, an address counter 10,
`a DMA address bus 11, an OR gate 12 and a NOR gate
`13 are added to FIG. 1. In addition, the time-division
`control circuit 5 generates an inverted signal T2 of the
`clock signal T1 for a terminal P9. The DMAC 2 in
`creases the count of the address counter 10 which gen
`erates an address signal for the DMA address bus 11.
`Therefore, a plurality of words which serve as the
`DMA data are read out of the RAM 3 to the DMA data
`bus 9. For example, if the address counter 10 comprises
`4 bits, eight words allocated by addresses “0”, “l”, “2",
`. . . , “7" can be read out from the RAM 3.
`The CPU data and the DMA data are alternately
`transmitted through the ports 6-0, 6-1, .
`.
`.
`, 6-7 to the
`terminals P0, P1, . . . , P7, in the same way as in FIG. 1.
`In this case, however, it is necessary to know the ad
`dress of a DMA output data (word) transmitted at the
`terminals P0, P1, .
`.
`. , P7. For this purpose, a terminal
`P9 is provided.
`The output potential of the OR gate 12 is low only
`when the value of the address counter 10 is 00 .
`.
`. 0
`(=“0"). In addition, as illustrated in FIGS. 4A, 4B and
`4C, the output potential T3 of the NOR gate 13 is hig_h
`only when the potential of each of the signals T1 and T2
`and the value of the address counter 10 is “0”. There
`fore, the value of the address counter 10 can be read by
`providing an appropriate external counter (now
`shown). That is, the external counter is reset by the rise
`of the potential T3 at the terminal P9 and increases by
`one count based on the rise of the potential T2.
`FIG. 5 is a block diagram illustrating a third embodi
`ment of the one-chip microcomputer according to the
`present invention. In FIG. 5, terminals P11 through P19,
`an address port 14, the gates Gil through G19 are pro
`vided to access the RAM 3 directly from the exterior
`during the DMA operation mode. Each of the ports 6-0,
`6-1, .
`. . , 6-7, which comprise six gates G; through G6,
`is bidirectional. The bidirectional I/O ports 6-0, 6-1, . .
`.
`, 6-7 are connected to a DMA write data bus 15. D
`type ?ip-flops 16 and 17, and an AND gate 18 are pro
`vided for a permission signal T7, which permits a DMA
`read or write operation.
`In more detail, based on the rise of the potential of the
`signal T1, as illustrated in FIG. 6A, the ?ip-?op 16
`inputs the potential of signal T4, as illustrated in FIG.
`6D, which is generated by the CPU 1. As a result, the
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`Ruiz Food Products, Inc.
`Exhibit 1016
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`

`4,467,420
`6
`a 5
`flip-flop 16 generates a signal T5, as illustrated in FIG.
`the DMAC 2 increases the count of the address counter
`6B. Further, by the rise of the potential of the signal T!
`24, so that one word data (8 bits) is read out of the RAM
`3 into the shift register 22. Next, a shift clock signal
`as illustrated in FIG. 6B, the ?ip-?op 17 stores the sig
`generated from a clock signal generator (not shown) is
`nal T5, and, accordingly, the ?ip-?op 17 generates a
`supplied to the shift register 22, so that the shift opera
`signal T6, as illustrated in FIG. 6F. Therefore, the per
`mission signal T7 generated from the AND gate 18,
`tion is performed on the shift register 22, in the same
`which receives the signals T1 and T5, is illustrated in
`way as in FIG. 7. For example, if the address counter 10
`comprises 4 bits, eight words allocated by the addresses
`FIG. 66.
`During the DMA read or write operation mode, the
`“0”, "l", . . . , "7” can be read out of the RAM 3 to the
`shift register 22.
`potential of each of the signals T4 and T7 is low and
`high, respectively. As a result, the gates G11 through
`In FIGS. 7 and 8, the DMAC 2 includes division
`means similar to those used in the previous examples to
`G19 are opened so that the address port 14 accesses the
`RAM 3 by supplying an externally-applied address
`control, via the CPU 1, whether the ?rst data is fed
`signal. In addition, during the DMA read operation
`from the serial input/output circuit 23 to the shift regis
`ter 22 or the second data is fed from the register 21 (or
`mode, the potential of a read/ write signal R/W applied
`the RAM 3) to the shift register 22.
`to a terminal P10 is caused to be high, so as to open gate
`Note that, in FIGS. 7 and 8, the DMA operation
`G4 of each port 6-(], 6-1, . .
`. , 6-7. As a result, the ports
`wherein the data is set in the shift register 22 by the
`6-0, 6-1, . . . , 6-7 transmit the DMA data from the RAM
`DMAC 2 is never superposed with the CPU operation
`3 to the exterior. In this case, for a time-period during
`wherein the shift operation is performed upon the shift
`which the potentials of each of the signals T4 and T7 are
`register 22.
`high and low, respectively, the CPU data is transmitted
`As explained hereinbefore, the present invention has
`from the output buffer register 4 through the ports 6-0,
`an advantage in that direct data transfer between the
`6-1, .
`.
`. , 6-7 to the exterior. This type of data, that is,
`RAM and the exterior can take place without increasing
`DMA data and CPU data, can be discriminated be
`the number of terminals.
`tween by the signal T2 obtained at the terminal Pg, as
`illustrated in FIG. 6C. In such a DMA read mode,
`>
`We claim:
`1. A one-chip microcomputer having a direct mem
`when address signals A, B, .
`.
`. are supplied to the ad
`ory access and central processing unit operation mode,
`dress port 14, as illustrated in FIG. 6H, DMA read data
`comprising:
`RA, RB, . .
`. are obtained at the terminal Pu through P1,
`a central processing unit having arithmetic, logic and
`as illustrated in FIG. 61.
`control units, for setting the direct memory access
`On the other hand, during the DMA write operation
`operation mode or central processing unit opera
`mode, the potential of the signal R/W is caused to be
`tion mode and for processing ?rst and second data;
`low, to close the gate G4 of each port 641, 6-1, . . . , 6-7.
`a random-access memory, operatively connected to
`Therefore, write data applied to the terminals P0, P1, . .
`said central processing unit, for storing the second
`. , P7 is written into an area of the RAM 3 accessed by
`data in a predetermined area and instructions pro
`the address port 14. In this case, as illustrated in FIGS.
`cessed by said central processing unit;
`6H and 61, write data WA, WB, WC, .
`.
`. is applied
`an output buffer register, operatively connected to
`simultaneously with the corresponding address A, B, C,
`said central processing unit, for storing the ?rst
`data processed by said central processing unit;
`a direct memory access controller, operatively con
`nected to and controlled by said central processing
`unit, for reading out the second data from the pre
`determined area of said random-access memory;
`port means, operatively connected to said output
`buffer and said random access memory, for receiv
`ing the ?rst data from said output buffer register
`and the second data, from said random-access
`memory;
`terminals operatively connected to said port means
`and used for the central processing unit operation
`mode and the direct memory access operation
`mode; and
`time-division means, operatively connected to said
`direct memory access controller and said port
`means and controlled by said direct memory access
`controller, for transmitting the ?rst and second
`data through said port means to said terminals.
`2. A one-chip microcomputer as set forth in claim 1,
`further comprising an address counter, operatively con
`nected to said direct memory access controller and said
`random access memory and controlled by said direct
`memory access controller, for generating an address
`signal to read the second data from the predetermined
`area of said random-access memory.
`3. A one-chip microcomputer having a direct mem
`ory access and central processing unit mode, compris
`ing:
`
`FIG. 7 is a block diagram illustrating a fourth em
`bodiment of the one-chip microcomputer according to
`the present invention. In FIG. 7, 21 is a resister for '
`storing the same data as that of a predetermined area of
`the RAM 3. That is, when the CPU 1 performs a write
`operation upon the predetermined area of the RAM 3,
`the CPU 1 also performs the same write operation upon
`the register 21. Therefore, the data of the register 21 is
`always the same as that of the predetermined area of the
`RAM 3.
`-
`During the DMA read operation mode, the DMAC
`2, which is set by the CPU 1, transmits the contents of
`the register 21 to a shift register 22. Next, a shift clock
`signal generated from a clock generator (not shown) is
`supplied to the shift register 22, so that the shift opera
`tion is performed upon the shift register 22. Therefore,
`the parallel data stored in the register 21 is converted
`into serial data which is transmitted through a terminal
`P21 to the exterior.
`It should be noted that the above-mentioned prede
`termined area of the RAM 3 comprises a word (8 bits)
`allocated to one address. In addition, the predetermined
`area can comprise at least one predetermined bit (i.e., a
`bit slice) of predetermined data words which are, for
`example, allocated by addresses “0”, “1", . . . , “7".
`FIG. 8 is a block diagram illustrating a ?fth embodi
`ment of the one-chip microcomputer according to the
`present invention. In FIG. 8, an address counter 24 is
`provided instead of the register 21 of FIG. 7. That is,
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`Ruiz Food Products, Inc.
`Exhibit 1016
`
`

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`a central processing unit having arithmetic, logic and
`parallel-serial converter means, operatively con
`nected to said central processing unit, said random
`control units, for setting the direct memory access
`operation mode or central processing unit opera
`access memory and said direct memory access
`tion mode, and for processing ?rst and second data;
`controller, and controlled by said central process
`ing unit, for converting parallel data into serial
`a random-access memory, operatively connected to
`data, said parallel data being sent from said register
`said central processing unit, for storing the second
`by said direct memory access controller; and
`data in a predetermined area and instructions pro
`cessed by said central processing unit;
`a terminal operatively connected to said parallel
`an output buffer register, operatively connected to
`serial converter means and used for the central
`processing unit operation mode and the direct
`said central processing unit and said random access
`memory, for storing the ?rst data processed by said
`memory access operation mode.
`6. A one-chip microcomputer as set forth in claim 5,
`central processing unit;
`‘
`wherein said parallel-serial converter means comprises:
`a direct memory access controller operatively con
`a shift register, operatively connected to said register
`nected to and controlled by said central processing
`unit;
`and said direct memory access controller, for re
`ceiving parallel data from said register; and '
`gate means, operatively connected to said random
`a serial input/output circuit, operatively connected to
`access memory and said central processing unit, for
`passing signals therethrough and controlled by said
`said central processing unit, said shift register, and
`central processing unit;
`said random access memory, and controlled by said
`central processing unit, for performing a shift oper
`address port means, operatively connected to said
`ation upon said shift register.
`gate means, for transmitting an externally applied
`7. A one-chip microcomputer as set forth in claim 5,
`address signal to said random-access memory
`wherein the predetermined area of said random-access
`through said gate means to read the second data
`memory comprises at least one predetermined bit of
`from said random-access memory;
`predetermined data words.
`port means, operatively connected to said output
`8. A one-chip microcomputer having a central pro
`buffer register and said random access memory, for
`cessing unit and data memory access operation mode,
`receiving the ?rst data from said output buffer
`comprising:
`register and the second data from said random-ac
`a central processing unit having arithmetic, logic and
`cess memory read under the control of said address
`control units for setting direct memory access or
`port means;
`central processing unit operation modes, and for
`terminals operatively connected to said port means
`processing first and second data;
`and used for the central processing unit operation
`a random-access memory, operatively connected to
`mode and the direct memory access operation
`said central processing unit, for storing the second
`mode; and
`data and instructions processed by said central
`time-division means, operatively connected to said
`processing unit;
`direct memory access controller and said port
`a direct memory access controller operatively con
`means and controlled by said direct memory access
`nected to and controlled by said central processing
`controller, for transmitting the ?rst and second
`unit;
`data through said port means to said terminals.
`an address counter, operatively connected to said
`4. A microcomputer as set forth in claim 3, wherein
`said port means comprises bidirectional input/ output
`random access memory and said direct memory
`access controller and controlled by said direct
`ports, operatively connected to said random access
`memory access controller for generating an ad
`memory and said output buffer register, through which
`dress signal for said random-access memory;
`an externally applied data signal is written into an area
`parallel-serial converter means, operatively con
`of said random-access memory accessed under the con
`nected to said central processing unit and said ran
`trol of said address port means.
`dom access memory, and controlled by said central
`5. A one-chip microcomputer, having a central pro
`processing unit, for converting parallel data into
`cessing unit and direct memory access mode, compris
`serial data, the data of said random-access memory
`ing:
`.
`accessed under the control of said address counter
`a central processing unit having arithmetic, logic and
`‘being input into said parallel-serial converter
`control units for setting the direct memory access
`or central processing unit operation mode, and for
`means; and
`a terminal operatively connected to said parallel
`processing ?rst and second data;
`serial converter means and used for the central
`a random-access memory, operatively connected to
`processing unit operation mode and direct memory
`said central processing unit, for storing the second
`access operation mode.
`data in a predetermined area and instructions pro
`9. A one-chip microcomputer as set forth in claim 8,
`cessed by said central processing unit;
`wherein said parallel-serial converter means comprises:
`a register, operatively connected to said random ac
`a shift register operatively connected to said random
`cess memory and said central processing unit,,for_
`access memory and said central processing unit, for
`storing the same data as that in said predetermined
`receiving parallel data from said random-access
`area of said random-access memory, a write opera
`memory; and
`tion upon said register and said predetermined area
`a serial input/output circuit, operatively connected to
`of said random-access memory being simulta
`said shift register, said central processing unit, and
`neously performed by said central processing unit;
`said random access memory and controlled by said
`direct memory access controller operatively con
`central processing unit, for performing a shift oper
`nected to said central processing unit and said reg
`ation on said shift register.
`ister and controlled by said central processing unit;
`
`45
`
`55
`
`60
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`65
`
`Ruiz Food Products, Inc.
`Exhibit 1016
`
`

`

`4,467,420
`
`9
`10. A one-chip microcomputer'as set forth in claim 3,
`further comprising ?ip-?ops, operatively connected to
`said time division means and said terminals, for provid
`ing a permission signal to permit the direct memory
`access operation mode.
`11. A one-chip microcomputer as set forth in claim 1,
`wherein said port means comprises input/output ports,
`operatively connected to the respective said terminals,
`
`5
`
`10
`said random access memory and said output buffer,
`each port means comprising:
`two AND gates each operatively connected to said
`output buffer and said random access memory; and
`an OR gate operatively connected between said two
`AND gates and the respective said terminal.
`12. A one-chip microcomputer as set forth in claim 1,
`wherein said time division means comprises inverters
`operatively connected to said port means and said direct
`10 memory access controller.
`ll
`i
`t t i
`
`25
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`30
`
`35
`
`45
`
`55
`
`65
`
`Ruiz Food Products, Inc.
`Exhibit 1016
`
`