`
`MT48LC4M4R1(S)
`4 MEG x 4 SDRAM
`
`SYNCHRONOUS
`
`4 MEG x 4SDRAM
`
`DRAM
`
`Pulsed RAS, Dual Bank,
`BURST Mode, 3.3V, SELF REFRESH
`
`ADVANCE
`
`PIN ASSIGNMENT (Top View)
`
`44-Pin TSOP
`FORWARD
`
`(DD-7)
`
`
`23
`
`NC
`V00
`
`3
`
`N-
`
`(customary
`
`43
`44
`42
`40
`39
`33
`37
`36
`35
`34
`33
`32
`31
`30
`29
`25
`26
`25
`24
`
`MT48C4M4R1TG
`
`
`
`INVHCISflONOHHONAS
`
`FEATURES
`Fully synchronous; all signals (excluding clock enable)
`registered to positive edge of system clock
`0 Meets all IEDEC functional specifications
`0 Dual internal banks: dual 2 Meg x 4 architecture
`Programmable burst—lengths: 2, 4, 8 cycles or full~page
`burst
`
`Programmable burst-sequence: sequential or interleave
`Burst termination
`
`Multiple burst READ, single WRITE capability
`Hidden precharge capability with optional automatic
`precharge command
`Programmable READ latency: 1, 2 or 3 clocks
`Industry-standard x8 pinouts, timing, functions and
`packages
`Refresh modes: AUTO and SELF
`Standard and extended AUTO REFRESH rates
`
`High-performance CMOS silicon-gate process
`Lead—over-chip assembly architecture
`Single +3.3V $0.3V power supply
`Low power, 3mW standby; ZOOmW active, typical
`LVTTL—compatible
`CKE—controlled power-down and suspend operations
`Mode register programming
`JEDEC-standard command set (pulsed RA—S)
`OPTIONS
`MARKING
`Timing
`(S100 MHz)
`10ns access
`( $83 MHz)
`12ns access
`13.3ns access ( 575 MHz)
`~ Auto Refresh
`
`-10
`—12
`-13
`
`(15.6us/ row)
`4,096—cycle in 64ms
`4,096-cycle in 128ms (31.25us/row)
`. SELF REFRESH
`Not allowed
`Allowed
`
`none
`5
`
`none
`5
`
`0 Plastic Packages
`TC
`44-pin TSOP (400 mil)——forward
`0 Part Number Example: MT48LC4M4R1TG-10 S
`
`with a synchronous interface. Each byte is uniquely ad—
`dressed through a bank-select bit and 20 address bits. The
`bank select and address are entered first byWregistering
`
`(row active command) 12 bits (AD—A10, BA) and then
`CAS registering 11 bits (AO-A9, BA). At C_AS_registration
`(READ or WRITE command), address bit A10 defines auto-
`precharge state (active HIGH). Bank selection is controlled
`by BA during both REand C—AS—registration.
`The MT48LC4M4R1 is designed to operate in a synchro-
`nous, 3.3V memory system. All input and output signals,
`with the exception of clock enable (CKE) during POWER—
`DOWN and SELF REFRESH modes, are synchronized to
`the positive-going edge of the system clock (CLK).
`The synchronous DRAM has several programmable fea-
`tures to allow maximum performance in each user’s system.
`Additionally, bank switching between the two internal
`memory banks in conjunction with the programmable
`GENERAL DESCRIPTION
`BURST mode provides very high-speed performance.
`The MT48LC4M4R1(S) is a randomly accessed, solid-
`The synchronous DRAM allows both AUTO REFRESH
`(during normal operation) and SELF REFRESH (for low-
`state memory containing 16,777,216 bits organized in a x4
`power, data-retention operation).
`configuration. It is structured as a dual 2 Meg x 4 DRAM
`
`MTIBLC4M4HI (S)
`Micron Semiconductor, Inc, reserves the right to change [>thth 01 specmcations Without notice.
`REV 4/94
`
`2-1
`
`HP Exhibit 1008 - Page»
`
`HP Exhibit 1008 - Page 1
`
`

`

`MICHDN
`.,
`
`4 MEG X 4 SDRAM
`
`MT48LC4M4R1(S)
`
`ADVANCE
`
`FUNCTIONAL BLOCK DIAGRAM
`
`DATA-IN
`
`- DQM
`
`BUFFER
`
`DATA-OUT
`
`. 001
`- 002
`- DQa
`' 004
`
`3 Lu
`< C'
`E 8
`0 g
`0
`
`fiéé
`
`52:
`
`REFRESH
`CONTROLLER
`
`REFRESH
`OSCILLATOR
`and TIMER
`
`Row‘
`ADDRESS
`BUFFEFIS
`
`(If)
`E5
`D 8
`5 LIJ
`0 E
`o
`<
`
`
`
`INVHGSDONOHHONASI
`
`CKE '
`CLK -
`
`BA.
`
`A10
`A9
`A8
`A7
`A6
`A5
`A4
`A3
`A2
`A1
`A0
`
`4—0 Vcc
`
`¢—o Vss
`
`no.1 CLOCK
`GENERATOR
`
`
`
` E
`
`MT48LC4M4RHS)
`REV 6/94
`
`
`MTcron Semiconducmr Inc reserves the right to change pmmms or specincan'ons wvlhout nmice.
`2HP Exhibit 1008- Page QWW
`
`
`BUFFER
`9o
`
`
`O_l
`_I
`0
`
`
`E
`
`I-
`z
`E
`3
`BANKO
`8
`
`E 8
`MEMORY
`
`3 o
`ARRAY
`LUD
`
`
`I]:
`CC
`
`E
`E
`$7710“an
`
`
`S . ER
`COLUMN
`8 ; 3 <0
`DECODER
`
`5' {3
`._
`E
`0 '1
`~1024~
`3
`8
`on
`
`
`GENERATOR
`
`<
`
`MULTIPLEXER
`
`NO. 2 CLOCK
`
`
`ADDRESS
`LATCH
`
`BANK1
`ROW-
`E o
`MEMORY
`O o
`ADDRESS
`m 0
`ARRAV
`BUFFERS
`E
`
`HP Exhibit 1008 - Page 2
`
`