(12) United States Patent
`Goodman
`
`US006243315B1
`(10) Patent No.:
`US 6,243,315 B1
`(45) Date of Patent:
`Jun. 5, 2001
`
`(54) COMPUTER MEMORY SYSTEM WITH A
`LOW POWER DOWN MODE
`
`(76) Inventor: James B. Goodman, 4750 Pear Ridge
`Dr., Apt 9301, Dallas, TX (US) 75287
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(*) Notice:
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`#: . º * soso22
`4901.283
`2/1990 Hanbury.
`5,089,993
`2/1992 Neal .
`5,222,044
`6/1993 Tsujimoto .
`5,262,998
`11/1993 Mnich .
`5,784,628
`7/1998 Reneris .
`
`8/1998 Heyden .
`5,798,961
`10/1998 Tran .
`5,818,299
`7/1999 Rao .
`5,920,885
`* cited by examiner
`Primary Examiner—Huan Hoang
`(74) Attorney, Agent, or Firm—David Fink
`(57)
`ABSTRACT
`A memory system for use in a computer system, includes a
`plurality of volatile solid state memory devices that retain
`(21) Appl. No.: 09/477,920
`information when an electrical power source is applied to
`-
`the memory devices within a predetermined voltage range,
`(22) Filed:
`Dec. 31, 1999
`
`(51) Int. Cl." … G11C 7/00 and are capable of being placed in a self refresh mode. The
`(52) U.S. Cl. .................... 365.222; 365,230,03, 365,229,
`memory devices have respective address and control lines,
`2
`365753
`and a control device for selectively electrically isolating the
`(58) Field of Search
`36.5/222, 51, 63
`memory devices from respective address lines and respec
`--------------------------- 365/52 230 03 229
`tive control lines so that when the memory devices are
`2
`• *-* >
`electrically isolated, any signals received on the respective
`address lines and respective control lines do not reach the
`memory devices. The memory system includes a memory
`access enable control device coupled to the control device
`and to the control lines for determining when the memory
`system is not being accessed, and for initiating a low power
`mode for the memory system wherein the control device
`electrically isolates the memory devices and places the
`memory devices in the self refresh mode.
`
`20 Claims, 59 Drawing Sheets
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`30
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`36
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`38
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`HP Exhibit 1001 - 1
`
`

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`U.S. Patent
`
`Jun. 5, 2001
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`Sheet 1 of 59
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`US 6,243,315 B1
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`36
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`FIG. 1
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`HP Exhibit 1001 - 2
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`U.S. Patent
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`Jun. 5, 2001
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`Sheet 2 of 59
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`US 6,243,315 B1
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`U.S. Patent
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`Jun. 5, 2001
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`Jun. 5, 2001
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`Jun. 5, 2001
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`Jun. 5, 2001
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`US. Patent
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`U.S. Patent
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`Jun. 5, 2001
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`Jun. 5, 2001
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`Jun. 5, 2001
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`Jun. 5, 2001
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`U.S. Patent
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`Jun. 5, 2001
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`Sheet 18 of 59
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`US 6,243,315 B1
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`Jun. 5, 2001
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`Jun. 5, 2001
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`Sheet 24 of 59
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`Jun. 5, 2001
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`Sheet 25 of 59
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`Jun. 5, 2001
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`Sheet 26 of 59
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`US 6,243,315 B1
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`U.S. Patent
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`Jun. 5, 2001
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`Sheet 27 of 59
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`US 6,243,315 B1
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`HP Exhibit 1001 - 28
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`U.S. Patent
`US. Patent
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`Jun. 5, 2001
`Jun. 5, 2001
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`Sheet 28 of 59
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`HP Exhibit 1001 - 29
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`U.S. Patent
`US. Patent
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`Jun. 5, 2001
`Jun. 5, 2001
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`Sheet 29 of 59
`Sheet 29 0f 59
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`US 6,243,315 B1
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`U.S. Patent
`US. Patent
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`Jun. 5, 2001
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`Sheet 31 of 59
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`U.S. Patent
`US. Patent
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`Jun. 5, 2001
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`US. Patent
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`U.S. Patent
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`Jun. 5, 2001
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`US. Patent
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`U.S. Patent
`US. Patent
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`Jun. 5, 2001
`Jun. 5, 2001
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`Sheet 39 of 59
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`U.S. Patent
`US. Patent
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`Jun. 5, 2001
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`Sheet 40 0f 59
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`U.S. Patent
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`Jun. 5, 2001
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`Sheet 41 of 59
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`US. Patent
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`Jun. 5, 2001
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`HP Exhibit 1001 - 44
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`US. Patent
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`Jun. 5, 2001
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`Sheet 44 0f 59
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`U.S. Patent
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`Jun. 5, 2001
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`Sheet 45 of 59
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`US 6,243,315 B1
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`Jun. 5, 2001
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`Sheet 47 of 59
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`U.S. Patent
`US. Patent
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`Jun. 5, 2001
`Jun. 5, 2001
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`Sheet 48 of 59
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`US. Patent
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`Jun. 5, 2001
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`Sheet 49 0f 59
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`U.S. Patent
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`Jun. 5, 2001
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`Sheet 50 of 59
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`US 6,243,315 B1
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`US. Patent
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`Jun. 5, 2001
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`Sheet 51 0f 59
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`U.S. Patent
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`Jun. 5, 2001
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`Sheet 52 of 59
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`U.S. Patent
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`Jun. 5, 2001
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`Sheet 53 of 59
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`US 6,243,315 B1
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`U.S. Patent
`US. Patent
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`Jun. 5, 2001
`Jun. 5, 2001
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`Sheet 54 of 59
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`

`

`U.S. Patent
`US. Patent
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`Jun. 5, 2001
`Jun. 5, 2001
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`Sheet 55 of 59
`Sheet 55 0f 59
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`US 6,243,315 B1
`US 6,243,315 B1
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`FIG. 7./
`FIG. 7J
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`HP Exhibit 1001 - 56
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`HP Exhibit 1001 - 56
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`U.S. Patent
`US. Patent
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`Jun. 5, 2001
`Jun.5,2001
`
`Sheet 56 of 59
`Sheet56 0f59
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`US 6,243,315 B1
`US 6,243,315 B1
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`FIG. 7L
`FIG. 7L
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`EH’EXhflflthOl-57
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`HP Exhibit 1001 - 57
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`

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`U.S. Patent
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`Jun. 5, 2001
`
`Sheet 57 of 59
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`US 6,243,315 B1
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`
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`O O oO O
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`FIG. 7M
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`FIG. 7N
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`HP Exhibit 1001 - 58
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`U.S. Patent
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`Jun. 5, 2001
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`Sheet 58 of 59
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`US 6,243,315 B1
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`HP Exhibit 1001 - 59
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`U.S. Patent
`US. Patent
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`Jun. 5, 2001
`Jun. 5, 2001
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`Sheet 59 of 59
`Sheet 59 0f 59
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`US 6,243,315 B1
`US 6,243,315 B1
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`HP Exhibit 1001 - 6O
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`HP Exhibit 1001 - 60
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`US 6,243,315 B1
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`1
`COMPUTER MEMORY SYSTEM WITH A
`LOW POWER DOWN MODE
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`STATEMENT RELATED TO GOVERNMENT
`FUNDED RESEARCH AND DEVELOPMENT
`Not Applicable
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`BACKGROUND
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`power down time period to too small a value can actually
`decrease battery life as the need to access the disk drive
`requires the disk drive be returned to a fully spinning
`condition. This return to a fully spinning condition can
`sometimes require more power than would be required to
`maintain the disk drive in the full spin operational mode.
`Computer systems contain different forms of semicon
`ductor memory used to store programs and data. The most
`common of these memories are Programmable Read-Only
`Memory (PROM), EPROM (Erasable PROM), EEPROM
`(Electrically Erasable PROM), FLASH and volatile solid
`state memory devices which maintain information only
`when a predetermined voltage is applied to them typically
`used for Random Access Memory (RAM). PROM memory
`is a memory where the contents, stored as a series of logical
`highs and lows(1 and 0) are permanently stored and
`unchangeable. When power is removed from the computer
`system, PROM memory retain the series of logical highs and
`lows stored within it. Similarly, EPROMs and EEPROMs,
`permanently retain the data stored with their memory, but
`have the capability to erase the logical highs and lows and
`replace the memory contents with new and different data
`patterns. Typically the EPROMs use Ultra-violet light as an
`eraser means, and EEPROMs uses electrical means as the
`€?äSè?.
`FLASH memory is similar to EEPROM memory. In each
`of these memory types, the storage of the data or programs
`in these memories is permanent, whether power is applied to
`the computer system or not. Such memory is referred to as
`non-volatile memory. As an example, Computer BIOS
`(Basic Input/Output Sequence) programs are stored in some
`form of PROM; where the older computer systems had
`BIOS program stored in EPROM, more current computer
`systems retain the BIOS in FLASH to allow for reprogram
`mability. When power is applied, the program stored in the
`BIOS begins the sequence to load the full operational
`program (such as Windows 3.11 or Windows95/NT) into the
`computer memory. PROM memory is used when size and
`power consumption are not critical factors, the program
`instructions do not change often and the program instruc
`tions are required to remain independent of the input power
`State.
`Unlike PROM, Random Access Memory, for example
`DRAM or any solid state volatile memory device that
`maintains information when a voltage is applied to it, is used
`in a computer system when the program instruction changes
`often and the need for data retention is generally for a short
`period of time. Application programs, such as WORDPER
`FECT (TRADEMARK), Microsoft Word (TRADEMARK),
`and Lotus 123 (TRADEMARK) are programs loaded into
`computer RAM when they are to be executed and remain in
`RAM through the period of execution. Examples commonly
`used RAM memory include devices Static (SRAM) and
`Dynamic (DRAM). Both SRAM and DRAM retain the
`contents of their memory states when electrical power is
`provided and maintained on the devices. Whenever electri
`cal power is removed from the devices, the memory contents
`of the device is lost and irretrievable. Memory systems that
`lose their data when electrical power is removed are called
`“volatile memories” in the art. When electrical power is
`intentionally removed, such as in an orderly shutdown of the
`computer system, there is no intent to retain RAM contents.
`But when the electrical power is unintentionally and unex
`pectedly removed, such as in cases of power outages, the
`lose of the contents of the RAM could be devastating.
`To protect the contents of the RAM memory under such
`unexpected conditions, it has become a common practice to
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`1. Field of the Invention
`This invention relates to a computer system including a
`central processing unit (CPU) memory system to retain data
`and to conserve electrical power by utilizing volatile solid
`state memory devices, such as DRAM (Dynamic Random
`Access Memory) semiconductor memory chips capable of
`retaining data, in a low power, self refresh mode whenever
`the memory system is not being accessed by the CPU.
`In addition, the invention relates to a CPU and a memory
`system wherein the retention of data within a volatile solid
`state memory device is maintained in a self refresh mode by
`an internal power supply during times when an external
`power supply voltage falls below a predetermined level.
`2. Prior Art
`Current computer systems consume relatively large
`amounts of electrical energy to power the components
`comprising the computer system, thereby making demands
`on batteries used in portable computer systems. Sources of
`this energy consumption are the microprocessor computer
`chip, the volatile memory modules that retain information as
`long as a voltage is applied to them, and usually a hard disk
`drive and CD-ROM drive. The increase in computer chip
`speeds and increase memory module sizes each also increase
`demand for electrical energy. Hard disk drives and CD
`drives which continuously spin whenever the computer
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`system is “powered on’ are a substantial and constant source
`of battery energy. Successive generations of portable, laptop
`or notebook computers contain computer chips which per
`form at higher operating speeds, or contain more memory, or
`larger hard disk drive capacity. Each of these additions to the
`computer system increases the demand on the electrical
`power source and shorten the use of battery operation.
`The batteries contain a limited amount of electrical energy
`to supply the electrical demands of the portable, laptop or
`notebook computer system. Larger batteries contain the
`capacity to provide electrical energy for a longer time than
`smaller batteries. However, as battery size increases to
`compensate for the increased electrical demands the weight
`of the portable, laptop or notebook computer also increases.
`Computer designers must continually trade off electrical
`power capacity against overall computer system weight.
`Power Management methods and tools are designed in
`current portable, laptop and notebook computers to conserve
`battery power. Such methods and tools include, operating
`the computer chips on lower voltage than the standard 5 volt
`logic (operation on a reduced voltage also reduces the heat
`generated in portable, laptop or notebook computer
`systems), placing the computer chip in suspended or deep
`sleep mode when the computer chip detects no activity for
`a predetermined period of time, and powering down the hard
`disk drive after a user defined time period.
`These methods and tools, while increasing battery life
`also have disadvantages. The methods and tools are essen
`tially time based. Under such a time based system access to
`the peripheral devices, such as hard disk drives, could be
`denied as the peripheral device could itself be in a power
`down, or power savings mode. Further, setting the disk drive
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`HP Exhibit 1001 - 61
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`25
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`use an external Uninterrupted Power Supply(UPS) to main
`tain electrical power to the computer system during the such
`unexpected power outages. The UPS is positioned between
`the source of the input electrical power and the computer
`system. The UPS provides sufficient power to enable a user
`to save the contents of a program in operation and complete
`the current application program. When main electrical
`power is restored, the user can restart the application pro
`gram and begin program operation again. Without the pro
`tection of UPS, the data entered and application program in
`RAM would be irretrievably lost.
`One embodiment of the present invention is a memory
`system including solid state volatile memory devices
`capable of maintaining information when a voltage is
`applied to the devices, for example DRAM or the like. The
`invention prevents the loss of data due to unexpected power
`outages and also prevents errant control and address signals
`to the memory devices by monitoring the input electrical
`power source to the memory devices for acceptable
`conditions, and electrically isolating the memory devices
`from signals received on the control lines and address lines
`and switching to an alternate internal electrical power
`source, typically a battery, whenever the input power source
`is unacceptable.
`The memory system maintains the integrity of the data
`retained by the memory devices by isolating the devices
`from the external power source, control lines and address
`lines and placing the memory devices into a power down
`self-refresh mode which will maintain the data using a
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`minimum of electrical power.
`The prior art U.S. Pat. No. 5,798,961 discloses a SIMM
`non-volatile memory module having a volatile memory
`array, a battery circuit, a charging circuit and a control
`circuit. The control circuit in connection with the battery
`circuit monitors the external power supply from the SIMM
`VCC line. If the external power source falls below a
`predetermined voltage then the battery circuit maintains the
`integrity of the data by supplying power to the volatile
`memory array. The data retained by the memory module is
`susceptible to errant control signals and address signals that
`may appear on the control and address lines during times of
`unstable power in the system.
`SUMMARY OF THE INVENTION
`In accordance with the present invention, a memory
`system for use in a computer system including a solid state
`volatile memory device that is capable of retaining infor
`mation when a voltage is applied to it and capable of being
`placed in a self refresh mode is placed in a low power
`standby mode when the memory system is not receiving
`requests for access. The low power mode utilizes signifi
`cantly less electrical current than when the memory device
`is in the operating mode or powered up mode. According to
`the present invention a control device is interposed electri
`cally between the memory devices and a CPU. The control
`device senses CPU accesses of the memory devices and
`conditions the memory devices to an operating mode con
`dition prior to the allowing access to the information con
`tained therein. Whenever the control device senses the
`termination of a memory cycle, the control device places the
`solid state memory devices in a low power standby mode.
`The present invention further provides for reducing the
`overall electrical power requirement of portable, laptop or
`notebook computers by utilizing another embodiment of
`memory system in a hard disk emulation mode, thereby
`removing the need to maintain electrical power to the hard
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`US 6,243,315 B1
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`4
`disk drive of the computer system during those periods when
`the hard disk is not needed for computer program operation.
`Such reduced electrical power usage substantially increases
`the effective time the battery for the computer system can
`provide electrical power to maintain operations. By using a
`hard disk simulation for memory accesses instead of access
`ing the hard drive for the portable or laptop computer,
`significant savings in electrical power are achieved and it is
`possible to use smaller main batteries to reduce the over
`weight of the computer.
`In yet another embodiment according to the invention, a
`memory system for use in a computer system the memory
`system comprising a plurality of volatile solid state memory
`devices that retain information when an electrical power
`source is applied to the memory devices within a predeter
`mined voltage range. The memory devices having address
`lines and control lines and a control device for monitoring an
`electrical power source to determine when the electrical
`voltage reaches a predetermined threshold and for selec
`tively electrically isolating the memory devices from respec
`tive address lines and respective control lines so that when
`the memory devices are electrically isolated, any signals
`received on said respective address lines and respective
`control lines do not reach the memory devices.
`BRIEF DESCRIPTIONS OF THE FIGURES
`In order that the present invention may be more clearly
`understood, embodiments of the invention will now be
`described in more detail by way of example only with
`reference to the accompanying drawings in which:
`FIG. 1 is a block diagram of the low power down memory
`system showing the interposition of the access and control
`module between the memory module connector and the
`DRAM memory devices.
`FIG. 2 is the self-refresh mode timing diagram of the
`Hitachi HM5165165 DRAM chips.
`FIGS. 3A to 30 are a schematic drawn to current industry
`standards and practices of a 32 MB low power down 144
`PIN SODIMM according to the invention.
`FIG. 4 is a block diagram of a non-volatile memory
`system according to the invention.
`FIGS. 5A to 5P are is a schematic drawn in accordance
`with current industry standards and practices of one embodi
`ment of a non-volatile memory system according to the
`invention. FIGS. 5A,B,C,D can be assembled to form a
`single large circuit diagram by aligning A1 with A2, B1 with
`B2, C1 with C2, and D1 with D2.
`FIGS. 6A-1 to 6A-11 are a schematic drawn to current
`industry standards and practices of another embodiment of
`a 32 MB low power down 144 PIN SIMM according to the
`invention.
`FIGS. 6B-1 to 6B-5 are a schematic drawn to current
`industry standards and practices of the programming logic of
`one component used in the embodiment shown in FIG. 6a.
`FIGS. 7A,B,C,D,E,F,FI,I,J,K,I,NM,N,O,P,Q ar