UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________
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`HP INC.,
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`Petitioner,
`
`v.
`
`JAMES B. GOODMAN,
`
`Patent Owner,
`__________________
`
`Case IPR2017-01994
`Patent No. 6,243,315
`__________________
`
`Before BRIAN J. McNAMARA, PATRICK M. BOUCHER, and
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`KIMBERLY McGRAW, Administrative Patent Judges.
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`PATENT OWNER’S RESPONSE TO THE DECISION ON THE PETITION
`
`By James B. Goodman
`Patent Owner
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`
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`1
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`I.
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`RELATED CASES
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`
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`A final decision in this proceeding could affect the following cases pending in the U.S.
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`District Courts in which the ‘315 Patent is asserted: Goodman v. Hewlett-Packard Co., C.A. No.
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`16-CV-03195 (S.D. Tex.) (“HP Case”); Goodman v. ASUS Computer International, C.A. 17-
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`CV-05542 (N.D. Cal. 05542) (Transferred from the S.D. Texas.); Goodman v. Samsung
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`Electronics America, Inc., C.A. No. 17-CV-05539 (S.D. N.Y.); and Goodman v. Lenovo (United
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`States) Inc., C.A. 17-CV-06782.
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`
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`In addition, an IPR has been instituted against the present patent, U.S. Patent No.
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`6,423,315, by Samsung Electronics America, Inc. (Case IPR2017-02021) and ASUS Computer
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`International, Inc. (Case IPR2018-00047).
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`II.
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`THE CLAIMED INVENTIONS OF THE ‘315 PATENT
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`
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`Fig. 1 of the ‘315 Patent is shown below. As stated in the ‘315 Patent at 5:41-42, “Fig. 1
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`is a block diagram of a preferred embodiment of the low power down memory system.”
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`2
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`The following is independent claim 1:
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`1. A memory system for use in a computer system, said memory system
`comprising:
`
`a plurality of volatile solid state memory devices that retain information when an
`electrical power source is applied to said memory devices within a predetermined
`voltage range and capable of being placed in a self refresh mode; said memory
`devices having address lines and control lines;
`
`a control device for selectively electrically isolating said memory devices from
`respective address lines and respective control lines so that when said
`memory devices are electrically isolated, any signals received on said
`respective address lines and respective control lines do not reach said
`memory devices; and
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`a memory access enable control device coupled to said control device and to
`said control lines for determining when said memory system is not being
`accessed and for initiating a low power mode for said memory system
`wherein said control device electrically isolates said memory devices and
`places said memory devices in said self refresh mode, thereby reducing the
`amount of electrical energy being drawn from an electrical power supply for said
`computer system. (Emphasis added)
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`
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`The phrase “a control device … “ has been highlighted to draw attention to this important
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`aspect of the claimed invention. Electrically isolating the memory devices from the respective
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`address lines and the respective control lines so that any signals on those lines do not reach the
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`memory devices is critical for avoiding any corruptions of the data in the memory devices from
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`unwanted signals during the self refresh mode.
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`
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`The phrase “a memory access enable control device …” has been highlighted to point to
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`the important issue of when the low power down mode for the memory system starts: It starts
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`when the memory system is not being accessed.
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`Claims 2-9 depend on claim 1.
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`3
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`Fig. 4 of the ‘315 Patent is shown below. The embodiment shown in Fig. 4 features a
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`memory system with a backup battery to avoid a loss of data when the initial battery fails. In
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`addition, data in the memory devices are protected against corruption when the initial battery is
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`less than the minimum voltage to maintain the data in the memory devices. Claims 10-20 are
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`directed to a system with battery backup.
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`4
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`
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`The following is independent claim 10:
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`10. A memory system for use in a computer system, said memory system
`comprising:
`
`a plurality of volatile solid state memory devices that retain information when an
`electrical power source having a voltage greater than a predetermined voltage is
`applied to said devices; said memory devices having address lines and control
`lines;
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`said computer system including a first electrical power source for operating said
`computer and being capable of producing a first voltage applied to said memory
`devices;
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`a control device for monitoring said first voltage to determine when said first
`voltage is less than said predetermined voltage and for selectively electrically
`isolating said memory devices from respective address lines and respective
`control lines so that when said memory devices are electrically isolated, any
`signals received on said respective address lines and respective control lines
`do not reach said memory devices; and
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`a second electrical power source operable for supplying a second voltage to said
`memory devices greater than said predetermined voltage;
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`said control device being operable for disconnecting said first electrical power
`source from said memory devices and connecting said second electrical power
`source to said memory devices when said first voltage is less than said
`predetermined voltage;
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`whereby, data in said memory devices is preserved by said second electrical
`power source when said first electrical power source fails to maintain at least said
`predetermined voltage on said memory devices, and said memory devices are
`isolated from errant signals. (Emphasis added)
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`The subsystem starting with “control device” has been made bold to draw attention to this
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`particular feature. It is known in the prior art to use backup batteries and the like as an electrical
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`power source in the event of a failure of the power source being used initially. The “control
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`source” protects data in the memory devices when the first electrical power source is less than
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`the minimum required for the memory devices by electrically isolating address and control lines
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`from the memory devices so that errant signals cannot reach the memory devices and potentially
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`5
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`corrupt data. When the data in the memory devices is protected against errant signals, a
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`transition from the first electrical source to the second electrical source can be made without data
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`corruption
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`Claims 11-20 depend on claim 10.
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`III. THE ASSERTED GROUNDS OF UNPATENTABILITY IN THE DECISION
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`
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`Reference is being made herein to the Decision in the IPR dated March 9, 2018
`(“Decision”.
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`A.
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`The Decision States that The Petitioner cites two grounds for invalidating the claims in
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`the ‘315 Patent
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`
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`Ground 1: Claims 1 and 5 are unpatentable under 35 U.S.C. § 103(a) as obvious over
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`U.S. Patent No. 5,600,605 to Schaefer (“Schaefer”) in view of U.S. Patent No. 5,793,776 to
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`Qureshi et al. (Qureshi”).
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`
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`Ground 2: Claims 10 and 16 are unpatentable under 35 U.S. C. § 103(a) as obvious over
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`U.S. Patent No. 5,600,605 to Schaefer in view of U.S. Patent No. 5,793,776 to Qureshi et al. and
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`further with U.S. Patent No. 5,204,840 to Mazur (“Mazur”).
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`
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`The Decision precludes any additional grounds in this IPR.
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`Mazur has been cited by the Petitioner to show the use of a backup battery for claims 10
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`and 16; however, Petitioner has failed to provide any technical argument for combining Mazur
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`with the combination of Schaefer and Qureshi
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`B.
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`The cited references
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`
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`The Decision states: Schaefer describes a volatile memory device “for storing data and
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`responsive to command signals.” Ex. 1004, 1:60. Schaefer includes a command decoder that
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`6
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`“controls the various circuitry of SDRAM based on decoded commands such as during
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`controlled reads or writes.” Id. at 3:35–37 (reference numerals omitted). Schaefer explains that
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`the memory device includes address and control lines, see Id. at 3:30–33, and discloses a “SELF-
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`REFRESH” command for the devices, Id. at 3:60–61. According to Schaefer, “[a]ll the input and
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`output signals of SDRAM, with the exception of the CKE input signal during power down
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`and self refresh modes, are synchronized to the active going edge . . . of the CLK signal.”
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`(Emphasis added) Id. at 3:20–25 (reference numerals omitted). Schaefer notes that refresh
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`commands “are performed . . . in a manner known in the art to refresh the memory arrays.” Id. at
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`3:61–65. Schaefer notes also that “[i]n one preferred embodiment of the present invention, the
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`memory device is a synchronous dynamic random access memory (SDRAM).” Id. at 2:33–35.
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`
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`Schaefer states: “The system clock (CLK) signal is provided through a CLK input pin
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`and a clock enable signal (CKE) is provided through a CKE input to SDRAM 20. The CLK
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`signal is activated and deactivated based on the state of the CKE signal.” Id. At 3:16-20.
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`
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`The Decision states: Qureshi describes a process in which “memory such as SDRAMs
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`are put into self refresh mode.” Ex. 1005, 1:63–64. Qureshi explains that “[o]nce the self refresh
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`mode is entered, SDRAM ignores all inputs other than a CKE (clock enable) pin while in self
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`refresh state.” (Emphasis added.) Id. at 5:49–51 (reference numerals omitted). Qureshi
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`characterizes self refresh mode as “preferred for data retention and low power operation.” Id. at
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`1:65–67. This is the reason the SDRAMs are forced into self refresh prior to the JTAG testing so
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`that the SDRAMs need not require re-initialization after the JTAG testing. The process of re-
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`initialization wipes the memory.
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`
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`Qureshi is used with testing of the memory system to enable Joint Test Action Group
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`(JTAG) test port of integrated circuit chips mounted on a board. Id. at 1:26-29. “in accordance
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`7
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`with this invention, memory such as SDRAMs are put into self refresh mode while JTAG testing
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`is performed.” Id. at 63-64. The self refresh mode is initiated by the JTAG Logic. See Id. 2: 3-6.
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`
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`The Decision states: Mazur has been cited for the added feature of Claim 10 of an
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`alternate voltage source. Claim 10, however is not limited to the elementary feature of an
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`alternate voltage source.
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`IV. DISCUSSION
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`
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`A.
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`Level of Skill in the Art
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`The Patent Owner agrees with the statement of the Decision at p. 7, second paragraph as
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`to the level of skill for a person with ordinary skill in the art (“POSITA”): “[w]e determine that
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`it is not necessary to state explicitly a specific level of skill as the prior art itself reflects an
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`appropriate level of skill. See Okajima v. Bourdeau, 261 F. 3d 1350, 1355 (Fed. Cir. 2001)”
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`B.
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`Claim Construction
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`The Decision at p. 7, last paragraph states that the claim terms in an unexpired patent are
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`construed in the broadest reasonable construction in light of the specification of the patent in
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`which they appear. Citing 36 C.F.R. § 42.100(b). The Decision cites:
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`Consistent with the broadest reasonable construction, claim terms
`are presumed to have their ordinary and customary meaning as
`understood by a person of ordinary skill in the art in the context of
`the entire patent disclosure. In re Translogic Tech. Inc., 504 F. 3d
`1249, 1257 (Fed. Cir. 2007)
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`The Decision points out at p. 8, first paragraph that neither the Petitioner nor the Patent
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`
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`Owner identifies any claim terms as warranting construction. The Decision then states that it
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`concludes that no claim construction is necessary.
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`
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`It is respectfully pointed out that both the Petitioner and the Patent Owner have dealt with
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`the issue of claim construction in the District Court, and both parties agreed on the claim
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`8
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`construction for each and every term of the claims that the parties believed needed construction.
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`See Exhibit A. In addition, the District Court accepted the claim construction as stated by the
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`parties. See Exhibit B.
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`
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`Thus, the issue of claim construction has not been raised by either party in this inter
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`partes Review in view of the prior agreement for the claim construction by the parties before the
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`District Court.
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`
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`It is respectfully pointed out that the Decision raises a question about claim construction
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`starting at p. 13, last paragraph concerning all address and control lines being electrically
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`isolated under certain conditions according to claim 1.
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`The Decision states that it does not understand claim 1 as requiring all address and
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`control lines to be electrically isolated from the memory devices. The Decision states that the
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`argument that all address and control lines are electrically isolated would be inconsistent with the
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`preferred embodiments, which, the Decision states does not appear to isolate the memory devices
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`5 from all address and control lines. The Decision, in support of its position, states:
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`For example, the ‘315 patent states that the control device shown
`in Figure 1 electrically isolates control bus 22 and address bus 17
`from the memory devices, but does not state that the memory
`devices are electrically isolated from the RAS and WE control
`lines, 26, 28. Ex. 1001, Fig. 4, 5:60-67; see also id. at 9:24-26
`(stating that the control center115 of Figure 4 electrically isolates
`memory devices 5 from control lines 122 and address lines 117,
`but not stating that the memory devices are isolated from RAS and
`WE Control Lines).
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`The only address and control lines which would need to be electrically isolated are the
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`
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`address and control lines which communicate to the memory devices because only those address
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`and control lines could introduce errant signals which might adversely change data in the
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`memory devices. Thus, the term “all” is referring to the class of address and control lines which
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`communicate with the memory devices, not address and control lines in general.
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`The Fig. 1 and the specification of the’315 Patent illustrate the distinction. The RAS and
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`WE Control Lines 26, 28 do not communicate with the memory devices 5.
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`The purpose of the RAS and WE control lines 26, 28 connecting to the memory access
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`enable control 30 in Fig. 1 is to indicate if a memory access is pending, not to communicate with
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`the memory devices 5:
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`FIG. 1 also shows RAS row address select lines, 26 and WE, write
`enable line 28 connected to a memory access enable control 30.
`The memory access enable control 30 receives signals from the
`CPU that indicate a memory access is pending. The memory
`access enable control 30 then signals the control device 15 to bring
`the memory devices to a normal operating mode by raising power
`up line 34 to a true or high state. The memory access 30
`determines when a memory access is appropriate. Id. 6:1-12.
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`Thus, RAS control line 26 and WE control line 28 do not communicate to the memory
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`
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`device 5 and need not be electrically isolated from the memory devices 5 to protect the memory
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`devices from errant signals which might be on RAS and WE control lines 26, 28. Thus, RAS
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`and WE control lines 26, 28 are effectively blocked from the SDRAMs during the self refresh.
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`As shown in Fig.1, the Address Buss 17 and the Control Buss 22 are connected to the
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`Address & Control Center 15. The operation is as follows
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`FIG. 1 is a block diagram of a preferred embodiment of the low
`power down memory system. FIG. 1 shows volatile solid state
`memory devices 5 in two way communications with a data buss 8
`that is coupled to a CPU (not shown) via an industry standard
`memory slot connector 11 for example 144 pin SODIMM memory
`connector or 168 PIN DIMM memory connector both in
`accordance with the JEDEC industry standard. The data buss 8 has
`lines for communicating electrical signals representing data to the
`memory devices 5. A control device 15 is interdisposed between
`an address buss 17 connected to memory connector 11 and an
`address buss 20 in direct communication with memory devices
`5 via the address pins of the memory devices 5. Control device
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`10
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`15 is also interdisposed between a control buss 22 coupled to
`memory connector 11 and a control bus 24 in direct
`communication with memory devices 5. The control device 15
`accepts input signals from the memory access enable control 30
`that indicate when the memory devices 5 are placed in a power
`down mode or in a powered up mode. The control device 15 also
`isolates the address buss 17 and control buss 22 from the
`memory devices 5 during the time period when the memory
`devices 5 are in a power down self refresh mode. By isolating
`the memory devices from the control buss 22 and address buss
`17 the control device 15 prevents errant signals from
`erroneously changing or affecting the data being retained by
`the memory devices 5. (Emphasis added) Id. 5:41-67
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`The control device 15 isolates the address buss 17 and control buss 22 and that means
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`
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`that the RAS, CAS, and WE are electrically isolated from the memory devices 5.
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`
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`It is respectfully pointed out that there is another view as to the RAS and WE control
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`lines 26, 28 becoming electrically isolated from the memory devices 5.
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`
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`Ex. 2001 at p. 2 states that the phrase in the claims of the ‘315 Patent, “selectively
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`electrically isolating said memory devices from respective address lines and respective control
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`lines” is to be construed as meaning, “inhibiting signals on respective address and respective
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`control lines from the memory devices such that signals on those lines do not arrive at the
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`memory devices”. Thus, claim 1 does not want to allow signals on the address and control lines
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`which ordinarily reach the memory devices 5 to reach memory devices 5 during the self refresh.
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`Both parties and the District Court have construed the phrases “address lines” and “control
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`lines”.
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`
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`Ex. 2001 showing the Court claim construction for the ‘315 Patent at p. 2 construes
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`“address lines” to mean “lines that carry signals specifying a memory location to be accessed”,
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`and “control lines” to mean “lines that carry control signals”.
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`It is respectfully noted that Ex. 2001 construes “control signals” as signals that control
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`11
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`the sequence of addressing and memory mode”.
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`
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`It is respectfully submitted that the claim construction for the ‘315 Patent by the District
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`Court, and the parties should apply at least for this inter partes Review. See In re Translogic
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`Tech. Inc. Hence, it would be reasonable for the aforementioned claim constructions to be
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`applied herein because the claim construction for each term mentioned above is obviously as
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`broad as possible, thereby complying with In re Translogic Tech. Inc..
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`
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`Accordingly, the phrase “selectively electrically isolating said memory devices from
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`respective address lines and respective control lines” must include all address and control signal
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`lines according to the address and control lines as construed by the parties and the District Court.
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`law:
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`C.
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`Principles of Law
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`Patent Owner does not dispute the statement in the Decision at p. 8 as to the applicable
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`A claim is unpatentable under 35 U.S.C. § 103(a) if “the
`differences between the subject matter sought to be patented and
`the prior art are such that the subject matter as a whole would have
`been obvious at the time the invention was made to a person
`having ordinary skill in the art to which said subject matter
`pertains.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`(2007). The question of obviousness is resolved on the basis of
`underlying factual determinations, including: (1) the scope and
`content of the prior art; (2) any differences between the claimed
`subject matter and the prior art; (3) the level of skill in the art; and
`(4) objective evidence of nonobviousness, i.e., secondary
`considerations. See Graham v. John Deere Co, 383 U.S. 1, 17–18
`(1966).
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`Overview of the Asserted Art
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`D.
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`
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`Schaefer (Ex. 1003)
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`The Decision has an overview of Schaefer (Ex. 1003) at p. 8-9, and points out that
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`“Schaefer explains the memory device includes address and control lines. See id. at 3:30-33 …”
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`The referenced portion of Schaefer states:
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`Command decoder 26 receivers control signals including a row
`address strobe (RAS*) signal on a RAS*pin, column address
`strobe (CAS*) signal on a CAS* pin, and write enable (WE*)
`signal on a WE*) pin.
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`Thus, Schaefer shows that the prior art acknowledged that RAS, CAS, and WE are
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`
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`control signals. (Emphasis added)
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`Qureshi (Ex. 1004)
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`The Decision has an overview of Qureshi (Ex. 1004) at p. 9 first full paragraph. It is
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`noted that Qureshi has the “ability to dynamically enter and exit SDRAM self refresh before and
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`after [JTAG] testing”. The self refresh is started externally, by an operator, or a programmed
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`system, prior to performing the JTAG testing. See Id 1:62-2:2 and 2:54-57.
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`
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`Thus, it is the JTAG Logic who initiates and stops the self refresh independently of the
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`activity of the memory devices. That is, the memory devices are forced into a self refresh mode
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`regardless of the activity of the memory devices.
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`Mazur (Ex. 1005)
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`The Decision has an overview of Mazur (Ex. 1005) at p. 9, last paragraph.
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`The Decision states: “According to Mazur, “[w]hen the power loss is detected, a
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`signal is generated which initiates a sequence to isolate the RAM and refresh it
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`with an independent power supply.” There is no mention of the “control device
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`… for selectively electrically isolating said memory devices … “ as set forth in
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`claims 10 and 16.
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`E.
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`Asserted Obviousness of Claims 1 and 5 over Schaefer and Qureshi
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`The Decision presents the Petitioner’s argument at pp. 10-13 as follows:
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`
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`Petitioner contends that claims 1 and 5 are unpatentable
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`13
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`under § 103(a) over the combined teachings of Schaefer and
`Qureshi. Pet. 3. 17–19, 23–30, 39–40, 50–51. For example, in
`mapping independent claim 1, Petitioner contends that Schaefer
`discloses a plurality of volatile solid state memory devices (e.g.,
`SDRAMs) that retain information when powered in a 3.3V low
`voltage environment. Id. at 24–25, 39–40 (citing Ex. 1003, 2:36–
`37, 3:13–16, Fig. 1). Petitioner also states that Schaefer’s memory
`has address lines (e.g., A0-A15) and control lines (e.g., RAS, CAS,
`WE) and is capable of being placed in a self refresh mode, id. at
`25–26 (citing Ex. 1003, 3:30–33, 3:58–61, 4:19–21). Petitioner
`also asserts that Qureshi teaches a memory controller (i.e., control
`device of claim element 1[e]) that places an SDRAM in a self-
`refresh mode prior to beginning JTAG testing, where “all access
`signals are ignored, which corresponds to electrically isolating
`the SDRAM.” (Emphasis added to enable an easy reference to this
`language) Id. at 26 (citing Ex. 1004, Abstract, 5:49–51).
`Petitioner states that once the self-fresh mode is entered, the
`SDRAM ignores all inputs other than a CKE (clock enable) pin
`while in the self-refresh state. (Emphasis added to enable an easy
`reference to this language) Id. (citing Ex. 1004, 5:49–51); Ex.
`1004, 1:65:2–2. Petitioner further asserts that a POSITA would
`understand that Qureshi’s memory controller is configured to place
`an SDRAM, such as the SDRAM of Schaefer, into a “don’t care”
`state, thereby electrically isolating the address/control lines and
`placing it in a low power self-refresh mode, prior to performing its
`tests. Id. at 26–27, 41 (citing Ex. 1002 ¶¶ 59–61). Petitioner states
`that Schaefer’s SDRAM memory includes a pin for receiving a
`“don’t care” signal, which then inhibits any action from the
`memory device, thereby electrically isolating it from the
`address/control lines. Id. at 27 (citing Ex. 1003 6:56–58, Fig. 1.
`Petitioner asserts that the combination of Schaefer and Qureshi
`teaches the “memory access enable device” of claim element 1[f].
`
`Specifically, Petitioner asserts that Schaefer’s command
`controller in the SDRAM is a “memory access enable control
`device” that includes circuitry for decoding read/write
`commands from Qureshi’s memory controller “so as to
`determine which memory bank should be addressed, (Emphasis
`added to enable an easy reference to this language) including
`decoding Qureshi’s signal that places Schaefer’s SDRAM into
`power down or self refresh mode, where all access signals are
`ignored.” Id. at 27–29, 41–43 (citing Ex. 1004, Abstract, 5:49–51,
`Fig. 1; Ex. 1003, 3:20– 25, 3:28–42, Fig. 1). Petitioner notes also
`that Qureshi teaches that the self-refresh mode “is preferred for
`data retention and low power operation.” Id. at 26 (quoting Ex.
`1005, 1:65–67) (emphasis omitted). Petitioner further asserts that
`the combination of Schaefer and Qureshi teaches DRAM
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`semiconductor microchips—the additional limitation in dependent
`claim 5—because both references “pertain to SDRAM, which is a
`subset of the DRAM semiconductor microchip.” Id. at 30, 50–51;
`Ex. 1002 ¶ 65.
`
`In addition, the Petition explains, with relevant support
`from Dr. Bagherzadeh, that combining Schaefer and Qureshi
`would have been obvious because one skilled in the art “would
`seek to use the memory controller of Qureshi to place the
`DRAM memory of Schaefer into the low power self-refresh
`mode so that existing data may be retained, while other signals
`may be ignored, and the amount of power consumed from the
`computer system is reduced.” Id. at 14 (citing Ex. 1002 ¶¶ 48–
`53). (Emphasis added to enable an easy reference to this language)
`
`
`
`
`The Patent Owner disputes the Petitioner’s statement for combining Schaefer and
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`Qureshi to render claims 1 and 5 obvious.
`
`a. Petitioner states: “all access signals are ignored, which corresponds to electrically
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`isolating the SDRAM.” [Id. at 26 (citing Ex. 1004, Abstract, 5:49–51)] thereby
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`suggesting that the quote is from Ex. 1004, Qureshi. This, however, is misleading.
`
`Actually, Ex. 1004, 5:49-51 states, “Once the self refresh mode is entered, SDRAM 116
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`ignores all inputs other than a CKE (clock enable) pin while in self refresh state.”
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`
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`Petitioner appears to be quoting from Qureshi, but actually Petitioner is quoting
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`from its consultant who has taken the liberty to change the language to make it appear
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`that Qureshi supports the Petitioner’s arguments directly. The Petitioner, in fact, has not
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`cited to any specific use of the phrase “electrically isolating” in either Schaefer or
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`Qureshi probably because neither Schaefer or Qureshi used such a phrase.
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`b. Petitioner asserts that Schaefer’s command controller in the SDRAM is a “memory
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`access enable control device” that includes circuitry for decoding read/write commands
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`from Qureshi’s memory controller “so as to determine which memory bank should be
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`addressed”, (emphasis added). The use of the phrase “memory access enable control
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`device” by Petitioner to describe Qureshi appears to be a reference to the subsystem in
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`claim 1 of the ‘315 Patent, not Qureshi. This is misleading by Petitioner. One of the
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`significant functions of the “memory access enable control device” in claim 1 of the ‘315
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`Patent is “for determining when said memory system is not being accessed and for
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`initiating a low power mode for said memory devices”. That is, the ‘315 Patent does
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`NOT initiate low power mode until the memory systems are NOT being accessed. In
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`contrast, Qureshi teaches to initiate the low power mode prior to the JTAG testing
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`without any determination as to whether the memory devices are being accessed at that
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`time. See Qureshi, 2:3-12. Prior to the JTAG testing, an operation is initiated to enter
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`the self refresh mode, the Memory Controller Unit waits until the current memory access
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`operation has been completed. Qureshi states:
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`The ability to dynamically enter and exit SDRAM self refresh
`before and after testing, respectively, using the JTAG Logic saves
`debugging time. Memory and control logic do not need to be
`initialized after the testing takes place. See Id. at 2:6-12, 4:58-62
`and 6:3-6.
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`By using the self refresh mode for the JTAG testing, Qureshi avoids initializing
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`
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`the memory and logic control.
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`c. Petitioner states from its consultant, as shown in bold above, “combining Schaefer and
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`Qureshi would have been obvious because one skilled in the art would seek to use the
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`memory controller of Qureshi to place the DRAM memory of Schaefer into the low
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`power self-refresh mode so that existing data may be retained, while other signals may be
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`ignored, and the amount of power consumed by the computer system is reduced.” Id. at
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`14 (citing Ex. 1002 ¶¶ 48–53).
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`
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`The Petitioner has not pointed to any place in Qureshi or Schaefer to support this
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`conclusion that Qureshi teaches that it can be used to save on power consumption. Once
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`again, the Expert is asserting a statement without support in an effort to mislead the
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`Board.
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`
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`The only mention of low power operation in Qureshi is: “Self refresh is a refresh
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`mode available in some memory and is preferred for data retention and low power
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`operation.” Id. 1:65-67. It is not logical to conclude that Qureshi is suggesting that it
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`should be combined with Schaefer to reduce power consumption.
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`
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`The assertion made by Petitioner for combining Qureshi and Schaefer to save
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`electrical power is patently illogical. Qureshi operates to stop Schaefer from processing
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`read or write commands, and sends Schaefer into a self refresh mode, thereby preventing
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`Schaefer from operating as an uninterrupted a memory system. Under such an
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`arrangement asserted by Petitioner that Qureshi be combined with Schaefer for the sole
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`purpose of saving power, a special program would be needed to periodically send
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`Schaefer into a self refresh mode. This would mean that the memory use of Schaefer
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`would be arbitrarily interrupted to save energy.
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` The operations of Schaefer to auto-refresh and self refresh are disclosed in several
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`places:
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`A synchronous dynamic random access memory (SDRAM) is
`designed to operate in a synchronous memory system. Thus, all
`input and output signals, with the exception of a clock enable
`signal during power down and self refresh modes, are
`synchronized to an active edge of a system clock. Id. 1:10-17
`(Emphasis added)
`
`
`The CLK signal is activated and deactivated
`based on the state of the CKE signal. All the input and output
`signals of SDRAM 20, with the exception of the CKE input
`signal during power down and self refresh modes, are
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`
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`17
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`synchronized to the active going edge (the positive going
`edge in the embodiment illustrated in FIG. 1 ) of the CLK signal.
`Id. 3:18-25 (Emphasis added)
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`Thus, Schaefer always has the CKE connected to the SDRAMs during self refresh.
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`
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`The facts disagree with Petitioner’s assertion.
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`
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`It has been pointed out above that the JTAG Logic initiates the low power down mode,
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`self refresh, without regard to pending activities in the memory devices. In addition, Qureshi
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`wants to enter the self refresh mode for the specific purpose of conducting the JTAG testing
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`according to Qureshi. After the JTAG testing, Qureshi takes Schaefer out of the self refresh
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`mode. There is no statement or suggestion in either Schaefer or Qureshi that the forced entry
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`of Schaefer into the self refresh mode is a suggested approach to save electrical power. It is
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`also pointed out that during the self refresh mode, the memory devices of Schaefer are
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`unavailable.
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`d. Petitioner has pointed out that Schaefer and Qureshi state that the RAS, CAS and WE
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`control lines are disabled when the self refresh mode is entered. Schaefer, 3:26-36, and
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`Qureshi, 5:39-51. It is noted in Qureshi at 1:65-2:2 that when an SDRAM enters the self
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`refresh mode, the SDRAM disables the system clock and all input buffers except CKE.
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`In addition, Id. 5:49 states explicitly, “Once the self refresh mode is entered, SDRAM
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`116 ignores all inputs other than a CKE (clock enable) pin while in a self refresh state.”
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`In view of the address and control signals into the memory devices being required by
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`
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`claim 1 to be electrically isolated, it is necessary to determine which address and control
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`lines are to be electrically isolated. In re Translogic Tech Inc. requires the broadest
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`reasonable construction. The parties have agreed and the District Court has confirmed
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`that the claim construction in Ex. 2001 is appropriate. It is respectfully submitted that the
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`claim construction of the relevant terms and phrases are the broadest reasonable