16 MEG: x4, x8
`SDRAM
`
`MT48LC4M4A1/A2 S - 2 Meg x 4 x 2 banks
`MT48LC2M8A1/A2 S - 1 Meg x 8 x 2 banks
`
`PIN ASSIGNMENT (Top View)
`44-Pin TSOP
`
`x8
`Vss
`DQ7
`VssQ
`DQ6
`VccQ
`DQ5
`VssQ
`DQ4
`VccQ
`NC
`NC
`DQM
`CLK
`CKE
`NC
`A9
`A8
`A7
`A6
`A5
`A4
`Vss
`
`x4
` -
`NC
` -
`DQ3
` -
`NC
` -
`DQ2
` -
` -
` -
` -
` -
` -
` -
` -
` -
` -
` -
` -
` -
` -
`
`44
`43
`42
`41
`40
`39
`38
`37
`36
`35
`34
`33
`32
`31
`30
`29
`28
`27
`26
`25
`24
`23
`
`1234567891
`
`0
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`
`x8
`Vcc
`DQ0
`VssQ
`DQ1
`VccQ
`DQ2
`VssQ
`DQ3
`VccQ
`NC
`NC
`WE#
`CAS#
`RAS#
`CS#
`BA
`A10
`A0
`A1
`A2
`A3
`Vcc
`
`x4
`-
`NC
`-
`DQ0
`-
`NC
`-
`DQ1
`
`--------------
`
`Note: The # symbol indicates signal is active LOW. A dash (-)
`indicates x4 pin function is same as x8 pin function.
`
`Configuration
`Refresh Count
`Row Addressing
`Bank Addressing
`Column Addressing
`
`2 MEG x 8
`4 MEG x 4
`2 Meg x 4 x 2 banks 1 Meg x 8 x 2 banks
`4K
`4K
`2K (A0-A10)
`2K (A0-A10)
`1 (BA)
`1 (BA)
`1K (A0-A9)
`512 (A0-A8)
`
`16Mb (x4/x8) SDRAM PART NUMBERS
`
`PART NUMBER
`MT48LC4M4A1TG S
`MT48LC4M4A2TG S
`MT48LC2M8A1TG S
`MT48LC2M8A2TG S
`
`ARCHITECTURE
`4 Meg x 4 (tWR = 1 CLK)
`4 Meg x 4 (tWR = 2 CLK)
`2 Meg x 8 (tWR = 1 CLK)
`2 Meg x 8 (tWR = 2 CLK)
`
`GENERAL DESCRIPTION
`The Micron 16Mb SDRAM is a high-speed CMOS, dy-
`namic random-access memory containing 16,777,216
`bits. It is internally configured as a dual memory array
`(the 4 Meg x 4 is a dual 2 Meg x 4, and the 2 Meg x 8 is a dual
`1 Meg x 8) with a synchronous interface (all signals are
`
`1
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`ª 1998, Micron Technology, Inc.
`
`SYNCHRONOUS
`DRAM
`
`FEATURES
`• PC100-compliant, includes CONCURRENT AUTO
`PRECHARGE
`• Fully synchronous; all signals registered on positive
`edge of system clock
`• Internal pipelined operation; column address can be
`changed every clock cycle
`• Internal banks for hiding row access/precharge
`• Programmable burst lengths: 1, 2, 4, 8 or full page
`• Auto Precharge and Auto Refresh Modes
`• Self Refresh Mode
`• 64ms, 4,096-cycle refresh (15.6m s/row)
`• LVTTL-compatible inputs and outputs
`• Single +3.3V – 0.3V power supply
`• One- and two-clock WRITE recovery (tWR) versions
`OPTIONS
`MARKING
`• Architectures
`4 Meg x 4
`2 Meg x 8
`• WRITE Recovery (tWR/tDPL)
`tWR = 1 CLK
`tWR = 2 CLK (Contact factory for availability.)
`
`4M4
`2M8
`
`A1
`A2
`
`• Plastic Package - OCPL
`44-pin TSOP (400 mil)
`
`• Timing (Cycle Time)
`8ns; tAC = 6ns @ CL = 3
`10ns; tAC = 9ns @ CL = 2
`
`TG
`
`-8B
`-10
`
`• Part Number Example: MT48LC2M8A1TG-10 S
`
`NOTE: The 16Mb SDRAM base number differentiates the offerings in two places:
`MT48LC2M8A1 S. The fourth field distinguishes the architecture offering:
`4M4 designates 4 Meg x 4, and 2M8 designates 2 Meg x 8. The fifth field
`distinguishes the WRITE recovery offering: A1 designates one CLK and A2
`designates two CLKs.
`
`KEY TIMING PARAMETERS
`
`SPEED
`GRADE
`-8B
`-10
`-8B
`-10
`
`CLOCK
`FREQUENCY
`125 MHz
`100 MHz
`83 MHz
`66 MHz
`
`ACCESS TIME
`CL = 2*
`CL = 3*
`–
`6ns
`–
`7.5ns
`9ns
`–
`9ns
`–
`
`SETUP
`TIME
`2ns
`3ns
`2ns
`3ns
`
`HOLD
`TIME
`1ns
`1ns
`1ns
`1ns
`
`* CL = CAS (READ) latency.
`
`16 Meg: x4, x8 SDRAM
`16MSDRAMx4x8.p65 – Rev. 3/98
`
`HP Exhibit 1009 - Page 1
`
`

`

`16 MEG: x4, x8
`SDRAM
`
`GENERAL DESCRIPTION (continued)
`registered on the positive edge of the clock signal, CLK).
`Each of the two internal banks is organized with 2,048 rows
`and either 1,024 columns by 4 bits (4 Meg x 4) or 512 columns
`by 8 bits (2 Meg x 8).
`Read and write accesses to the SDRAM are burst oriented;
`accesses start at a selected location and continue for a
`programmed number of locations in a programmed se-
`quence. Accesses begin with the registration of an ACTIVE
`command, which is then followed by a READ or WRITE
`command. The address bits registered coincident with the
`ACTIVE command are used to select the bank and row to be
`accessed (BA selects the bank, A0-A10 select the row). The
`address bits registered coincident with the READ or WRITE
`command are used to select the starting column location for
`the burst access.
`The SDRAM provides for programmable READ or WRITE
`burst lengths of 1, 2, 4 or 8 locations, or the full page, with
`a burst terminate option. An AUTO PRECHARGE function
`may be enabled to provide a self-timed row precharge that
`is initiated at the end of the burst sequence.
`
`The Micron 16Mb SDRAM uses an internal pipelined
`architecture to achieve high-speed operation. This architec-
`ture is compatible with the 2n rule of prefetch architectures,
`but it also allows the column address to be changed on every
`clock cycle to achieve a high-speed, fully random access.
`Precharging one bank while accessing the alternate bank
`will hide the PRECHARGE cycles and provide seamless,
`high-speed, random-access operation.
`The Micron 16Mb SDRAM is designed to operate in 3.3V,
`low-power memory systems. An auto refresh mode is
`provided, along with a power-saving, power-down mode.
`All inputs and outputs are LVTTL-compatible.
`SDRAMs offer substantial advances in DRAM operating
`performance, including the ability to synchronously burst
`data at a high data rate with automatic column-address
`generation, the ability to interleave between internal banks
`in order to hide precharge time, and the capability to
`randomly change column addresses on each clock cycle
`during a burst access.
`
`16 Meg: x4, x8 SDRAM
`16MSDRAMx4x8.p65 – Rev. 3/98
`
`2
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`ª 1998, Micron Technology, Inc.
`
`HP Exhibit 1009 - Page 2
`
`

`

`TABLE OF CONTENTS
`4
`Functional Block Diagram - 4 Meg x 4 ...........................
`5
`Functional Block Diagram - 2 Meg x 8 ...........................
`6
`Pin Description ..................................................................
`7
`Functional Description ....................................................
`7
`Initialization .................................................................
`7
`Register Definitions .....................................................
`7
`Mode Register ........................................................
`7
`Burst Length .....................................................
`7
`Burst Type .........................................................
`9
`CAS Latency .....................................................
`9
`Operating Mode ...............................................
`9
`Write Burst Mode ............................................
`Commands ................................................................... 10
`Truth Table 1 (Commands and DQM Operation) ............. 10
`Command Inhibit .................................................. 11
`No Operation (NOP) ............................................. 11
`Load Mode Register .............................................. 11
`Active ...................................................................... 11
`Read ......................................................................... 11
`Write ........................................................................ 11
`Precharge ................................................................ 11
`Auto Precharge ...................................................... 11
`Burst Terminate ..................................................... 11
`Auto Refresh ........................................................... 12
`Self Refresh ............................................................. 12
`
`16 MEG: x4, x8
`SDRAM
`
`Operation ..................................................................... 13
`Bank/Row Activation ........................................... 13
`Reads ....................................................................... 14
`Writes ...................................................................... 20
`Precharge ................................................................ 22
`Power-Down .......................................................... 22
`Clock Suspend ........................................................ 23
`Burst Read/Single Write ...................................... 23
`Truth Table 2 (CKE) ..................................................... 24
`Truth Table 3 (Current State) ......................................... 25
`Absolute Maximum Ratings ............................................ 27
`DC Electrical Characteristics and Operating Conditions .... 27
`ICC Operating Conditions and Maximum Limits ......... 27
`Capacitance ........................................................................ 28
`AC Electrical Characteristics (Timing Table) .............. 28
`Timing Waveforms
`Initialize and Load Mode Register ............................ 31
`Power-Down Mode ..................................................... 32
`Clock Suspend Mode .................................................. 33
`Auto Refresh Mode ..................................................... 34
`Self Refresh Mode ........................................................ 35
`Reads
`Read - Without Auto Precharge .......................... 36
`Read - With Auto Precharge ................................ 37
`Alternating Bank Read Accesses ......................... 38
`Read - Full-Page Burst .......................................... 39
`Read - DQM Operation ......................................... 40
`Writes
`Write - Without Auto Precharge ......................... 41
`Write - With Auto Precharge ............................... 42
`Alternating Bank Write Accesses ........................ 43
`Write - Full-Page Burst ......................................... 44
`Write - DQM Operation ........................................ 45
`
`16 Meg: x4, x8 SDRAM
`16MSDRAMx4x8.p65 – Rev. 3/98
`
`3
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`ª 1998, Micron Technology, Inc.
`
`HP Exhibit 1009 - Page 3
`
`

`

`16 MEG: x4, x8
`SDRAM
`
`DQM
`
`FUNCTIONAL BLOCK DIAGRAM
`4 Meg x 4 SDRAM
`
`BANK 0
`MEMORY
`ARRAY
`(2,048 x 1,024 x 4)
`
`2,048
`
`DECODER
`
`ROW
`
`11
`
`ROW-
`ADDRESS
`LATCH
`
`11
`
`1,024 (x4)
`
`SENSE AMPLIFIERS
`I/O GATING
`DQM MASK LOGIC
`
`4
`
`DQ0 -
`DQ3
`
`DATA
`OUTPUT
`REGISTER
`
`DATA
`INPUT
`8
`REGISTER
`
`1,024
`
`4
`
`10
`
`COLUMN
`DECODER
`
`4
`
`ADDRESS BUFFER
`
`COLUMN-
`
`BURST COUNTER
`
`ADDRESS LATCH
`
`COLUMN-
`
`10
`
`CONTROL
`LOGIC
`
`DECODE
`COMMAND
`
`MODE REGISTER
`
`12
`
`CKE
`CLK
`
`CS#
`
`WE#
`
`CAS#
`RAS#
`
`A0-A10, BA
`
`12
`
`ADDRESS
`REGISTER
`
`REFRESH
`CONTROLLER
`
`REFRESH
`COUNTER
`
`11
`
`11
`
`ROW-
`ADDRESS
`MUX
`
`1,024
`
`SENSE AMPLIFIERS
`I/O GATING
`DQM MASK LOGIC
`
`1,024 (x4)
`
`BANK 1
`MEMORY
`ARRAY
`(2,048 x 1,024 x 4)
`
`2,048
`
`DECODER
`
`ROW
`
`11
`
`ROW-
`ADDRESS
`LATCH
`
`11
`
`16 Meg: x4, x8 SDRAM
`16MSDRAMx4x8.p65 – Rev. 3/98
`
`4
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`ª 1998, Micron Technology, Inc.
`
`HP Exhibit 1009 - Page 4
`
`

`

`16 MEG: x4, x8
`SDRAM
`
`DQM
`
`FUNCTIONAL BLOCK DIAGRAM
`2 Meg x 8 SDRAM
`
`BANK 0
`MEMORY
`ARRAY
`(2,048 x 512 x 8)
`
`2,048
`
`DECODER
`
`ROW
`
`11
`
`ROW-
`ADDRESS
`LATCH
`
`11
`
`512 (x8)
`
`SENSE AMPLIFIERS
`I/O GATING
`DQM MASK LOGIC
`
`8
`
`DQ0 -
`DQ7
`
`DATA
`OUTPUT
`REGISTER
`
`DATA
`INPUT
`8
`REGISTER
`
`512
`
`8
`
`9
`
`COLUMN
`DECODER
`
`8
`
`ADDRESS BUFFER
`
`COLUMN-
`
`BURST COUNTER
`
`ADDRESS LATCH
`
`COLUMN-
`
`9
`
`CONTROL
`LOGIC
`
`DECODE
`COMMAND
`
`MODE REGISTER
`
`12
`
`CKE
`CLK
`
`CS#
`
`WE#
`
`CAS#
`RAS#
`
`A0-A10, BA
`
`12
`
`ADDRESS
`REGISTER
`
`REFRESH
`CONTROLLER
`
`REFRESH
`COUNTER
`
`11
`
`11
`
`ROW-
`ADDRESS
`MUX
`
`512
`
`SENSE AMPLIFIERS
`I/O GATING
`DQM MASK LOGIC
`
`512 (x8)
`
`BANK 1
`MEMORY
`ARRAY
`(2,048 x 512 x 8)
`
`2,048
`
`DECODER
`
`ROW
`
`11
`
`ROW-
`ADDRESS
`LATCH
`
`11
`
`16 Meg: x4, x8 SDRAM
`16MSDRAMx4x8.p65 – Rev. 3/98
`
`5
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`ª 1998, Micron Technology, Inc.
`
`HP Exhibit 1009 - Page 5
`
`

`

`16 MEG: x4, x8
`SDRAM
`
`PIN DESCRIPTIONS
`TSOP
`PIN NUMBERS
`32
`
`SYMBOL
`CLK
`
`DESCRIPTION
`TYPE
`Input Clock: CLK is driven by the system clock. All SDRAM input signals are
`sampled on the positive edge of CLK. CLK also increments the internal burst
`counter and controls the output registers.
`Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
`Deactivating the clock provides PRECHARGE POWER-DOWN and SELF
`REFRESH operations (all banks idle), ACTIVE POWER-DOWN (row active in
`either bank), or CLOCK SUSPEND operation (burst/access in progress). CKE
`is synchronous except after the device enters power-down and self refresh
`modes, where CKE becomes asynchronous until after exiting the same mode.
`The input buffers, including CLK, are disabled during power-down and self
`refresh modes, providing low standby power. CKE may be tied HIGH.
`Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH)
`the command decoder. All commands are masked when CS# is registered
`HIGH. CS# provides for external bank selection on systems with multiple
`banks. CS# is considered part of the command code.
`Input Command Inputs: RAS#, CAS# and WE# (along with CS#) define the
`command being entered.
`Input/Output Mask: DQM is an input mask signal for write accesses and an
`output enable signal for read accesses. Input data is masked when DQM is
`sampled HIGH during a WRITE cycle. The output buffers are placed in a
`High-Z state (after a two-clock latency) when DQM is sampled HIGH during a
`READ cycle.
`Input Bank Address: BA defines to which bank the ACTIVE, READ, WRITE or
`PRECHARGE command is being applied. BA is also used to program the
`twelfth bit of the Mode Register.
`Input Address Inputs: A0-A10 are sampled during the ACTIVE command (row-
`address A0-A10) and READ/WRITE command (column-address A0-A9 [x4];
`A0-A8 [x8]; with A9 as a “Don’t Care” and A10 defining AUTO PRECHARGE)
`to select one location out of the memory array in the respective bank. A10 is
`sampled during a PRECHARGE command to determine if both banks are to
`be precharged (A10 HIGH). The address inputs also provide the op-code
`during a LOAD MODE REGISTER command.
`x4: DQ0, 1, 2, 3 Input Data I/O: Data bus.
`x8: DQ1, 3, 4, 6
`No Connect: These pins should be left unconnected.
`–
`x4: NC
`x8: DQ0, 2, 5, 7 Input Data I/O: Data bus.
`NC
`–
`No Connect: These pins should be left unconnected.
`VCCQ
`Supply DQ Power.
`VSSQ
`Supply DQ Ground.
` Supply Power Supply: +3.3V – 0.3V.
`VCC
`VSS
` Supply Ground.
`
`CKE
`
`CS#
`
`RAS#, CAS#,
` WE#
`DQM
`
`Input
`
`BA
`
`A0-A10
`
`31
`
`15
`
`14, 13,
`12
`33
`
` 16
`
`18-21, 24-29, 17
`
`4, 8, 37, 41
`
`2, 6, 39, 43
`
`10, 11, 30, 34, 35
`5, 9, 36, 40
`3, 7, 38, 42
`1, 22
`23, 44
`
`16 Meg: x4, x8 SDRAM
`16MSDRAMx4x8.p65 – Rev. 3/98
`
`6
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`ª 1998, Micron Technology, Inc.
`
`HP Exhibit 1009 - Page 6
`
`

`

`FUNCTIONAL DESCRIPTION
`In general, the SDRAM is a dual memory array (the
`4 Meg x 4 is a dual 2 Meg x 4, and the 2 Meg x 8 is a dual
`1 Meg x 8) which operates at 3.3V and includes a synchro-
`nous interface (all signals are registered on the positive edge
`of the clock signal, CLK). Each of the two internal banks is
`organized with 2,048 rows and either 1,024 columns by 4
`bits (4 Meg x 4) or 512 columns by 8 bits (2 Meg x 8).
`Read and write accesses to the SDRAM are burst oriented;
`accesses start at a selected location and continue for a
`programmed number of locations in a programmed se-
`quence. Accesses begin with the registration of an ACTIVE
`command, which is then followed by a READ or WRITE
`command. The address bits registered coincident with the
`ACTIVE command are used to select the bank and row to be
`accessed (BA selects the bank, A0-A10 select the row). The
`address bits (A0-A9; A9 is a “Don’t Care” for x8) registered
`coincident with the READ or WRITE command are used to
`select the starting column location for the burst access.
`Prior to normal operation, the SDRAM must be initial-
`ized. The following sections provide detailed information
`covering device initialization, register definition, command
`descriptions and device operation.
`
`INITIALIZATION
`SDRAMs must be powered up and initialized in a pre-
`defined manner. Operational procedures other than those
`specified may result in undefined operation. Once power
`is applied to VCC and VCCQ (simultaneously) and the clock
`is stable, the SDRAM requires a 100m s delay prior to apply-
`ing an executable command. The RAS#, CAS#, WE# and
`CS# inputs should be held HIGH during this phase of
`power-up.
`Once the 100m s delay has been satisfied, CKE HIGH and
`the PRECHARGE command can be applied (set up and
`held with respect to a positive edge of CLK). Both banks
`must be precharged, thereby placing the device in the all
`banks idle state.
`Once in the idle state, two AUTO REFRESH cycles must
`be performed. Once the AUTO REFRESH cycles are com-
`plete, the SDRAM is ready for Mode Register program-
`ming. Because the Mode Register will power up in an
`unknown state, it should be loaded prior to applying any
`operational command.
`
`REGISTER DEFINITION
`MODE REGISTER
`The Mode Register is used to define the specific mode of
`operation of the SDRAM. This definition includes the selec-
`tion of a burst length, a burst type, a CAS latency, an
`
`16 MEG: x4, x8
`SDRAM
`
`operating mode, and a write burst mode, as shown in
`Figure 1. The Mode Register is programmed via the LOAD
`MODE REGISTER command and will retain the stored
`information until it is programmed again or the device loses
`power.
`Mode Register bits M0-M2 specify the burst length, M3
`specifies the type of burst (sequential or interleaved), M4-
`M6 specify the CAS latency, M7 and M8 specify the operat-
`ing mode, M9 specifies the write burst mode, and M10 and
`M11 are reserved for future use.
`The Mode Register must be loaded when both banks are
`idle, and the controller must wait the specified time before
`initiating the subsequent operation. Violating either of
`these requirements will result in unspecified operation.
`
`Burst Length
`Read and write accesses to the SDRAM are burst ori-
`ented, with the burst length being programmable, as shown
`in Figure 1. The burst length determines the maximum
`number of column locations that can be accessed for a given
`READ or WRITE command. Burst lengths of 1, 2, 4 or 8
`locations are available for both the sequential and the
`interleaved burst types, and a full-page burst is available for
`the sequential type. The full-page burst is used in conjunc-
`tion with the BURST TERMINATE command to generate
`arbitrary burst lengths.
`Reserved states should not be used, as unknown opera-
`tion or incompatibility with future versions may result.
`When a READ or WRITE command is issued, a block of
`columns equal to the burst length is effectively selected. All
`accesses for that burst take place within this block, meaning
`that the burst will wrap within the block if a boundary is
`reached. The block is uniquely selected by A1-A9 (A9 is
`“Don’t Care” for x8) when the burst length is set to two; by
`A2-A9 (A9 is “Don’t Care” for x8) when the burst length is
`set to four; and by A3-A9 (A9 is “Don’t Care” for x8) when
`the burst length is set to eight. The remaining (least signifi-
`cant) address bit(s) is (are) used to select the starting loca-
`tion within the block. Full-page bursts wrap within the page
`if the boundary is reached.
`
`Burst Type
`Accesses within a given burst may be programmed to be
`either sequential or interleaved; this is referred to as the
`burst type and is selected via bit M3.
`The ordering of accesses within a burst is determined by
`the burst length, the burst type and the starting column
`address, as shown in Table 1.
`
`16 Meg: x4, x8 SDRAM
`16MSDRAMx4x8.p65 – Rev. 3/98
`
`7
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`ª 1998, Micron Technology, Inc.
`
`HP Exhibit 1009 - Page 7
`
`

`

`16 MEG: x4, x8
`SDRAM
`
`Table 1
`BURST DEFINITION
`
`Order of Accesses Within a Burst
`
`Type = Sequential Type = Interleaved
`
`0-1
`1-0
`
`0-1-2-3
`1-2-3-0
`2-3-0-1
`3-0-1-2
`
`0-1
`1-0
`
`0-1-2-3
`1-0-3-2
`2-3-0-1
`3-2-1-0
`
`Burst
`Length
`
`2
`
`4
`
`BA
`
`A10
`
`A9
`
`A8
`
`A7
`
`A6
`
`A5
`
`A4
`
`A3
`
`A2
`
`A1 A0
`
`Address Bus
`
`11
`
`10
`
`9
`
`8
`
`7
`
`6
`
`5
`
`4
`
`3
`
`2
`
`1
`
`0
`
`Mode Register (Mx)
`
`Reserved* WB
`
`Op Mode
`
`CAS Latency
`
`BT
`
`Burst Length
`
`Burst Length
`
`M2
`
`M1
`
`M0
`
`M3 = 0
`
`M3 = 1
`
`1 2 4 8
`
`1 2 4 8
`
`Reserved
`
`Reserved
`
`Reserved
`
`Reserved
`
`*Should program
`M11, M10 = 0, 0
`to ensure compatibility
`with future devices.
`
`0-1-2-3-4-5-6-7
`1-2-3-4-5-6-7-0
`2-3-4-5-6-7-0-1
`3-4-5-6-7-0-1-2
`4-5-6-7-0-1-2-3
`5-6-7-0-1-2-3-4
`6-7-0-1-2-3-4-5
`7-0-1-2-3-4-5-6
`Cn, Cn+1, Cn+2
`Cn+3, Cn+4...
`…Cn-1,
`Cn…
`
`0-1-2-3-4-5-6-7
`1-0-3-2-5-4-7-6
`2-3-0-1-6-7-4-5
`3-2-1-0-7-6-5-4
`4-5-6-7-0-1-2-3
`5-4-7-6-1-0-3-2
`6-7-4-5-2-3-0-1
`7-6-5-4-3-2-1-0
`
`Not supported
`
`Starting Column
` Address:
`A0
`0
`1
`A0
`0
`1
`0
`1
`A0
`0
`1
`0
`1
`0
`1
`0
`1
`
`A1
`0
`0
`1
`1
`A2 A1
`0
`0
`0
`0
`0
`1
`0
`1
`1
`0
`1
`0
`1
`1
`1
`1
`
`8
`
`x4: n = A0-A9
`Full
`x8: n = A0-A8
`Page
`(x4: 1,024) (location 0-1,023)
`(location 0-511)
`(x8: 512)
`
`Reserved
`
`Reserved
`
`Full Page
`
`Reserved
`
`0 1 0 1 0 1 0 1
`
`0 0 1 1 0 0 1 1
`
`0 0 0 0 1 1 1 1
`
`Burst Type
`
`Sequential
`
`Interleaved
`
`M3
`
` 0 1
`
`M6
`
` M5
`
`M4
`
`CAS Latency
`
`Reserved
`
`1 2 3
`
`Reserved
`
`Reserved
`
`Reserved
`
`Reserved
`
`0 1 0 1 0 1 0 1
`
`0 0 1 1 0 0 1 1
`
`0 0 0 0 1 1 1 1
`
`1. For a burst length of two, A1-A9 select the block of
`two burst (A9 is a “Don’t Care” for x8); A0 selects the
`starting column within the block.
`2. For a burst length of four, A2-A9 select the block of
`four burst (A9 is a “Don’t Care” for x8); A0-A1 select
`the starting column within the block.
`3. For a burst length of eight, A3-A9 select the block of
`eight burst (A9 is a “Don’t Care” for x8); A0-A2 select
`the starting column within the block.
`4. For a full-page burst, the full row is selected and
`A0-A9 select the starting column (A9 is a “Don’t
`Care” for x8).
`5. Whenever a boundary of the block is reached within
`a given sequence above, the following access wraps
`within the block.
`6. For a burst length of one, A0-A9 select the unique
`column to be accessed (A9 is a “Don’t Care” for x8),
`and Mode Register bit M3 is ignored.
`
`NOTE:
`
`M8
`
`M7
`
`M6-M0
`
`Operating Mode
`
`Defined
`
`Standard Operation
`
`-
`
`All other states reserved
`
`0 -
`
`0 -
`
`Write Burst Mode
`
`Programmed Burst Length
`
`Single Location Access
`
`M9
`
` 0 1
`
`Figure 1
`MODE REGISTER DEFINITION
`
`16 Meg: x4, x8 SDRAM
`16MSDRAMx4x8.p65 – Rev. 3/98
`
`8
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`ª 1998, Micron Technology, Inc.
`
`HP Exhibit 1009 - Page 8
`
`

`

`16 MEG: x4, x8
`SDRAM
`
`CAS Latency
`The CAS latency is the delay, in clock cycles, between the
`registration of a READ command and the availability of the
`first piece of output data. The latency can be set to 1, 2 or 3
`clocks.
`If a READ command is registered at clock edge n, and the
`latency is m clocks, the data will be available by clock edge
`n + m. The DQs will start driving as a result of the clock edge
`one cycle earlier (n + m - 1) and, provided that the relevant
`access times are met, the data will be valid by clock edge
`n + m. For example, assuming that the clock cycle time is
`such that all relevant access times are met, if a READ
`command is registered at T0, and the latency is programmed
`to two clocks, the DQs will start driving after T1 and the
`data will be valid by T2, as shown in Figure 2. Table 2 below
`indicates the operating frequencies at which each CAS
`latency setting can be used.
`
`T0
`
`T1
`
`T2
`
`CLK
`
`Reserved states should not be used, as unknown opera-
`tion or incompatibility with future versions may result.
`
`Operating Mode
`The normal operating mode is selected by setting M7 and
`M8 to zero; the other combinations of values for M7 and M8
`are reserved for future use and/or test modes. The pro-
`grammed burst length applies to both READ and WRITE
`bursts.
`Test modes and reserved states should not be used be-
`cause unknown operation or incompatibility with future
`versions may result.
`
`Write Burst Mode
`When M9 = 0, the burst length programmed via M0-M2
`applies to both READ and WRITE bursts; when M9 = 1, the
`programmed burst length applies to READ bursts, but
`write accesses are single-location (nonburst) accesses.
`
`Table 2
`CAS LATENCY
`ALLOWABLE OPERATING
`FREQUENCY (MHz)
`CAS
`LATENCY = 2
`£ 83
`£ 66
`
`CAS
`LATENCY = 1
`£ 33
`£ 33
`
`CAS
`LATENCY = 3
`£ 125
`£ 100
`
`SPEED
`-8A/B/C
`-10
`
`
`(cid:0) (cid:0)(cid:0)
`(cid:0)NOP
`COMMAND(cid:0)
`READ
`
`(cid:0)(cid:0)
`t
`tOH
`LZ
`
`(cid:0)(cid:0)
`(cid:0)(cid:0)
`
`(cid:0)(cid:0) DOUT
`(cid:0)(cid:0)
`
`DQ
`
`tAC
`
`CAS Latency = 1
`
`T0
`
`T1
`
`T2
`
`T3
`
`CLK
`
`COMMAND
`
`(cid:0)(cid:0)
`
`DQ
`
`
`(cid:0)(cid:0)
`
`(cid:0)(cid:0)
`
`(cid:0)(cid:0)
`READ
` NOP (cid:0)(cid:0)NOP
`
`
`
`(cid:0)(cid:0)
`t
`tOH
`LZ
`
`(cid:0)(cid:0)
`
`(cid:0)
`
`(cid:0)(cid:0) DOUT
`
`tAC
`
`CAS Latency = 2
`
`T1
`
`T2
`
`T3
`
`T4
`
`T0
`(cid:0)
`CLK
`(cid:0)(cid:0)
`
`(cid:0)
`
`(cid:0)(cid:0)
`(cid:0)(cid:0)NOP NOP
`COMMAND(cid:0)
`(cid:0)
`READ
`NOP
`
`
`(cid:0)(cid:0)
`
`(cid:0)(cid:0)DOUT(cid:0)(cid:0)
`
`(cid:0) (cid:0)(cid:0) (cid:0)
`t
`tOH
`(cid:0)
`LZ
`DQ
`(cid:0)(cid:0)
`(cid:0)(cid:0)
`
`(cid:0)(cid:0)
`
`(cid:0) (cid:0)(cid:0)
`
`DON’T CARE
`
`UNDEFINED
`
`tAC
`
`CAS Latency = 3
`
`Figure 2
`CAS LATENCY
`
`16 Meg: x4, x8 SDRAM
`16MSDRAMx4x8.p65 – Rev. 3/98
`
`9
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`ª 1998, Micron Technology, Inc.
`
`HP Exhibit 1009 - Page 9
`
`

`

`16 MEG: x4, x8
`SDRAM
`
`COMMANDS
`Truth Table 1 provides a quick reference of available
`commands. This is followed by a verbal description of each
`command. Two additional Truth Tables appear following
`
`the Operation section; these tables provide current state/
`next state information.
`
`TRUTH TABLE 1 – Commands and DQM Operation
`(Notes: 1)
`
`NAME (FUNCTION)
`COMMAND INHIBIT (NOP)
`NO OPERATION (NOP)
`ACTIVE (Select bank and activate row)
`READ (Select bank and column and start READ burst)
`WRITE (Select bank and column and
`start WRITE burst)
`BURST TERMINATE
`PRECHARGE (Deactivate row in bank or banks)
`AUTO REFRESH or
`SELF REFRESH (Enter self refresh mode)
`LOAD MODE REGISTER
`Write Enable/Output Enable
`Write Inhibit/Output High-Z
`
`DQs NOTES
`ADDR
`CS# RAS# CAS# WE# DQM
`X
`X
`H
`X
`X
`X
`X
`X
`X
`L
`H
`H
`H
`X
`X
`L
`L
`H
`H
`X Bank/Row
`X
`L
`H
`L
`H
`X
`Bank/Col
`L
`H
`L
`L
`X
`Bank/Col Valid
`
`3
`4
`4
`
`L
`L
`L
`
` L
`-
`-
`
`H
`L
`L
`
`L
`-
`-
`
`H
`H
`L
`
`L
`-
`-
`
`L
`L
`H
`
`L
`-
`-
`
`X
`X
`X
`
`X
`L
`H
`
`X
`Code
`X
`
`Active
`X
`X
`
`5
`6, 7
`
`Op-code
`-
`-
`
`X
`Active
`High-Z
`
`2
`8
`8
`
`NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
`2. A0-A10 and BA define the op-code written to the Mode Register.
`3. A0-A10 provide row address, and BA determines which bank is made active (BA LOW = Bank 0 and BA
`HIGH = Bank 1).
`4. A0-A9 (A9 is a “Don’t Care” for x8) provide column address; A10 HIGH enables the auto precharge feature
`(nonpersistent), while A10 LOW disables the auto precharge feature; BA determines which bank is being
`read from or written to (BA LOW = Bank 0 and BA HIGH = Bank 1).
`5. For A10 LOW, BA determines which bank is being precharged (BA LOW = Bank 0 and BA HIGH = Bank 1);
`for A10 HIGH, both banks are precharged and BA is a “Don’t Care.”
`6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
`7.
`Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
`8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
`
`16 Meg: x4, x8 SDRAM
`16MSDRAMx4x8.p65 – Rev. 3/98
`
`10
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`ª 1998, Micron Technology, Inc.
`
`HP Exhibit 1009 - Page 10
`
`

`

`COMMAND INHIBIT
`The COMMAND INHIBIT function prevents new com-
`mands from being executed by the SDRAM, regardless of
`whether the CLK signal is enabled. The SDRAM is effec-
`tively deactivated, or deselected.
`
`NO OPERATION (NOP)
`The NO OPERATION (NOP) command is used to per-
`form a NOP to an SDRAM which is selected (CS# is LOW).
`This prevents unwanted commands from being registered
`during idle or wait states.
`
`LOAD MODE REGISTER
`The Mode Register is loaded via inputs A0-A10 and BA.
`See Mode Register heading in Register Definition section.
`The LOAD MODE REGISTER command can only be issued
`when both banks are idle, and a subsequent executable
`command cannot be issued until tMRD is met.
`
`ACTIVE
`The ACTIVE command is used to open (or activate) a row
`in a particular bank for a subsequent access. The value on
`the BA input selects the bank, and the address provided on
`inputs A0-A10 selects the row. This row remains active (or
`open) for accesses until a PRECHARGE command is issued
`to that bank. A PRECHARGE command must be issued
`before opening a different row in the same bank.
`
`READ
`The READ command is used to initiate a burst read access
`to an active row. The value on the BA input selects the bank,
`and the address provided on inputs A0-A9 (A9 is a “Don’t
`Care” on x8) selects the starting column location. The value
`on input A10 determines whether or not AUTO
`PRECHARGE is used. If AUTO PRECHARGE is selected,
`the row being accessed will be precharged at the end of the
`READ burst; if AUTO PRECHARGE is not selected, the row
`will remain open for subsequent accesses. Read data ap-
`pears on the DQs, subject to the logic level on the DQM
`input, two clocks earlier. If the DQM signal was registered
`HIGH, the DQs will be High-Z two clocks later; if the DQM
`signal was registered LOW, the DQs will provide valid
`data.
`
`WRITE
`The WRITE command is used to initiate a burst write
`access to an active row. The value on the BA input selects the
`bank, and the address provided on inputs A0-A9 (A9 is a
`“Don’t Care” on x8) selects the starting column location.
`The value on input A10 determines whether or not AUTO
`PRECHARGE is used. If AUTO PRECHARGE is selected,
`the row being accessed will be precharged at the end of the
`
`16 MEG: x4, x8
`SDRAM
`
`WRITE burst; if AUTO PRECHARGE is not selected, the
`row will remain open for subsequent accesses. Input data
`appearing on the DQs is written to the memory array
`subject to the DQM input logic level appearing coincident
`with the data. If the DQM signal is registered LOW, the
`corresponding data will be written to memory; if the DQM
`signal is registered HIGH, the corresponding data inputs
`will be ignored, and a WRITE will not be executed to that
`location.
`
`PRECHARGE
`The PRECHARGE command is used to deactivate the
`open row in a particular bank or the open row in both
`banks. The bank(s) will be available for a subsequent row
`access some specified time (tRP) after the PRECHARGE
`command is issued. Input A10 determines whether one or
`both banks are to be precharged, and in the case where only
`one bank is to be precharged, input BA selects the bank.
`Otherwise BA is treated as a “Don’t Care.” Once a bank has
`been precharged, it is in the idle state and must be activated
`prior to any READ or WRITE commands being issued to
`that bank.
`
`AUTO PRECHARGE
`AUTO PRECHARGE is a feature which performs the
`same individual-bank PRECHARGE function described
`above, without requiring an explicit command. This is
`accomplished by using A10 to enable AUTO PRECHARGE
`in conjunction with a specific READ or WRITE command.
`A PRECHARGE of the bank/row that is addressed with the
`READ or WRITE command is automatically performed
`upon completion of the READ or WRITE burst, except in the
`full-page burst mode, where AUTO PRECHARGE does not
`apply. AUTO PRECHARGE is nonpersistent in that it is
`either enabled or disabled for each individual READ or
`WRITE command.
`AUTO PRECHARGE ensures that the PRECHARGE is
`initiated at the earliest valid stage within a burst. The user
`must not issue another command until the precharge time
`(tRP) is completed. This is determined as if an explicit
`PRECHARGE command was issued at the earliest possible
`time, as described for each burst type in the Operation
`section of this data sheet.
`
`BURST TERMINATE
`The BURST TERMINATE command is used to truncate
`either fixed-length or full-page bursts. The most recently
`registered READ or WRITE command prior to the BURST
`TERMINATE command will be truncated, as shown in the
`Operation section of this data sheet.
`
`16 Meg: x4, x8 SDRAM
`16MSDRAMx4x8.p65 – Rev. 3/98
`
`11
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`ª 1998, Micron Technology, Inc.
`
`HP Exhibit 1009 - Page 11
`
`

`

`16 MEG: x4, x8
`SDRAM
`
`AUTO REFRESH
`AUTO REFRESH is used during normal operation of the
`SDRAM and is analagous to CAS#-BEFORE-RAS# (CBR)
`REFRESH in conventional DRAMs. This command is non-
`persistent, so it must be issued each time a refresh is
`required.
`The addressing is generated by the internal refresh con-
`troller. This makes the address bits a “Don’t Care” during
`an AUTO REFRESH command. The Micron 16Mb SDRAM
`requires all of its 4,096 rows to be refreshed every 64ms
`(tREF). Providing a distributed AUTO REFRESH command
`every 15.6m s will meet the refresh requirement and ensure
`that each row is refreshed. Alternatively, all 4,096 AUTO
`REFRESH commands can be issued in a burst at the mini-
`mum cycle rate (tRC) once every 64ms.
`
`SELF REFRESH
`The SELF REFRESH command can be used to retain data
`in the SDRAM, even if the rest of the system is powered
`down. When in the self refresh mode, the SDRAM retains
`data without external clocking. The SELF REFRESH com-
`
`mand is initiated like an AUTO REFRESH command except
`CKE is di