`
`
`
`
`
`
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`HP INC.
`
`Petitioner
`
`v.
`
`JAMES B. GOODMAN
`
`Patent Owner
`
`
`Case No. IPR2017-01994
`
`U.S. Patent No. 6,243,315
`
`
`
`DECLARATION OF DR. NADER BAGHERZADEH
`UNDER 37 C.F.R. § 1.68
`
`HP EXHIBIT 1002
`
`
`
`
`
`Case No. IPR2017-01994
`
`I, Nader Bagherzadeh, declare as follows:
`
`1.
`
`I am making this declaration at the request of HP Inc. (“HP”) in
`
`support of HP’s petition for Inter Partes review of U.S. Patent No. 6,243,315.
`
`This declaration includes Appendices A and B.
`
`2.
`
`I am being compensated for my services in this matter at the rate of
`
`$525/hour plus expenses. My compensation is not contingent upon the
`
`outcome of this proceeding.
`
`3.
`
`4.
`
`5.
`
`6.
`
`In preparing this declaration, I considered the following materials:
`
`the ’315 patent, attached as Exhibit 1001;
`
`the ’315 patent file history;
`
`U.S. Patent No. 5,600,605 to Schaefer (“Schaefer”), attached as
`
`Exhibit 1003;
`
`7.
`
`U.S. Patent No. 5,793,776 to Qureshi et al. (“Qureshi”), attached as
`
`Exhibit 1004;
`
`8.
`
`U.S. Patent No. 5,204,840 to Mazur (“Mazur”), attached as Exhibit
`
`1005;
`
`9.
`
`U.S. Patent No. 4,005,395 to Fosler, Jr. et. al. (“Fosler”), attached as
`
`Exhibit 1006;
`
`HP EXHIBIT 1002 – PAGE 1
`
`
`
`
`
`Case No. IPR2017-01994
`
`10. Reengineering the Curriculum: Design and Analysis of a New
`
`Undergraduate Electrical and Computer Engineering Degree at Carnegie Mellon
`
`University, Director et al., IEEE 1995, attached as Exhibit 1007;
`
`11. Micron Technology, Inc. Functional Specification for
`
`MT48LC4M4R1(S) SDRAM, attached as Exhibit 1008;
`
`12. Micron Technology, Inc. Data Sheet for MT48LC4M4A1/A2
`
`SDRAM, attached as Exhibit 1009; and
`
`13. Decision Instituting Inter Partes Review, Paper 6, IPR2015-01675
`
`(PTAB February 11, 2016), attached as Exhibit 1010.
`
`I.
`
`PROFESSIONAL BACKGROUND
`14. My Curriculum Vitae is attached hereto as Appendix A. I earned a
`
`bachelor’s degree in electrical engineering in 1977 from the University of Texas at
`
`Austin. In 1979 and 1987, respectively, I earned a master of science in electrical
`
`engineering and a doctorate degree in computer engineering from the University of
`
`Texas at Austin.
`
`15.
`
`I am currently a professor in the department of Electrical Engineering
`
`and Computer Science at the University of California, Irvine – a position I have
`
`held since 2003. Previously, from 1987 to 1992, I was an assistant professor in the
`
`Department of Electrical & Computer Engineering at the University of California,
`
`Irvine. Thereafter, from 1993 to 1997, I was an associate professor in the
`
`HP EXHIBIT 1002 – PAGE 2
`
`
`
`
`
`Case No. IPR2017-01994
`
`Department of Electrical & Computer Engineering at the University of California,
`
`Irvine. In 1998, I was promoted to Professor and Chair of the Department of
`
`Electrical Engineering at the University of California, Irvine. I held that position
`
`until 2003, when I assumed my current role with the Department. I was elected as
`
`an IEEE Fellow in 2014.
`
`16.
`
`I have been involved in design and development of digital systems for
`
`more than 30 years. While at AT&T Bell Labs in the early 1980’s, I worked on an
`
`interface card for T1 lines as part of a support R&D team for the design of the first
`
`#5ESS digital switches. I was responsible for design of the hardware and software
`
`of this board which included memory devices (EEPROM, DRAM, and SRAM).
`
`17. Since joining University of California, Irvine in 1987, I have been
`
`teaching, researching, and consulting regarding almost all aspects of memory
`
`design for high performance computer systems, including but not limited to
`
`DRAMs and SRAMs. In 2000, I became a cofounder of a high-tech company
`
`called Morpho Technologies, which was focused on the design and development of
`
`low power and high performance digital signal processors for mobile applications.
`
`As part of my duties as the chief technologist for the company, I evaluated patents,
`
`technical reports and presentations related to memory chip designs, DSPs, and
`
`parallel processing algorithms for mobile platforms.
`
`HP EXHIBIT 1002 – PAGE 3
`
`
`
`
`
`Case No. IPR2017-01994
`
`18. For the Morpho project, I designed, developed and tested the key
`
`memory block responsible for exchanging data between the host processor and the
`
`slave processor (array processor). This subcomponent was designed to meet the
`
`power and performance requirements of the architecture for mobile embedded
`
`applications. I also designed the main data storage of the microcontroller (Tiny
`
`RISC) that was used for storing temporary data, as is the case for synchronous
`
`random-access memory (SRAM), which is a type of volatile memory. I was a
`
`primary contributor for the prototype board design for the Morpho device, which
`
`was integrated with DRAMs, FPGA, and other prototype board components.
`
`19. As part of my teaching and research experience, I was responsible for
`
`developing circuits, electronic modules, and related architectures for memory
`
`systems. For the multithreaded superscalar DSP that was developed at UCI, I
`
`designed the memory block responsible for managing out-of-order execution of
`
`data registers corresponding to different threads. I also designed the original
`
`temporary data storage subcomponents for the VLIW processor, ViPER, and for
`
`the original Tiny RISC processor. I have done extensive work on the design of
`
`efficient data correction schemes for NAND flash memory circuits.
`
`HP EXHIBIT 1002 – PAGE 4
`
`
`
`
`
`Case No. IPR2017-01994
`
`II. RELEVANT LEGAL STANDARDS
`I have been asked to provide my opinion whether the prior art I
`20.
`
`reviewed would render Claims 1, 5, 10, and 16 of the ’315 patent anticipated or
`
`obvious to a person of ordinary skill in the art at the time of the alleged invention.
`
`21. My background and training is in engineering. The opinions I express
`
`in this declaration involve the application of my engineering knowledge and
`
`experience to the evaluation of certain prior art with respect to the ’315 patent.
`
`Given that I have a lay person’s knowledge of patent law, I have requested that the
`
`attorneys from Shelton Coburn LLP, who represent HP, provide me with guidance
`
`as to the applicable patent law in this matter. The paragraphs below express my
`
`understanding of how I must apply current principles related to patent validity in
`
`my analysis.
`
`22.
`
`It is my understanding that in an Inter Partes review, the Patent Office
`
`must construe the claims by giving the claim terms their broadest reasonable
`
`interpretation consistent with the specification.
`
`23.
`
`It is my understanding that a claim is obvious under 35 U.S.C. § 103 if
`
`the differences between the invention and the prior art are such that the subject
`
`matter as a whole would have been obvious to a person of ordinary skill in the art
`
`at the time of the alleged invention. It is also my understanding that an obviousness
`
`analysis must take into account the scope and content of the prior art, the
`
`HP EXHIBIT 1002 – PAGE 5
`
`
`
`
`
`Case No. IPR2017-01994
`
`differences between the claimed subject matter and the prior art, and the level of
`
`ordinary skill in the art at the time of the invention.
`
`24.
`
`It is my understanding that to assess the differences between prior art
`
`and the claimed subject matter, 35 U.S.C. § 103 requires the claimed invention to
`
`be considered as a whole. This “as a whole” assessment requires showing that one
`
`of ordinary skill in the art at the time of invention, confronted by the same
`
`problems as the inventor and with no knowledge of the claimed invention, would
`
`have selected the elements from the prior art and combined them in the claimed
`
`manner.
`
`25.
`
`It is my understanding that in determining the scope and content of the
`
`prior art, a reference is considered appropriate prior art if it falls within the field of
`
`the inventor’s endeavor. In addition, a reference is prior art if it is reasonably
`
`pertinent to the particular problem with which the inventor was involved. A
`
`reference is reasonably pertinent if it logically would have commended itself to an
`
`inventor’s attention in considering his problem. If a reference relates to the same
`
`problem as the claimed invention, that supports use of the reference as prior art in
`
`an obviousness analysis.
`
`26.
`
`It is also my understanding that there are several specifically
`
`recognized rationales for combining references or modifying a reference to show
`
`obviousness of claimed subject matter. Some of these rationales include:
`
`HP EXHIBIT 1002 – PAGE 6
`
`
`
`
`
`Case No. IPR2017-01994
`
`combining prior art elements according to known methods to yield predictable
`
`results; simple substitution of one known element for another to obtain predictable
`
`results; a predictable use of prior art elements according to their established
`
`functions; applying a known technique to a known device (method or product)
`
`ready for improvement to yield predictable results; choosing from a finite number
`
`of identified, predictable solutions, with a reasonable expectation of success; and
`
`some teaching, suggestion, or motivation in the prior art that would have led one of
`
`ordinary skill to modify the prior art reference or to combine prior art reference
`
`teachings to arrive at the claimed invention. It is also my understanding this list is
`
`not exhaustive.
`
`III. PERSON OF ORDINARY SKILL IN THE ART
`It is my understanding that when interpreting the claims of the ’315
`27.
`
`patent, I must do so based on the perspective of one of ordinary skill in the art at the
`
`relevant priority date. My understanding is that the earliest alleged priority date of
`
`the ’315 patent is December 31, 1999.
`
`28. The ’315 patent relates to a volatile memory system with data
`
`retention capabilities in low power situations. Specifically, as stated in the Abstract
`
`of the ’315 patent, it pertains to volatile solid-state memory devices that retain
`
`information when an electrical power source is applied to the memory devices
`
`within a predetermined voltage range.
`
`HP EXHIBIT 1002 – PAGE 7
`
`
`
`
`
`Case No. IPR2017-01994
`
`29. Volatile memory systems typically include only volatile memory
`
`devices, such as dynamic random access memories (DRAM) that are subject to
`
`loss of data in the absence of electrical power. Such volatile memory devices,
`
`however, typically include a self-refresh mode that requires lower electrical power
`
`than during normal operations.
`
`30. Further, volatile memory devices are typically configured to interface
`
`with a memory controller of a host computer system for regular operation. Once
`
`connected with the memory controller of the computer system, the volatile
`
`memory devices receive power for operation and instructions for various
`
`computing processes.
`
`31.
`
`In my opinion, a person of ordinary skill in the art for the ’315 patent
`
`in December 1999 would have a bachelor’s degree in electrical, electronics, or
`
`computer engineering, or a related discipline; or the equivalent training or
`
`experience in electrical, electronics, or computer engineering, or a related
`
`discipline. The person would also have an additional two or more years of
`
`experience in computer hardware, including the use of computer memory.
`
`32. A person having a bachelor’s degree in electrical, electronics,
`
`computer engineering, or a related discipline would have experience with
`
`memories and computer architecture. The additional two or more years of
`
`experience in experience in computer systems, circuits, electronics, or a related
`
`HP EXHIBIT 1002 – PAGE 8
`
`
`
`
`
`Case No. IPR2017-01994
`
`disciple would provide practical experience required to address issues such as low
`
`power backup for volatile memories.
`
`33. The curriculum of a bachelor’s degree program in computer,
`
`electronics, or a related discipline typically includes courses pertaining to circuit
`
`design from component parts, including building complex systems from basic
`
`building blocks, and interconnecting digital elements and circuit elements. Such
`
`courses also include design for electronic memory components. For example, the
`
`bachelor’s degree program in electrical and computer engineering at Carnegie
`
`Mellon University includes the following course requirements:
`
`• Building Complex Systems from Basic Building Blocks
`
`• Interconnecting digital elements
`
`• Interconnecting circuit elements . . .
`
`• Dealing with the system: memory, programmed, and hardwired control.
`
`Ex. 1007, pp. 1255-56 & Table 2. With an additional 2 or more years of
`
`experience in memory related circuits, a POSITA would have the
`
`prerequisite skill to take the memory controller from Qureshi and connect
`
`it to the SDRAM of Schaefer, and further to combine the teachings of
`
`Qureshi and Schaefer with the secondary power supply features of Mazur.
`
`34.
`
`In my experience, this bachelor’s degree program is not unique to
`
`Carnegie Mellon University. Many other universities offer similar courses and
`
`HP EXHIBIT 1002 – PAGE 9
`
`
`
`
`
`Case No. IPR2017-01994
`
`programs of study at the bachelor’s level for electrical, electronics, and computer
`
`engineering, or a related discipline.
`
`35. A POSITA, with this level of experience, would be capable of reading
`
`and understanding the open literature (including patents) related to memory system
`
`design and would be able to modify an existing process based on the teachings
`
`found in the literature.
`
`IV. SUMMARY OF PRIOR ART
`36. Volatile memories, such as dynamic random access memory (DRAM)
`
`and its subset, synchronous dynamic random access memory (SDRAM), must have
`
`their contents “refreshed” electrically periodically or information will be lost over
`
`time. Early systems had external circuitry to refresh the DRAM, as illustrated in
`
`U.S. Patent No. 4,005,395 to Fosler, Jr. et al. (Ex. 1006).
`
`37. DRAMs have included self-refresh modes since at least the mid-
`
`1990s, in which the DRAM or SDRAM memory chip refreshes itself
`
`automatically. See Ex. 1003, U.S. Patent No. 5,600,605 to Schaefer, 1:14-17 (filed
`
`June 7, 1995). During the self-refresh mode, the power consumption is reduced in
`
`comparison to the normal operation of the SDRAM.
`
`38. As “refresh” is a low-power operation, a secondary power source may
`
`provide the low power required for operation. The secondary power source may be
`
`a temporary power source. The use of a secondary power source for providing
`
`HP EXHIBIT 1002 – PAGE 10
`
`
`
`
`
`Case No. IPR2017-01994
`
`temporary low power during refresh modes was well-known in the art since at least
`
`May 8, 1975, as taught by Fosler. For example, Fosler discloses “[d]ynamic
`
`memory devices [that] are commercially available as MOS random access memory
`
`(RAM) devices” configured so that “[d]uring the refresh address mode, should the
`
`high power [be lost], low power output . . . will be sufficient to generate a refresh
`
`signal.” Fosler, 2:35-38 and 4:49-56. Fosler specifically discloses that “when
`
`operating from standby power there is very little drain on the battery or always-on
`
`power source.” Id., 5:31-35.
`
`Schaefer
`A.
`39. Schaefer (Ex. 1003) is assigned to Micron Technology Inc. and issued
`
`on February 4, 1997. Schaefer discloses an SDRAM chip that includes power
`
`down and self refresh modes to retain data with reduced power requirements.
`
`Specifically, Schaefer explains that a low-power self refresh mode is in an
`
`SDRAM chip (e.g., Micron’s MT48LC4M4R1 SDRAM chip), in which the
`
`amount of electrical energy drawn from the computer system is reduced. Id. 3:58-
`
`61, 3:21-26 & 6:56-58. Schaefer expressly incorporates the functional specification
`
`of Micron’s MT48LC4M4R1 SDRAM chip by reference. Id., 3:3-8. I also
`
`understand that “incorporation by reference” is a term of art that means that the
`
`entire disclosure of the Micron functional specification is part of the specification
`
`of Schaefer.
`
`HP EXHIBIT 1002 – PAGE 11
`
`
`
`
`
`Case No. IPR2017-01994
`
`40.
`
`I located the functional specification for the Micron SDRAM
`
`referenced in Schaefer. See Ex. 1008, Micron Technology, Inc. Functional
`
`Specification for MT48LC4M4R1(S) (“Micron Functional Specification”). This
`
`functional specification is dated April 1994 and in my opinion, was the functional
`
`specification incorporated by reference in Schaefer, which was filed in June 1995.
`
`I also located a Micron data sheet for the MT48LC4M4A1/A2 SDRAM (“Micron
`
`Data Sheet”), attached as Ex. 1009. Although the Micron Data Sheet is dated
`
`March 1998, in my opinion it is a reliable source of information regarding the
`
`SDRAM referenced in Schaefer and consistent with the MT48LC4M4R1
`
`functional specification incorporated by reference into Schaefer (Ex. 1008).
`
`41. Both the Micron Functional Specification and Micron Data Sheet
`
`describe the self refresh mode. See Ex. 1008, 1 (“SELF REFRESH (for low-power,
`
`data-retention operation”); Ex. 1009, 12. The Micron Data Sheet provides a timing
`
`diagram for self refresh mode. Micron Data Sheet, 37. The specifications for the
`
`Micron SDRAM show that in self refresh mode, the chip only draws 1 or 2 mA of
`
`current, compared to 90 or 105 mA in normal operation. Id., 29. Thus, in self
`
`refresh mode the power consumption is reduced in comparison to the normal
`
`operation of the SDRAM.
`
`HP EXHIBIT 1002 – PAGE 12
`
`
`
`
`
`Case No. IPR2017-01994
`
`42. Fig. 1 of Schaefer is a functional block diagram of the SDRAM
`
`memory device described in the patent, such as Micron’s MT48LC4M4R1
`
`SDRAM memory chip. Annotated Fig. 1 of Schaefer is shown below:
`
`
`Schaefer, Fig. 1.
`
`
`
`43.
`
`In my opinion, a POSITA would understand that the SDRAM of
`
`Schaefer is a type of DRAM.
`
`B. Qureshi
`44. Qureshi (Ex. 1004) is assigned to Samsung and issued on August 11,
`
`1998. Qureshi teaches a memory controller for SDRAM chips, such as the Micron
`
`SDRAM chip described in Schaefer. Qureshi’s memory controller is a test
`
`controller that is configured to place a connected SDRAM chip into a low power
`
`self-refresh mode to retain the existing data. Qureshi, Abstract.
`
`HP EXHIBIT 1002 – PAGE 13
`
`
`
`
`
`Case No. IPR2017-01994
`
`C. Mazur
`45. Mazur (Ex. 1005) issued on April 20, 1993. Mazur teaches the use of
`
`a battery as an alternative low power source (e.g., a rechargeable battery”) to drive
`
`a DRAM device in a low power refresh mode. For example, Mazur discloses
`
`“methods [to] back up the dynamic RAM memory of the associated computer
`
`system in the event of a power loss or outage.” Mazur, 2:24-26. Mazur discloses
`
`corresponding hardware that includes “a power loss detection circuit, an
`
`independent power supply, a continuously rechargeable battery which is recharged
`
`by the independent power supply, a standby refresh circuit, a switch-over circuit,
`
`address and data busses, and an address control circuit, all of which are in addition
`
`to and augment the existing conventional computer circuits.” Id., 2:6-14.
`
`V. CLAIM CONSTRUCTION
`It is my understanding that the claims are to be given their broadest
`46.
`
`reasonable interpretation to a POSITA at the time of the alleged invention in an
`
`inter partes review. I have applied that standard in my invalidity analysis set forth
`
`in Section VI below. In its decision instituting inter partes review in IPR2015-
`
`01675 on the same grounds as presented in this declaration, the Board indicated
`
`that it did not need to construe any claim terms of claims 1, 5, 10 and 16. See Ex.
`
`1010, Decision Instituting Inter Partes Review, Paper 6, IPR2015-01675 at 6
`
`(PTAB February 11, 2016).
`
`HP EXHIBIT 1002 – PAGE 14
`
`
`
`
`
`VI.
`
`Case No. IPR2017-01994
`
`INVALIDITY OF CLAIMS 1, 5, 10 AND 16
`A. Obviousness over Schaefer in View of Qureshi
`
`Obviousness of Claims 1 and 5
`1.
`47. Claims 1 and 5 of the ’315 patent are obvious over Schaefer in view of
`
`Qureshi. Attached as Appendix B is a claim chart showing how and where each
`
`limitation of Claims 1 and 5 is disclosed by Schaefer in view of Qureshi.
`
`a. Motivation to Combine and Predictability of the Art
`48. A POSITA would be motivated to combine Schaefer with Qureshi,
`
`because the functional electronic modules of Schaefer and Qureshi are configured
`
`to work together. For example, Schaefer teaches an SDRAM memory (e.g., Micron
`
`MT48LC4M4R1 chip) that includes a low power self refresh mode used to retain
`
`data in low power situations (Schaefer, 3:3-6); and Qureshi teaches a memory
`
`controller that is configured to place any SDRAM memory into a low power self-
`
`refresh mode, for the purposes of data retention during testing (Qureshi, 1:65-2:2).
`
`49. Schaefer and Qureshi also disclose that their respective teachings are
`
`merely exemplary modules that a POSITA may apply, in a variety of ways,
`
`without departing from the scope of their corresponding functions. For example,
`
`Schaefer discloses that “those of ordinary skill in the art [would appreciate] that a
`
`wide variety of alternate and/or equivalent implementations calculated to achieve
`
`the same purposes may be substituted . . . without departing from the scope of the
`
`HP EXHIBIT 1002 – PAGE 15
`
`
`
`
`
`Case No. IPR2017-01994
`
`present invention.” Schaefer, 10:25-33. Qureshi explains that “in accordance with
`
`[its] invention, memory such as SDRAMs are put into self-refresh mode while
`
`JTAG testing is performed. Self refresh is a refresh mode available in some
`
`memory and is preferred for data retention and low power operation.” Qureshi,
`
`1:63-67.
`
`50. As Schaefer and Qureshi provide that their respective disclosures are
`
`understood by a POSITA, and may be modified, altered or adapted, while retaining
`
`their corresponding expected functions, the prior art teaches that the field of the
`
`’315 patent is very predictable. Accordingly, combination of Schaefer with
`
`Qureshi does not stray from the scope and spirit of each respective electronic
`
`module corresponding to each reference. Each reference is merely an independent
`
`electronic module, which performs a specific function, and which may be
`
`combined with another, while retaining their functions and providing a unified
`
`overall function.
`
`51. The ’315 patent states that the invention is in a predictable field,
`
`where a POSITA would understand that multiple components may be combined,
`
`so long as the function of each is maintained: “[i]t is evident that those skilled in
`
`the art may now make numerous uses and modifications of and departures from the
`
`specific embodiments described herein without departing from the inventive
`
`concepts.” ’315 patent, 13:9-12.
`
`HP EXHIBIT 1002 – PAGE 16
`
`
`
`
`
`Case No. IPR2017-01994
`
`52. A POSITA at the time of the alleged ’315 invention would possess the
`
`requisite skill to combine basic electrical components or modules in an expected or
`
`natural way (as described in each reference) to meet the claimed limitations,
`
`because the teachings in the references provide the requisite inputs, the functions,
`
`and the corresponding outputs, which are not changed in the proposed
`
`combinations of prior art.
`
`53. For example, Schaefer teaches that “[a]ll the input and output signals
`
`of SDRAM 20, with the exception of the CKE input signal during power down and
`
`self refresh modes, are synchronized to the active going edge. . . of the CLK
`
`signal.” Schaefer, 3:20-25 (references to the figures omitted). Qureshi teaches a
`
`memory controller to provide signals that would “place an SDRAM in a self-
`
`refresh mode,” such that when “the self-refresh mode is entered[, the] SDRAM
`
`ignores all inputs other than a CKE (clock enable) pin while in self-refresh state.”
`
`Qureshi, Abstract & 5:49-51. A POSITA would understand from these teachings
`
`the signals that are required from the memory controller of Qureshi to place the
`
`SDRAM device of Schaefer into a low power self-refresh mode.
`
`Claim 1
`b.
`54. As to limitation 1.a, “[a] memory system for use in a computer
`
`system,” this limitation is disclosed by the combination of Schaefer and Qureshi.
`
`Specifically, Schaefer discloses an application using Micron’s MT48LC4M4R1
`
`HP EXHIBIT 1002 – PAGE 17
`
`
`
`
`
`Case No. IPR2017-01994
`
`SDRAM chip. Schaefer, 3:1-8. Based on these disclosures, a POSITA would
`
`understand that the SDRAM memory device of Schaefer is part of a memory
`
`system for use in a computer system.
`
`55. Qureshi teaches a memory controller for providing testing signals to
`
`SDRAM devices. Qureshi, 2:3-6 and Fig. 1. Accordingly, a POSITA would
`
`understand that the memory controller of Qureshi, along with the SDRAM of
`
`Schaefer form a memory system. In this system, the SDRAM of Schaefer is
`
`connected to receive test signals from Qureshi’s memory controller. This reasoning
`
`is supported, because Schaefer discloses that “alternate and/or equivalent
`
`implementations calculated to achieve the same purposes may be substituted . . .
`
`without departing from the scope of the present invention.” Schaefer, 10:25-33.
`
`The SDRAM of Schaefer is a familiar functional electronic component that may be
`
`taken as described and combined with the memory controller of Qureshi, which is
`
`also a familiar functional electronic component that may be taken as described.
`
`Integrating these two components together does not depart from the teachings of
`
`either reference, but combines the teachings by utilizing the signals from the
`
`memory controller, as taught by Qureshi, to operate the SDRAM of Schaefer in the
`
`way that is explicitly contemplated and intended by Qureshi.
`
`56. As to limitation 1.b, “a plurality of volatile solid state memory devices
`
`that retain information when an electrical power source is applied to said memory
`
`HP EXHIBIT 1002 – PAGE 18
`
`
`
`
`
`Case No. IPR2017-01994
`
`devices within a predetermined voltage range,” this limitation is disclosed in
`
`Schaefer. Specifically, a POSITA would understand that Schaefer discloses a
`
`volatile memory that includes two banks - bank 0 and bank 1, that are powered by a
`
`nominal voltage of 3.3V on power pin Vcc. Schaefer, 3:14-17; Micron Functional
`
`Specification, 1; Micron Data Sheet, 1. Additionally, each bank includes a plurality
`
`of volatile solid state memory devices. A POSITA would also understand that the
`
`SDRAM of Schaefer—like all DRAM and SDRAM chips—has a range of
`
`allowable voltage for optimal functioning, e.g., 3.3V ±0.3V. See Micron
`
`Functional Specification, 1; Micron Data Sheet, 1. Accordingly, such a
`
`predetermined voltage range would range from 3.0 to 3.6V for the two memory
`
`banks in the SDRAM of Schaefer.
`
`57. As to limitation 1.c, “capable of being placed in a self refresh mode,”
`
`Schaefer discloses that its SDRAM is configured to operate in accordance with “a
`
`SELF-REFRESH command.” Schaefer, 3:58-61.
`
`58. As to limitation 1.d, “said memory devices having address lines and
`
`control lines,” this limitation is disclosed in Schaefer. The ’315 patent describes
`
`the control lines as “/CAS, /RAS and /WE.” ’315 Patent, 9:66-67. Specifically,
`
`Schaefer discloses a volatile memory that receives “control signals including a row
`
`address strobe (RAS*) signal on a RAS* pin, column address strobe (CAS*) signal
`
`HP EXHIBIT 1002 – PAGE 19
`
`
`
`
`
`Case No. IPR2017-01994
`
`on a CAS* pin, and a write enable (WE*) signal on a WE* pin,” as well as
`
`“address bits on input pins A0-A10.” Schaefer, 3:30-33 & 4:19-21.
`
`59. As to limitation 1.e, “a control device for selectively electrically
`
`isolating said memory devices from respective address lines and respective control
`
`lines so that when said memory devices are electrically isolated, any signals
`
`received on said respective address lines and respective control lines do not reach
`
`said memory devices,” this limitation is disclosed by Schaefer in view of Qureshi.
`
`Qureshi teaches a memory controller for providing a requisite signal to place
`
`Schaefer’s SDRAM memory into self-refresh mode, in which all access signals are
`
`ignored, which a POSITA would understand corresponds to electrically isolating
`
`the SDRAM. See Qureshi, Abstract & 1:65-2:2.
`
`60. Schaefer discloses that its volatile memory includes a pin for
`
`receiving the requisite signal that would place it in a “don’t care” state, thereby
`
`inhibiting it from responding to any requests. The “don’t care” state represents the
`
`electrical isolation. Schaefer, 6:56-58.
`
`61. Schaefer teaches that the SDRAM memory device is configured for a
`
`self-refresh mode when the SELF-REFRESH command is received. Schaefer,
`
`3:58-61. In self refresh mode, the memory is in a “don’t care” mode. Micron Data
`
`Sheet, 12, 37. The “don’t care” state renders the memory device as non-responsive
`
`HP EXHIBIT 1002 – PAGE 20
`
`
`
`
`
`Case No. IPR2017-01994
`
`to requests in the form of input and control signals received at the memory device.
`
`Id. Accordingly, the memory device is inhibited or electrically isolated.
`
`62. As to limitation 1.f, “a memory access enable control device coupled
`
`to said control device and to said control lines for determining when said memory
`
`system is not being accessed and for initiating a low power mode for said memory
`
`system,” this limitation is disclosed by Schaefer in view of Qureshi. Schaefer
`
`discloses a command controller in the SDRAM (“memory access enable device”),
`
`which includes circuitry for decoding read/write commands from Qureshi’s
`
`memory controller (“control device”). Schaefer, 3:28-42; Qureshi, Abstract.
`
`63. Schaefer also discloses that the command controller of its SDRAM
`
`(“memory access enable device”) decodes commands from the Qureshi memory
`
`controller (“control device”) to determine which memory bank should be
`
`addressed, including decoding Qureshi’s signal that places Schaefer’s SDRAM
`
`into power down or self-refresh mode, where all access signals are ignored
`
`(“memory system is not being accessed and for initiating a low power mode”).
`
`Schaefer, 3:20-25; Qureshi, 5:49-51.
`
`64. As to limitation 1.g, “wherein said control device electrically isolates
`
`said memory devices and places said memory devices in said self-refresh mode,
`
`thereby reducing the amount of electrical energy being drawn from an electrical
`
`power supply for said computer system,” Qureshi discloses that its memory
`
`HP EXHIBIT 1002 – PAGE 21
`
`
`
`
`
`Case No. IPR2017-01994
`
`controller (“control device”) causes Schaefer’s SDRAM to ignore all signals and to
`
`go into a low power self-refresh mode, thereby reducing the amount of electrical
`
`energy being drawn from a primary electrical power supply of a connected
`
`computer system. Qureshi, 1:65-2:2.
`
`Claim 5
`c.
`65. Schaefer and Qureshi disclose functional electrical modules for
`
`SDRAM memory devices. SDRAM is a synchronous variation (and subset) of
`
`DRAM memory devices. Accordingly, a claim that recites a DRAM memory
`
`device is inclusive of SDRAM memory devices, unless indicated otherwise. As
`
`Schaefer in view of Qureshi invalidates claim 1, from which claim 5 depends, the
`
`disclosure in these references also invalidates claim 5, because the SDRAM is a
`
`type of DRAM.
`
`Schaefer in View of Qureshi, Further in View of Mazur
`B.
`66. Each limitation of claims 10 and 16 is disclosed by Schaefer in view
`
`of Qureshi, and further in view of Mazur.
`
`Obviousness of Claims 10 and 16
`1.
`67. Claims 10 and 16 of the ’315 patent are obvious over Schaefer in view
`
`of Qureshi, and further in view of Mazur. Attached as Appendix B is claim chart
`
`showing how and where each limitation of Claims 10 and 16 is disclosed by
`
`Schaefer in view of Qureshi, and further in view of Mazur.
`
`a. Motivation to Combine and Predictability of the Art
`
`HP EXHIBIT 1002 – PAGE 22
`
`
`
`
`
`Case No. IPR2017-01994
`
`68. A POSITA would be motivated to combine Schaefer with Qureshi, for
`
`the reasons discussed in Section (VI)(A)(1)(a). Further, a POSITA would be
`
`motivated to combine Mazur with Schaefer and Qureshi, because the functional
`
`electronic modules of Schaefer, Qureshi, and Mazur are configured to work
`
`together.
`
`69. Mazur teaches a secondary power (e.g., battery) that supports a
`
`DRAM memory during a low power refresh mode (Mazur, 5:36-39). Schaefer
`
`establishes that a power failure situation would require a reset of the components in
`
`the memory device, stating that:
`
`Mode register 40 is typically a persistent register wherein once
`programmed, the mode register retains the program op-code
`until the mode register is reprogrammed or SDRAM 20 loses
`power.
`Schaefer, 4:4-7. As Qureshi’s memory controller is configure
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
