IEEE ELECTRON DEVICE LETTERS, VOL. 11, NO. 5, MAY 1990
`
`221
`
`A New LDDStructure: Total Overlap with
`Polysilicon Spacer (TOPS)
`
`J. E. MOON, T. GARFINKEL, J. CHUNG, M. WONG, P. K. KO, ann CHENMINGHU, FELLOW, IEEE
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`Abstract—This letter presents a new fully overlapped lightly doped
`drain structure—the total overlap with polysilicon spacer (TOPS)struc-
`ture. The TOPSstructure achieves full gate overlap of the lightly doped
`region with simple processing. TOPS devices have demonstrated superior
`performanceandreliability compared to oxide-spacerlightly doped drain
`(LDD) devices, with an order of magnitude advantage in current
`degradation under stress for the sameinitial current drive or 30% more
`drive for the same amount of degradation. TOPS devices also show a
`much smaller sensitivity to n~ dose variation than LDD devices, Gate-
`induced drain leakage (GIDL) is reported for the first time in fully
`overlapped LDD devices.
`
`I. INTRODUCTION
`
`HE long-term reliability of n-channel MOSFET’s has
`been a major concern as device channel lengths have been
`reduced to submicrometer and deep-submicrometer dimen-
`sions[1], [2]. The lightly doped drain (LDD)structure [3] has
`been widely investigated as a means of reducing the lateral
`electric field and the associated hot-carrier effects on reliabil-
`ity. Theoretical and experimental investigations [4]-[6] have
`demonstrated that gate control over the n~ region is a crucial
`element
`in both the performance and reliability of LDD
`devices. This letter presents a new fully overlapped lightly
`doped drain structure—the total overlap with polysilicon
`spacer (TOPS) structure. Unlike other proposed fully over-
`lapped structures which require complicated fabrication se-
`quences or unusual fabrication techniques [5]-[7], the TOPS
`structure achieves full overlap with simple and proven
`processing techniques.
`II. Device PROCESSING
`
`Fig. 1 showsthe critical steps in the fabrication sequence.
`Gate oxide is grown after LOCOSisolation, and then layers of
`thin polysilicon, very thin LPCVD oxide, and thick doped
`polysilicon are deposited. Wafers were cleaned in piranha
`(H,SO,/H20;) after thin polysilicon deposition, followed by
`removal of chemical oxide in dilute HF;
`the thin oxide
`deposition was followed directly by thick polysilicon deposi-
`tion. Gate definition (using the thin LPCVD oxide as an etch
`stop) is followed by n- implantation through the thin oxide
`and thin polysilicon layers, and removal of the thin oxide in
`
`Manuscript received November 14, 1989; revised January 25, 1990. This
`work was supported in part by JSEP under Contract F49620-87-C-0041 and
`by ISTO/SDIO through ONR under Contract N00014-85-K-0603. J. E. Moon
`was supported by a Doctoral Award from Eastman Kodak Company.
`The authors are with the Department of Electrical Engineering and
`Computer Sciences, University of California, Berkeley, CA 94720.
`IEEE Log Number 9035748.
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`TOPSstructure layered gate and polysilicon spacer formation. Gate
`Fig. 1.
`and spacer definitions are accomplished by plasma etching with oxide
`endpoint detection. Typical CVD film thicknesses are shown.
`
`dilute buffered HF. Doped polysilicon is then deposited and
`etched to form the polysilicon spacer. The last etch proceeds
`until a well-defined endpoint corresponding to gate oxide and
`field oxide is detected. Both polysilicon etches are very easily
`controlled and do not require the extremely high selectivity or
`timed etching of previously reported structures [5], [6]. The
`oxide-spacer LDD devices were prepared by n~ implantation
`after gate definition, followed by LPCVD oxide deposition,
`densification, and etch-back to form the oxide spacer [8].
`Control over formation of the TOPS polysilicon spacer is
`mucheasier than that of the LDD oxide spacer because of the
`easily detected endpoint; the oxide spacer etch mustbe timed.
`Source/drain n+ implantation, contact formation, and metalli-
`zation follow a standard process sequence. Althoughit was not
`done in this initial study, silicidization of gate, source, and
`drain could be done by additional process steps after the
`polysilicon spacer formation.
`All devices had a gate oxide of 15 nm and were fabricated
`using the deep-submicrometer optical lithographic technique
`reported earlier [9]. All spacer lengths were designed to be 0.2
`pm. TOPS devices received n~ doses of 0.5, 1.0, and 3.0 x
`1013 cm~?, and the oxide-spacer LDD devices received doses
`of 0.5 and 1.5 x 10) cm-?. Two types of TOPS devices,
`having either in-situ doped or undoped thin polysilicon, were
`
`0741-3106/90/0500-0221$01.00 © 1990 IEEE
`
`TSMC 1322
`TSMC 1322
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`

`

`222
`
`IEEE ELECTRON DEVICE LETTERS, VOL. 11, NO. 5, MAY 1990
`
`TABLEI
`EFFECT OF n> DOSE VARIATION ON PERFORMANCEOF TOPS AND LDD
`DEVICES
`Tis Values measured at V, = 5 Vi &msa Values measured at V,=3V.
`*
`
`
`Structure
`Dose (cm)
`|
`Performance _
`
`i
`Tasat (mA/um)
`_
`Snsat (mS/mm)
`
`0.5 x 10°
`0.4500.36
`118/103
`
`1.0x 10
`0.46/0.36
`120/104
`TOPS
`
`_
`3.0 x 0
`0.48/0,38
`122/104
`
`Lop
`05x 0
`0.36/0.32
`.
`90/84
`1.5 x 10
`0.43/0.36
`110/98
`* Dual entries are for L,.,=0.5 jum and L0.8 pm,
`eee
`
`
`
`
`Tox=15nm
`O LDD-1E13
`* LOD-SE12
`
`© TOPS-3E13
`© TOPS-1E13
`v TOPS-1£13
`Undeped This Pay
`4 TOPS-SE12
`Undeped This Paty
`
`(T=1200sec)
`did/Id(%)
`
`
`mized with respect to n~ dose and spacer length in thisinitial
`feasibility study.
`For a given Ley the TOPS device has significantly less
`substrate current than the non-LDD device. Peak Toup (at Va =
`5 Vand V, ~ 2V; W = 10 um, Ley = 0.8 pm) was 81, 16,
`and 8 nA for non-LDD, TOPS, and LDD devices, respec-
`tively. Although TOPS devices have more J/,,,, than oxide
`spacer LDD devices, they exhibit significantly less hot-carrier
`degradation. After 20 min ofstressing at peak J,,,5 and Vp = 6
`V, a TOPS device with Leg = 0.8 um shows a forward linear
`current degradation of 1.0% compared to 4.4 and 34% for the
`LDD and non-LDD devices, respectively. Creation of inter-
`face traps by hot carriers and subsequentelectron trappingis
`offset in the TOPS device by the overlapped gate, whereas in
`the LDD device only fringing fields are available to exert
`control over the resistive n~ region. A definitive comparison
`of performance and reliability among the three device struc-
`tures is shown in Fig. 2. The superiority of the TOPS devices
`compared to the LDD and non-LDD devicesin this study is
`clearly demonstrated, with roughly an order of magnitude
`advantage in degradation for the same drive or 30% more
`drive for the same amount of degradation. Fig. 2 also shows
`the effect of n~ dose variations for the levels studied. The
`TOPSstructure again appears to be less sensitive to n- dose
`variability.
`The doping of the thin polysilicon layer (as deposited) had
`no demonstrable effect on the current drive orreliability of the
`TOPS devices. One plausible explanation for the lack of a
`noticeable effect of thin polysilicon doping on both perform-
`ance and reliability is that the undoped thin polysilicon may
`have been subsequently doped by diffusion from the top gate
`and spacerpolysilicon. The thermal cycle after gate definition
`and source/drain implant was carefully controlled in order to
`limit junction drive-in (a total of 30 min at 925°C), butit is
`possible that dopant diffusion occurred rapidly along polysili-
`con grain boundaries.
`The gate-induced drain leakage (GIDL) [11] behavior of
`non-LDD, oxide-spacer LDD, and TOPS devices are com-
`pared in Fig. 3. Besides hot-carrier degradation, GIDL is
`considered to be another major factor in limiting the power-
`supply voltage for deep-submicrometer MOStechnologies [2].
`The non-LDD MOSFEThasthe largest GIDL, as expected
`[11]. Of the remaining two devices, the oxide-spacer LDD is
`GIDL-free while the TOPS device still shows significant
`
`80
`
`120
`110
`100
`90
`(mS/mm)
`Gysay
`Fig. 2. Overall performance comparison of TOPS, LDD, and non-LDD
`technologies. Degradation values are for forward linear operation and 2ysat
`values are measured at Vz = 3 V.
`
`130
`
`140
`
`madein order to investigate the possibility of modifying the
`gate work function through the doping of the bottom layer of
`the gate [10]. In-situ doped polysilicon was used in all TOPS
`devices for
`the thick top layer of the gate and for the
`polysilicon spacer.
`
`TI. PERFORMANCE AND RELIABILITY
`Performance and reliability characteristics of non-LDD,
`conventional oxide-spacer LDD, and TOPS n-MOSFET de-
`vices have been evaluated. Table I contains a comparison of
`TOPS and LDD device performance for Le of 0.5 and 0.8 pm.
`The TOPSstructure, due to the fully overlapped gate, shows
`better current drive and larger transconductance than an LDD
`structure of comparable channel length. Theg,, characteristics
`of the TOPS devices approach those of non-LDD’s
`in
`magnitude. At Vz = 3 V the peak gm of non-LDD, TOPS,and
`oxide spacer LDD devices were 109, 104, and 98 mS/mm,
`Tespectively, for an Ler of 0.8 um. The drive advantage of
`TOPS devices over LDD devices was seen to increase with
`decreasing channel
`length, with as much as 20% more at
`Lee = 0.3 wm (0.62 versus 0.52 mA/um). Importantly, the
`TOPS devices show a much smaller sensitivity to n- dose
`variation than the LDD devices do over the range of doses
`evaluated, as shownin Table I. It should be noted that device
`and process characteristics have not necessarily been opti-
`
`

`

`223
`
`{3]
`
`REFERENCES
`[1] C. Hu ef al., ‘‘Hot-electron induced MOSFET degradation—Model,
`monitor, and improvement,’’ JEEE Trans. Electron Devices, vol,
`ED-32, no. 2, p. 375, 1985.
`for deep-submicrometer
`(2] M.-C.
`Jeng ef ai.,
`“‘Design guidelines
`MOSFET’s,”’ in JEDM Tech. Dig., 1988, p. 386.
`S. Ogura, P. J. Tsang, W. W. Walker, D. L. Critchlow, and J. F.
`Shepard, ‘‘Design and characteristics of the lightly doped drain-source
`(LDD) insulated gate field-effect transistor,’” JEEE Trans. Electron
`Devices, vol. ED-27, no. 8, p. 1359, 1980.
`[4] K. Mayaram, J. C. Lee, and C. Hu, ‘‘A modelfor the electric field in
`lightly doped drain structures,’’ JEEE Trans, Electron Devices, vol.
`ED-34, no. 7, p. 1509, 1987.
`[5] T.-Y. Huang ef ai, “A new LDD transistor with inverse-T gate
`structure,’’ JEEE Electron Device Lett., vol. EDL-8, no. 4, p. 151,
`1987.
`{6] R. Izawa, T. Kure, S. lijima, and E. Takeda, ‘‘The impact of gate-
`drain overlapped LDD (GOLD)
`for deep submicron VLSI's,”* in
`IEDM Tech, Dig., 1987, p. 38.
`‘‘A new submicron
`{7] T. Hori, K. Kurimoto, T. Yabu, and G. Fuse,
`MOSFETwith LATID(large-tilt-angle implanted drain) structure,”* in
`Dig. Tech. Papers Symp. VLSI Technol., 1988, p. 15.
`S. Ogura, P. J. Tsang, W. W. Walker, D. L. Critchlow, and J. F.
`Shepard, ‘‘Elimination of hot electron gate current by the lightly doped
`drain-source structure,’’ in JEDM Tech. Dig., 1981, p. 651.
`J. Chungef a/., ‘‘Deep-submicrometer MOSdevice fabrication using a
`photoresist-ashing technique,’” IEEE Electron Device Leit., vol. 9,
`no. 4, p. 186, 1988.
`J. R. Pfiester and L. C. Parrillo, ‘‘A novel p~!/p* poly gate CMOS
`VLSI Technology,’’ JEEE Trans. Electron Devices, vol. 35, no. 8, p.
`1305, 1988.
`T. Y. Chan, J. Chen, P. K. Ko, and C. Hu, **The impact of gate-
`induced drain leakage current on MOSFETscaling,”’ in JEDM Tech.
`Dig., 1987, p. 718.
`
`[8]
`
`[9]
`
`{10}
`
`1d)
`
`-24
`
`- 1.6
`
`0.0
`- 0.8
`(Vv)
`Gate Voltage
`Fig. 3. GIDL behavior of TOPS, LDD, and non-LDD devices. Implanted
`n- doses are 3 x 10" and 1.5 x 10! cm~? for the TOPS and LDD
`devices, respectively.
`
`—_
`0.8
`
`GIDL. Because the gate would overlap the n* region in any
`fully overlapped LDD device such as TOPS, we expect GIDL
`to be an important design consideration for fully overlapped
`LDDstructures.
`
`IV. Conclusions
`
`A new fully overlapped LDD structure—TOPS—has been
`fabricated and characterized. TOPS devices produce more
`current drive and better transconductance than oxide-spacer
`LDD devices of equivalent size. A major advantage of TOPS
`over LDDis its improved reliability. Even though the TOPS
`devices had greater /,,, than LDD devices, current degrada-
`tion under hot-electron stressing conditions is significantly less
`for the TOPS devices. The choice of n~ doseis less critical for
`the TOPSstructure than for the LDD structure in the results
`
`MOONef al.: TOTAL OVERLAP WITH POLYSILICON SPACER
`
`n-channel MOSFET’s
`
`reported here, implying less overall process sensitivity. GIDL
`
`¢ =15nmOx
`was noted in the TOPS devices, the first such report of this
`
`
`behavior in fully overlapped LDD devices. This represents an
`WAL6 = 10/5 pm
`important design constraint for submicrometer devices. The
`1E-06FYp 25 V
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`superior performance and reliability characteristics of the
`
`TOPSstructure merit further investigation for deep-submicro-
`meter applications.
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