United States Patent 9
`5,472,890
`(11] Patent Number:
`Oda
`[45] Date of Patent:
`Dec. 5, 1995
`
`
`AMAT ACAATTO
`
`US005472890A
`
`[54] METHOD FOR FABRICATING AN
`
`oeneronGATE FIELD EEFECI
`Inventor: Noriaki Oda, Tokyo, Japan
`
`[75]
`
`[73] Assignee: NEC Corporation, Tokyo, Japan
`
`[21] Appl. No.: 427,816
`
`Apr. 26, 1995
`Filed:
`[22]
`Foreign Application Priority Data
`[30]
`Apr. 28, 1994
`[JP]
`Japan wn.sessssessssecsssessseecneessseees 5-090882
`[SU]
`Unite CLS acsecsnscsnennesnsnenee Hoi27336
`[52] US. CU. ceceeeeceeeseecssecrneerees 437/41; 437/44; 437/235;
`437/236; 748/DIG. 113
`[58] Field of Search oo.cccccecon 437/44, 235, 236,
`437/41 SW, 41 RLD; 748/DIG. 113; 257/336,
`408. 759
`,
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`6/1988 Parmillo et al. sssevsrsesnsnseee 437/44
`4,753,898
`.. 257/373
`9/1988 Horiuchi et al. .......
`4,769,686
`
`vee 156/643
`...
`4,776,922 10/1988 Bhattacharyya et al.
`
`4,838,991
`6/1989 COLE cecccccsrensnsesseceees
`.. 156/643
`5/1990 Shimbo «0...eesecceecoseseeceessateestenses 257/58
`4,924,279
`
`
`1/1992 Fazan etal. ....
`ww. 361/313
`5,081,559
`
`..............
`we 437/195
`5,166,096 11/1992 Cote et al.
`6/1994 Gelatos et al. oo... 437/236
`5,324,690
`
`FOREIGN PATENT DOCUMENTS
`
`9/1992 Buropean Pat. Off. we 257/759
`502614A2
`62-147776
`7/1987
`Japan.
`2270335 U1990 Japan.
`OTHER PUBLICATIONS
`
`Pfiester, J. R., “LDD MOSFET’s Using Disposable Sidewali
`Spacer Technology”, IEEE Elec. Dev. Lett., vol. 9, No. 4,
`Apr. 1988, pp. 189-192.
`“Copper Multilevel Interconnections”, IBM Tech. Disc.
`Bull., vol. 33, No. 11, Apr. 1991, pp. 299-300.
`Primary Examiner—T. N. Quach
`“407™e Agent, or Firm—Young & Thompson
`[57]
`ABSTRACT
`.
`.
`.
`;
`.
` 4LDD MOS transistor havinga small fringe capacitance is
`fabricated by the steps of forming, lightly-doped source and
`drain regions by introducing impurities into a semiconductor
`substrate by using gate electrode as a mask, forming a pair
`of sidewall spacers above side surfacesof the gate electrode,
`forming heavily doped source and drain regions by an ion
`implantation method using the pair of sidewall spacers as a
`mask, removingthe pair of sidewall spacers, and forming a
`Pair of new sidewall spacers having a dielectric constant
`lowerthan that ofsilicon oxide abovethe side surface of the
`gate electrode, including the use of polyimide or boron
`nitride as the spacer material.
`
`10 Claims, 4 Drawing Sheets
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`TMSC 1305
`TMSC 1305
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`

`

`U.S. Patent
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`Dec. 5, 1995
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`Sheet 1 of 4
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`5,472,890
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`Dec. 5, 1995
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`US. Patent
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`Dec. 5, 1995
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`Sheet 3 of 4
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`Dec. 5, 1995
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`Sheet 4 of 4
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`PRIOR ART
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`PRIOR ART
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`

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`5,472,890
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`1
`METHOD FOR FABRICATING AN
`INSULATING GATE FIELD EFFECT
`TRANSISTOR
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to a method for fabricating
`an insulating gate field effect transistor such as an MOS
`transistor suppressing the so-called short channeleffect.
`2. Description of the Related Art
`As one of means for improving the performance of an
`MOStransistor, it is well known to make the channel length
`thereof short. In accordance with shortening in channel
`length, however, the electric field applied near the drain
`region of the transistor becomes stronger because of an
`abrupt
`impurity profile thereof.
`In order to reduce the
`electric field, therefor, such an MOStransistor that has a
`lightly doped drain (LDD)structure have been proposed and
`put into practical use.
`Referring to FIGS. 3(a) to 3(c), such an LDDtransistoris
`fabricated as follows:
`
`First, a field oxide film 202 and a gate oxide film 203 are
`formed by the thermal oxidation of an element isolation
`region and an element formation region, respectively, of a
`P-type silicon substrate 201 having an impurity concentra-
`tion of about 10> cm”?. After implantation of boron ionsfor
`threshold voltage adjustment under conditions of,
`for
`example, 35 keV and 4x10’? cm”, a 300 nm-thick poly-
`crystalline silicon film is formed over the entire surface by
`the chemical vapor deposition (CVD) method and then
`diffused with phosphorus impurities, followed by patterning
`to form a gate electrode 204. Phosphorusions are implanted
`at, for example, 20 keV and 7x10** cmin a self-alignment
`manner with the gate electrode 204 and the field oxide film
`202 to form N-type lightly-doped layers 205a and 205b
`having an impurity concentration of about 10'8 cm. A
`silicon oxide film 206 with thickness of about 150 nm is then
`formed allover the surface by the CVD method (FIG.3(a)).
`Next, as shownin FIG.3(5),the silicon oxide film 206 is
`etched back by the anisotropic reactive ion etching (RIE)
`method to jeave and thus form silicon sidewall spacers 206a
`on the both side of the gate electrode 204. Arsenic ions are
`implanted at, for example, 70 keV and 3x10? cm™in a
`self-alignment manner with the silicon oxide spacers 206a,
`the gate electrode 204 andthefield oxide film 202 to thereby
`form highly-doped N*-type diffused layers 207a and 207b
`having an impurity concentration of about 1x10'? cm? In
`this way, a source region 208 consisting of the N~-type
`diffused layer 205a and the N--type diffused layer 207a, and
`a drain region 209 consisting of the N-type diffused layer
`2055 and the N-type diffused layer 207b, are formed.
`Followingthat, as shown in FIG. 3(c), a silicon oxide film
`210 with thickness of about 100 nm is formed on the entire
`surface by the CVD method. Then, a BPSG film with
`thickness of about 700 nm is formedon the entire surface by
`a atmospheric pressure chemical vapor deposition (APCVD)
`which uses tetraethoxysilane (Si(OC,H,),; TEOS) gas,
`ozone (O3) gas,
`trimethylphosphate (PO(OCH,),; TMP)
`gas, and trimethylborate (B(OCH3)3,; TMB) gas as source
`gases and further a spin-on-glass (SOG)film (not shown)is
`formed on the entire surface. Thesilicon oxidefilm is etched
`back until the SOG film is removed completely to thereby
`form a BPSG film 211 having a flat top surface. Contact
`openings which reach respectively the source region 208 and
`the drain region 209 are formed by RIE by sequential
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`etching of the BPSG film 211 andthesilicon oxidefilm 210.
`A titanium film 212 with thickness of about 60 nm and a
`titanium nitride film 213 with thickness of about 100 nm are
`formed on the entire surface by sputtering and reactive
`sputtering, respectively. Further, the surface is blanketed
`with a tungsten film having a thickness of about 500 nm, and
`the tungsten film is etched back leaving a tungsten film 214
`within the contact openings. Then, an aluminum film 215
`with thickness of, for example, about 500 nm is formed by
`sputtering and then patterned to form metallic wirings each
`composed of the aluminum film 215, the titanium nitride
`film 213 and the titanium film 212. Next, an inter-layer
`insulating film 216 is formed on the entire surface. Thus, the
`LDD MOStransistor is derived.
`
`Although the LDD MOStransistor presents an improved
`performance, in order to further enhance the device perfor-
`mance, the reductionin the parasitic or stray capacity of the
`MOStransistor itself becomes also important. The MOS
`transistor inherently has the stray capacitances between the
`gate and channel and between the gate and source/drain, In
`the LDDstructure, however, each of the gate length (L) and
`the gate width (W) is reduced and further the lightly-doped
`regions 205 is suppressed to extend laterally. Therefore, the
`overlap capacitance between the gate electrode and the
`channel region is decreased.
`However, the decrease in the overlap capacitance causes
`in tum the rate of the so-called fringe capacitance to
`increase. The fringe capacitance is formed between the gate
`electrode and the source/drain region due to the fringe
`electric fields between the sides of the gate electrode and the
`source/drain region. That is, the fringe capacitance becomes
`in turn one of major factors influencing the operating speed
`of the transistor.
`
`For example, in the transistor shown in FIG.3, the fringe
`capacity between the gate electrode and the drain region is
`about 1.24 fF, for L=0.5 pm and W=10 um. When this
`transistor is employed to constitute a CMOS inverter
`together with a P-channel transistor with L=0.5 pm and
`W=15 um, the delay time of the inverter becomes the order
`of 100 ps.
`In order to reduce thefringe capacitance, therefore, it may
`be considered that the inter-Jayer insulating film 211 is
`replaced with a polyimide film having a low dielectric
`constant. In this case, however, the polyimide layer gener-
`ates an organic gas upon sputting the metal film 212, so that
`many voids in the metal layer.
`It may be further considered that the silicon oxide side
`spacer 206 is replaced with a low dielectric film such as
`polyimide. In that case, a polyimide film is deposited over
`the entire surface in place of the oxide film 206 and then
`etched back to form a polyimide side spacer, followed by
`forming the regions 207a and 207b. However, the polyimide
`space hardly operates as a mask for selective ion-implanta-
`tion, so that undesirably large highly-doped regions are
`formed. Moreover, it is not easy to control the width of the
`polyimide spacer.
`
`SUMMARYOF THE INVENTION
`
`Therefore, an object of this invention is to provide an
`improved method for fabricating an MOStransistor having
`a low fringe capacitance.
`It is another object of the present invention to provide a
`methodfor fabricating an MOStransistor with lowered stray
`or parasitic capacitance in both overlapping and fringe
`capacitances.
`
`

`

`5,472,890
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The above-mentioned and other objects, features, and
`advantagesof this invention will become more apparent by
`reference to the following detailed description of the inven-
`tion taken in conjunction with the accompanying drawings,
`wherein:
`
`FIG. 1(a) to FIG. 1(/) are the cross sectional views
`illustrative of respective steps of a method accordingtofirst
`embodimentof the invention;
`FIG.2 is a sectional view illustrate of a MODtransistor
`fabricated by a method according to second embodiment of
`the invention; and
`FIG. 3(a) to FIG. 3(c) are the sectional viewsillustrative
`of respective steps of a method accordingto the priorart.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`3
`A method of fabricating a transistor according to this
`invention is characterized in that side spacers used as a mask
`for forming highly-doped regions by ion-implantation is
`removedandthereafter a low dielectric insulation layer such
`as polyimide or boron nitride is deposited over the entire
`surface and then etched back to form new side spacers made
`of the low dielectric layer.
`the highly-doped
`With the above-featured method,
`regions are formed in a desired pattem and the fringe
`capacitance is lowered by the new side spacers.
`
`4
`the function of relaxing the stress of the silicon nitride film
`136 at the part covering the gate electrode 104.
`Following that, arsenic ions are implantation at, for
`example, 70 keV and 3x10'° cmin a self-alignment
`mannerwith the silicon oxide spacers 106, the silicon oxide
`film 126 and the silicon nitride film 136, the gate electrode
`104, and the field oxide film 102 to thereby form highly-
`doped N*-type layers 107a and 107b having an impurity
`concentration of about 1x10'® cm’°.In this way, the N-type
`diffused layer 105a and the N*-type diffused layer 107a
`constitutes a source region, and the N-type diffused layer
`105b and the N*-type diffused layer 107b constitutes a drain
`Tegion.
`the silicon oxide spacers 106 are selectively
`Next,
`removed by an isotropic etching using, for example, buff-
`ered hydrofluoric acid. In this case, the silicon nitride film
`136 functions also as an etching stopper. Therefore, no
`damages are applied to the gate oxide film 103. Following
`that, a polyimide film 146 having a thickness of about 200
`nm is formed on the entire surface by a spin coating thenit
`is heated at 400° C. for 30 min. (FIG. 1(c)) .
`Next, the polyimide film 146is etched back by an oxygen
`plasma to form the polyimide sidewall spacers 146a.At this
`time,the silicon nitride film 136 serves as an etching stopper.
`Although the maximum width of the polyimide sidewall
`spacer which covers over the source region 108 andthe drain
`region 109 depends on the controllability of this etching,it
`is possible to restrict its width within the range of 200+50
`nm (FIG. 1(d)) .
`Next, a second silicon nitride film 190 with thickness of
`Referring now to FIG.1, in the first step as shown FIG.
`about 10 nm is formed by PECVDusing monosilane (SiH,)
`1(a) of a method according to the first embodimentof this
`gas and ammonia (NH) gas asa source gasat a temperature
`invention, a P-type silicon substrate is first selectively oxi-
`below 500° C.to protect the highly hygroscopic polyimide
`dized by the so-called LOCOSprocessto formafield oxide
`35
`film 102. This film 102 is formed on an elementisolation
`spacers 146a. Subsequently, a BPSGfilm with thickness of
`about 700 nm is formed on the entire surface at a tempera-
`region of the substrate 101 surrounding an element forma-
`ture below 500° C. by the APCVD using, for example,
`tion regions thereof. The substrate has an impiurity concen-
`tration of about 10’* cm”>. The elementformation regionis
`TEOSgas, ozone gas, TMP gas, and TMBgasasthe source
`gases, and further an SOGfilm (not shown) is formed on the
`then thermal-oxidized to form a gate oxide film 103. The
`entire surface. The SOG and BPSGfilms are then etched
`implantation of boron ions is carried out for threshold
`back until the SOG film is removed completely, so that a
`voltage adjustment underthe conditions of, for example, 35
`keV and 4x10’? cm. A 300 nm-thick polycrystalline
`BPSG film 110A with flat top surface is formed as an
`inter-layer insulating film (FIG. 1(e)).
`silicon film is then formed over the entire surface by the
`CVD method and diffused with phosphorus impurities,
`Next, contact openings reaching the respective parts of
`followed by patterning to form a gate electrode 104. Then,
`the source region 108 and the drain region 109 are formed
`lightly doped layers 105a and 105b having an impurity
`by RIE by sequentially etching the insulating layer 110A,the
`concentration of about 10'® cm™ are formed by an phos-
`silicon nitride film 136, the silicon oxide film 126, and the
`phorus implantation at, for example, 20 keV and 7x10%?
`gate oxide film 103. Then, a titanium film 112 with thickness
`cm” ina self-alignment manner with the gate electrode 104
`of about 60 nm and a titanium nitride film 113 with thickness
`and the field oxide film 102. A silicon oxide film 126 with
`of about 100 nm are formed on the entire surface by a
`thickness of about 10 nm anda silicon nitride film 136 with
`sputtering and a reactive sputtering, respectively. Further, a
`thickness of about 10 nm are then formed sequentially on the
`tungsten is deposited on the entire surface to form a blanket
`entire surface by the low pressure chemical vapor deposition
`tungsten film with thickness of about 500 nm. This blanket
`(LPCVD). These films have an excellent step coverage and
`tungsten film is then etched back to thereby form tungsten
`give only a slight damageto the silicon substrate 101.
`plugs 114filling the respective the contact openings. Then,
`for example, an aluminum film, an aluminum alloy layer
`Next, a silicon oxide film (not shown) with thickness of
`such as Al—Si, Al—Si—Cu, Al—Georthelike, or a copper
`about 150 nm is formed onthe entire surface by the LPCVD
`film with thickness of about 500 nm is formed by a sput-
`or the plasma-enhanced CVD (PECVD). Next, as shown in
`tering and then patterned to form metallic wirings each
`FIG. 1(5),silicon oxide sidewall spacers 106 asfirst spacers
`composed of the aluminum film 115, the titanium nitride
`are formed on the both side faces of the gate electrode by
`film 113, and the titanium film 112. Next, as inter-layer film
`etching backthesilicon oxide film by the RIE at the pressure
`116 is further formed on the entire surface FIG. 1(/). Thus,
`of 7 Pa and the RF power of 600 W using 50 sccm
`the LDDtransistor is derived.
`trifluoromethane (CHF,) gas and 150 sccm carbon monox-
`ide (CO)gas.In this etching back,the selectivity ratio for the
`etchingof the silicon oxide film to the silicon nitride film is
`high (about 5), so that the silicon nitride film 136 functions
`as an etching stopper. Further, the silicon oxide film 126 has
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`A significant difference of the first embodiment from the
`conventional LDDtransistor is the presence of the polyim-
`ide sidewall spacers 146a in place of the silicon oxide
`sidewall spacers. Becauseofthis, in a caseofthe field-effect
`
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`5,472,890
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`6
`disclosed embodiments, as well as other embodimentsofthe
`invention, will become apparent to personsskilled in the art
`upon reference to the description of the invention. It is
`therefore contemplated that the described claims will cover
`any modifications of embodiments as fall within the true
`scope of the invention.
`Whatis claimedis:
`1. A method forfabricating a field effect transistor com-
`prising the steps of:
`forming a gate insulating film on a semiconductor sub-
`strate;
`
`5
`transistors of L=0.5 ym and W=10 pm, by formed by the
`method mentioned above the fluctuations in the transistor
`characteristics themselves are made small even when the
`maximum fluctuation width of the polyimide spacers is
`taken into consideration. The fringe capacity between the
`gate electrode and the drain region is smaller about 15% than
`that of the conventional LDD transistor as shown in FIG.
`3(c). Whenthis transistor is employed to constitute a CMOS
`inverter together with a P-channel transistor with L=0.5 um
`and W=15 pm,the delay time of the inverter is reduced by
`about 10% compared with the conventional LDDtransistor.
`Turning to FIG. 2, there is shown an LDD transistor
`according to the second embodiment of this invention in
`which the same constituents as those shown in FIG. 1 are
`denoted by the same reference numerals to omit the further
`description thereof. In this embodiment, boron nitride spac-
`ers 156 are employed in place of the polyimide sidewall
`spacers 146 as shown in FIG.1. Further an undoped silicon
`oxide film 110B is employed in place of the BPSG film.
`The formation of the boron nitride spacers 156 is done in
`the following way. Up to the steps of the formation of the
`N’-type higher doped layers 107a and 107b and the removal
`ofthe first sidewall spacers composedofa silicon oxidefilm,
`this embodiment follows the same method as in thefirst
`embodiment. Then, a boron nitride film with thickness of
`about 200 nm is formed by the PECVD using diboron
`(B.H,) gas and ammonia gas as the source gases. Subse-
`quently, boron nitride spacers 156 with width of about 200
`nm are formed by etching back the boronnitride film by an
`RIE using boron trichloride (BCI,) gas as the etching gas.
`Note that the embodiment does not have the siliconnitride
`film 190 as shown in FIG.1.
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`forming a gate electrode onsaid gate insulating film, said
`gate electrode having a top surface and a pair of side
`surfaces;
`forming lightly-doped source and drain regions in said
`semiconductor substrate by introducing impurities into
`said semiconductor substrate by using said gate elec-
`trode as a mask;
`covering said gate electrode with a first insulating film,
`said first insulating film thereby having a first portion
`on said top surface of said gate electrode and second
`and third portions respectively on said pair of side
`surfaces of said gate electrode,
`forming first and second sidewall spacers respectively on
`said second and third portions of said first insulating
`film;
`forming heavily-doped source and drain regions into said
`semiconductor substrate by introducing impurities into
`said semiconductor substrate by using said first and
`second sidewall spacers, said first insulating film and
`said gate electrode as a mask;
`subjecting said first and second sidewall spacers to an
`etchant to removesaidfirst and second sidewall spac-
`ers, said first insulating film protecting said gate insu-
`lating film against said etchant; and
`forming third and fourth sidewall spacers respectively on
`said second and third portions of said first insulating
`film, each of said third and fourth sidewall spacers
`having a dielectric constant lower than that of a silicon
`oxide film.
`2. The method as claimed in claim 1, wherein each of said
`third and fourth sidewall spacers is made of polyimide.
`3. The method as claimed in claim 2, further comprising
`a step of forming a second insulating film on said third and
`fourth sidewall spacers to protect said third and fourth
`sidewall spacers.
`4. The method as claimed in claim 3, wherein said second
`insulating film is a silicon nitride film.
`5. The methodas claimed in claim 1, wherein each of said
`third and fourth sidewall spacers is made of boronnitride.
`6. The methodas claimed in claim 5, further comprising
`a step for an inter-layer insulating film to coversaid third and
`fourth sidewall spacers and said first insulating film, said
`the first
`As described in the above, in this invention,
`inter-layer insulating film being an undopedsilicon oxide
`spacers consisting of the silicon oxide film are used as the
`film.
`mask of ion implantation to form the source and the drain
`7. A method for fabricating a field effect transistor com-
`regions and removed after the implantation, and the second
`prising the steps of:
`spacers consisting of an insulating material havingarelative
`60
`dielectric sonstant smaller than that of silicon oxide are
`forming a gate insulating film on a semiconductor sub-
`strate;
`formed over the side faces of the gate electrode. Because of
`this,
`there are obtained field effect
`transistors with no
`fluctuations in the transistor characteristics, and has a small
`fringe capacity as a result of adoption of this invention.
`Although the invention has been described with reference
`to specific embodiments, this description is not meant to be
`construed in a limiting sense. Various modifications of the
`
`The reason for constructing the insulating film layer 110B
`by an undopedsilicon oxide film, is to avoid an increase in
`the relative dielectric constant (3.4) of the boron nitride
`spacers 156 due to diffusion of the phosphorus impurity
`from the BPSG film into the boron nitride spacers 156.
`In a case of L=0.5 pm and W=10 um,the fringe capacity
`between the gate electrode and the drain region is smaller
`about 10% than that of the conventional LDD transistor.
`When this transistor is employed to construct a CMOS
`inverter together with a P-channel transistor with L=0.5 um
`and W=15 um,the delay time is reduced by about 7%. In
`comparison to the case of the first embodiment, both the
`degree of reductionin the fringe capacity and the degree of
`reduction in t, of the CMOSinverter are smaller. However,
`the adoption of this embodiment has another effect in that
`the nonuniformity in the fringe capacity becomes extremely
`small due to the fact that the width of the boron nitride
`spacers 156 can be formed with a high precise dimensions.
`Analogous to the case of the first embodiment,
`this
`embodiment can also be applied to a P-channel field-effect
`transistor.
`
`65
`
`forming a gate electrode on said gate insulating film, said
`gate electrode having a top surface and a pair of side
`surfaces;
`forming lightly-doped source and drain regions by intro-
`ducing impurities into said semiconductor substrate by
`using said gate electrode as a mask;
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`covering said gate electrode with a first insulating film,
`gate electrode having a top surface and a pair of side
`said first insulating film thereby having a first portion
`surfaces;
`on said top surface of said gate electrode and second
`forming lightly-doped source and drain regions by intro-
`and third portions respectively on said pair of side
`ducing impurities into said semiconductor substrate by
`surfaces of said gate electrode, said first insulating film
`using gate electrode as a mask;
`including a first silicon oxide film andafirst silicon
`covering said gate electrode with a first insulating film,
`nitride film formed onsaid first silicon oxide film;
`said first insulating film thereby havingafirst portion
`forming first and second silicon oxide sidwall spacers
`on said top surface of said gate electrode and second
`respectively on said second andthird portions of said
`and third portions respectively on said pair of side
`first insulating film;
`surfacesof said gate electrode, said first insulating film
`forming heavily-doped source and drain regions by intro-
`including a first silicon oxide film andafirst silicon
`ducing impurities into said semiconductor substrate by
`nitride film formed on said first silicon oxide film;
`using said first and secondsilicon oxide sidewall spac-
`forming first and second silicon oxide sidewall spacers
`ers, said first insulating film and said gate electrode as
`respectively on said second and third portions of said
`a mask;
`first insulating film;
`removing said first and second sidewall spacers while
`forming heavily-doped source and drain regions by intro-
`protecting said first silicon oxide film in said first
`ducing impurities into said semiconductor substrate by
`insulating film and said gate insulating film by said first
`using said first and second silicon oxide sidewall spac-
`silicon nitride film in said first insulating film;
`ers, said first insulating film and said gate electrode as
`forming first and second polyimide sidewall spacers on
`a mask;
`,
`said second and third portions of said first insulating
`removing said first and second sidewall spacers while
`film;
`protecting said first silicon oxide film in said first
`covering said first and second polyimide sidewall spacers
`insulating film and said gate insulating film bysaid first
`with a secondsilicon nitride film;
`silicon nitrode film in said first insulating film;
`forming an inter-layer insulating layer on said second
`formingfirst and second boron nitride sidewall spacers on
`silicon nitride film.
`said second and third portions of said first insulating
`8. The method as claimed in claim 7, wherein said
`film; and
`inter-layer insulating layer is a boron-phosphor silicate
`forming an inter-layer insulating layer on said first and
`glass.
`second boron nitride sidewall spacers and said first
`9. A method for fabricating a field effect transistor com-
`insulating film.
`prising thesteps of:
`10. The method as claimed in claim 9, said inter-layer
`forming a gate insulating film on a semiconductor sub-
`insulating film is an undopedsilicon oxide.
`strate;
`*
`F
`* *
`forming a gate electrode onsaid gate insulating layer, said
`
`20
`
`25
`
`30
`
`