Case 2:17-cv-00100-JRG-RSP Document6 Filed 02/01/17 Page 1of9PagelD#: 74
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE EASTERN DISTRICT OF TEXAS
`MARSHALLDIVISION
`
`GODOKAISHA IP BRIDGE1,
`
`Case No. 2:17-cv-00100
`
`JURY TRIAL DEMANDED
`
`
`
`
`
`
`Plaintiff,
`
`Ve
`
`XILINX,INC.,
`
`Defendant.
`
`PLAINTIFF’S FIRST AMENDED COMPLAINT FOR PATENT INFRINGEMENT
`
`Plaintiff Godo Kaisha IP Bridge1 (“Plaintiff’ or “IP Bridge”) files this First Amended
`
`Complaint for Patent Infringement (“Complaint”) against Defendant Xilinx, Inc. (“Defendant”or
`
`“Xilinx”). Plaintiff alleges as follows:
`
`NATURE OF THE ACTION
`
`L
`
`This is an action for infringement of U.S. Patent No. 7,893,501 (the “’501
`
`patent”), and U.S. Patent No. 7,265,450 (the “’450 Patent’).
`
`2.
`
`IP Bridge is a Japanese corporation havinga principal address of c/o Sakura Sogo
`
`Jimusho, 1-11 Kanda Jimbocho, Chiyoda-ku, Tokyo 101-0051 Japan.
`
`3.
`
`Xilinx, Inc. is a Delaware corporation with its principal place of business located
`
`at 2100 Logic Drive, San Jose, California 95154. Xilinx maintains a substantial presence in this
`
`State through its regional sales office located at 5801 Tennyson Parkway, Suite 460, Plano,
`
`Texas 75024. Xilinx can be servedvia its registered agent for service of process, CT Corporation
`
`System, 1999 Bryan Street, Suite 900, Dallas, Texas 75201. Upon information andbelief, Xilinx
`
`is registered with the Texas Secretary of State to conduct business in Texas and has been since at
`
`PLAINTIFF’S FIRST AMENDED COMPLAINT FOR PATENT INFRINGEMENT- Page 1
`
`TSMC v. Godo Kaisha IP Bridge 1
`IPR2017-01844
`TSMC 1335
`
`

`

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`least June 8, 1990. Xilinx conducts business operations within the Eastern District of Texas
`
`throughits facilities in Plano, Texas.
`
`JURISDICTION AND VENUE
`
`4.
`
`This action arises under the Patent Laws of the United States, 35 U.S.C. § 1, et
`
`seq., including 35 U.S.C. §§ 271, 281, 283, 284, and 285. This is a patent infringement lawsuit,
`
`over which this Court has subject matter jurisdiction under 28 U.S.C. §§ 1331 and 1338(a).
`
`5.
`
`This Court has general and specific personaljurisdiction over Defendant because
`
`it is present in and transacts and conducts business in and with residents of this District and the
`
`State of Texas. IP Bridge’s causes ofactionarise, at least in part, from Defendant’s contacts with
`
`andactivities in this State and this District. In addition, upon information and belief, Defendant
`
`has committed acts of infringement within this District and this State by, inter alia, making,
`
`selling, offering for sale, importing, and/or using productsthat infringe one or more claimsofthe
`
`patents-in-suit. Defendant, directly and/or through intermediaries, uses, sells, ships, distributes,
`
`offers for sale, and/or advertises or otherwise promotes products in this State and this District.
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`Defendant regularly conducts andsolicits business in, engages in other persistent courses of
`
`conductin, and/or derives substantial revenue from goods andservices provided to residents of
`
`this State and this judicial District.
`
`6.
`
`Uponinformation and belief, Defendant has purposefully and voluntarily placed
`
`one or more infringing products into the stream of commerce with the expectation that they will
`
`be purchased and/or used byresidents of this District and/or incorporated into downstream
`
`products purchased by consumersin this District, including by directly or indirectly working
`
`with subsidiaries, distributors, and other entities located within this District and this State .
`
`PLAINTIFF’S FIRST AMENDED COMPLAINT FOR PATENT INFRINGEMENT- Page 2
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`

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`Vi
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`Defendant maintains highly interactive and commercial websites, accessible to
`
`residents of Texas and this judicial District, through which Defendant promotesits products and
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`services, including products that infringe the patents-in-suit.
`
`8.
`
`Venueis properin this District under 28 U.S.C. §§ 1391 and 1400(b)for at least
`
`the reasonsset forth above.
`
`COUNT ONE: INFRINGEMENTOFU.S. PATENT NO.7,893,501
`
`9.
`
`IP Bridge adopts andrestates the allegations in paragraphs 1-8 asif fully set forth
`
`herein.
`
`10.
`
`On February 22, 2011, the United States Patent and Trademark Office issued the
`
`’501 Patent, “Semiconductor Device Including MISFET HavingInternal Stress Film” A true and
`
`correct copy of the ’501 Patent is attached hereto as Exhibit A.
`
`11.
`
`By assignment, Plaintiff owns theentire right, title, and interest in and to the ’501
`
`patent, including the right to sue and recover damages, including damagesfor past infringement.
`
`12.
`
`Defendant has had knowledgeof the *501 patent no later than September21,
`
`2016—the date on which the parties met and Plaintiff IP Bridge provided specific notice that
`
`Defendant waspracticing the °501 patent.
`
`The °501 patent is valid and enforceable.
`
`Defendant hasat no time, either expressly or impliedly, been licensed underthe
`
`13.
`
`14.
`
`*501 patent.
`
`15.
`
`Uponinformation and belief, Defendant has been and nowis directly,literally
`
`under 35 U.S.C. § 271(a), and/or equivalently under the doctrine of equivalents, infringing the
`
`’501 patent by making,using, selling, offering for sale, and/or importing in or into the United
`
`States, without authority, products that fall within the scope of one or more claimsof the *501
`
`PLAINTIFEF’S FIRST AMENDED COMPLAINT FOR PATENT INFRINGEMENT- Page3
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`

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`patent including,but not limited to, the Kintex-7 28nm FPGAfamily of programmable
`
`integrated circuits, and devices that perform substantially the same function in substantially the
`
`same wayto achieve substantially the sameresult (the “FPGA devices”). Upon information and
`
`belief, all Xilinx devices employing Xilinx’s 28nm technology, including the FPGA devices
`
`noted above, infringe the °501 patent because each accused Xilinx product and device comprises
`
`a MISFETwith all additional elements recited in at least claims 1, 5-7, 10, 11, 15-19, 21, and 23-
`
`25 of the ’501 patent. In particular, each accused Xilinx product’s and device’s circuit includes
`
`an active region made of a semiconductor substrate, a gate-insulating film formed on the active
`
`region, a gate electrode formed on the gate-insulating film, source/drain regions formed in
`
`regionsofthe active region located on bothsides of the gate electrode, a silicon nitride film
`
`formed over from side surfaces of the gate electrode to upper surfaces of the source/drain regions
`
`wherein the silicon nitride film is not formed on an uppersurface of the gate electrode and the
`
`gate electrode protrudes upward from a surfacelevelofparts ofthe silicon nitride film located at
`
`both side surface of the gate electrode. As an example, Xilinx’s infringementofat least claim 1
`
`of the ’501 patent by the Kintex-7 28nm FPGAisillustrated in the charts attached hereto as
`
`Exhibit B.
`
`16.
`
`Since nolater than the date upon whichit first learned of the ’501 patent,
`
`Defendant has induced, and is continuing to actively and knowingly induce, with specific intent,
`
`infringementof the 501 patent by its customers under 35 U.S.C. § 271(b). Defendant further has
`
`contributed to the infringementof the ’501 patent under 35 U.S.C. § 271(c), by making, using,
`
`offering for sale, selling, and/or importing image sensors. Defendant encouragesandfacilitates
`
`infringing sales and uses of image sensors through the creation and dissemination of promotional
`
`and marketing materials, instructional materials, product manuals, and/or technical materials to
`
`PLAINTIFF’S FIRST AMENDED COMPLAINT FOR PATENT INFRINGEMENT- Page 4
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`

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`manufacturers and/ordistributors. Defendant contributesto infringement by others, including
`
`manufacturers, distributors, resellers, and end users, knowing that its FPGA devices constitute a
`
`material part of the inventions of the ’501 patent, knowing those FPGA devicesto be especially
`
`madeor adapted to infringe the ’501 patent, and knowing that those FPGA devices are not staple
`
`articles or commodities of commercesuitable for substantial non-infringing use. Defendant
`
`knew, or should have known,that its encouragement wouldresult in infringementofat least one
`
`claim of the *501 patent.
`
`17.
`
`Defendant has andis continuing to willfully infringe the ’501 patent by,at
`
`minimum, continuing to engagein infringingactivities after Plaintiff notified Defendant of
`
`Defendant’s infringement. For that reason, Defendanthas acted despite an objectively high
`
`likelihood that its actions constituted infringementofa valid patent and such objective risk of
`
`infringement was known to Defendant or so obvious that Defendant should have knownit.
`
`COUNT TWO: INFRINGEMENT OF U.S. PATENT NO.7,265,450
`
`18.
`
`19.
`
`IP Bridgerestates the allegations in paragraphs 1-8 asif fully set forth herein.
`
`On September4, 2007, the United States Patent and Trademark Office issued the
`
`’450 Patent, “Semiconductor Device and Method for Fabricating the Same.” A true and correct
`
`copy of the ’450 Patent is attached hereto as Exhibit C.
`
`20.
`
`Byassignment, Plaintiff ownstheentire right, title, and interest in andto the ’450
`
`Patent, including the right to sue and recover damages, including damages for past infringement.
`
`21.
`
`Defendant has had knowledgeof the ’450 patent no later than September 21,
`
`2016—the date on which the parties met and Plaintiff IP Bridge provided specific notice that
`
`Defendant waspracticing the °450 patent.
`
`D2)
`
`The ’450 Patent is valid and enforceable.
`
`PLAINTIFF’S FIRST AMENDED COMPLAINT FOR PATENT INFRINGEMENT- Page 5
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`

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`Case 2:17-cv-00100-JRG-RSP Document6 Filed 02/01/17 Page 6 of 9 PagelD #: 79
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`23.
`
`Defendanthasat no time, either expressly or impliedly, been licensed under the
`
`’450 patent.
`
`24.—Upon information and belief, Defendant has been and nowis directly, literally
`
`under 35 U.S.C. § 271(a), and/or equivalently under the doctrine of equivalents, infringing the
`
`°450 patent by making,using,selling, offering for sale, and/or importing in or into the United
`
`States, without authority, products that fall within the scope of one or more claimsof the *450
`
`patent including, but not limited to, the Kintex-7 28nm FPGA and Virtex-6 40nm FPGAdevice
`
`families of programmable semiconductors and devices that perform substantially the same
`
`function in substantially the same way to achieve substantially the same result (the “FPGA
`
`device families”). Upon information andbelief, all Xilinx devices employing Xilinx’s 28nm
`
`technology andall devices employing the 40nm technology, including the FPGA devices noted
`
`above, infringe the °450 patent because each accused Xilinx product and deviceis a
`
`semiconductor comprising a substrate, a first interlayer dielectric film provided on the substrate,
`
`a first interconnect provided within thefirst interconnect groove with convex or concave portions
`
`at least at one ofits side surfaces and bottom surface, a second interlayerdielectric film provided
`
`over thefirst interlayer dielectric film and the first interconnect, andafirst plug that passes
`
`through the secondinterlayer dielectric film and comesinto contact with a partofthe first
`
`interconnect and any andall additional elementsrecited in at least claims 1, 2, 3, 8, 10, 11, 13
`
`and 14 of the ’450 patent. As an example, Xilinx’s infringementofat least claim 1 of the °450
`
`patent by the Kintex-7 28nm FPGAisillustrated in the charts attached hereto as Exhibit D.
`
`25.
`
`Since nolater than the date upon whichit first learned of the ’450 patent,
`
`Defendant has induced,andis continuing to actively and knowingly induce, with specific intent,
`
`infringementof the ’450 patent by its customers under 35 U.S.C. § 271(b). Defendant further has
`
`PLAINTIFF’S FIRST AMENDED COMPLAINT FOR PATENT INFRINGEMENT-— Page 6
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`

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`Case 2:17-cv-00100-JRG-RSP Document6 Filed 02/01/17 Page 7 of 9 PagelD #: 80
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`contributed to the infringementof the ’450 patent under 35 U.S.C. § 271(c), by making,using,
`
`offering for sale, selling, and/or importing image sensors. Defendant encourages andfacilitates
`
`infringing sales and uses of image sensors through the creation and dissemination of promotional
`
`and marketing materials, instructional materials, product manuals, and/or technical materials to
`
`manufacturers and/or distributors. Defendant contributes to infringement by others, including
`
`manufacturers, distributors, resellers, and end users, knowing that its FPGA device families
`
`constitute a material part of the inventions of the ’450 patent, knowing those FPGA device
`
`families to be especially made or adapted to infringe the ’450 patent, and knowingthat those
`
`FPGAdevice families are not staple articles or commodities of commerce suitable for substantial
`
`non-infringing use. Defendant knew,or should have known,that its encouragement wouldresult
`
`in infringementof at least one claim of the ’450 patent.
`
`26.
`
`Defendanthasandis continuing to willfully infringe the ’450 patentby,at
`
`minimum,continuing to engagein infringing activities after Plaintiff notified Defendant of
`
`Defendant’s infringement. For that reason, Defendant has acted despite an objectively high
`
`likelihoodthat its actions constituted infringementofa valid patent and such objective risk of
`
`infringement was known to Defendant or so obvious that Defendant should have knownit.
`
`PLAINTIFF’S FIRST AMENDED COMPLAINT FOR PATENT INFRINGEMENT- Page 7
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`

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`PRAYER FOR RELIEF
`
`Plaintiff prays for the followingrelief:
`
`A.
`
`A judgmentthat Xilinx has infringed and continuesto infringe the ’501 and ’450
`
`patents;
`
`B.
`
`A judgmentand order requiring the Xilinx to pay IP Bridge damages under 35
`
`U.S.C. § 284, including treble damages for willful infringement as provided by 35 U.S.C. § 284,
`
`and supplemental damages for any continuing post-verdict infringementup until entry of the
`
`final judgment with an accounting as needed;
`
`i.
`
`A judgmentandorder requiring Xilinx to pay IP Bridge pre-judgment and
`
`post-judgmentinterest on the damages awarded;
`
`D.
`A judgmentandorderfindingthis to be an exceptional case and requiring Xilinx
`to pay the costs ofthis action (includingall disbursements) and attorneys’ fees as provided by 35
`
`U.S.C. § 285;
`
`E.
`
`A permanentinjunction against Xilinx’s direct infringement, active inducements
`
`of infringement, and/or contributory infringement of the ’501 and ’450 patents, as well as against
`
`each of Xilinx’s agents, employees, representatives, successors, and assigns, and those acting in
`
`privity or in concert with Xilinx;
`
`F.
`
`G.
`
`In the eventa final injunction is not awarded, a compulsory on-going royalty; and
`
`Such other and furtherrelief as the Court deems just and equitable.
`
`PLAINTIFF’S FIRST AMENDED COMPLAINT FOR PATENT INFRINGEMENT- Page 8
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`

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`Case 2:17-cv-00100-JRG-RSP Document6 Filed 02/01/17 Page 9 of 9 PagelD #: 82
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`DATED: February 1, 2017
`
`/s/ Michael W. Shore
`Michael W. Shore, Texas Bar No. 18294915
`Lead Attorney
`mshore@shorechan.com
`Alfonso Garcia Chan, Texas Bar No. 24012408
`achan@shorechan.com
`Jennifer M. Rynell, Texas Bar No. 24033025
`jrynell@shorechan.com
`Christopher L. Evans, Texas Bar No.24058901
`cevans@shorechan.com
`Russell DePalma, Texas Bar No.00795318
`redepalma@shorechan.com
`Ari Rafilson, Texas Bar No. 24060465
`arafilson@shorechan.com
`Andrew M. Howard, Texas Bar No. 24059973
`ahoward@shorechan.com
`
`SHORE CHAN DePUMPO LLP
`901 Main Street, Suite 3300
`Dallas, Texas 75202
`Telephone: 214-593-9110
`Facsimile: 214-593-9111
`
`Hiromasa Ohashi*
`ohashi@ohashiandhorn.com
`Jeff J. Horn Jr., Texas Bar No. 24027234
`horn@ohashiandhorn.com
`Cody A. Kachel, Texas Bar No. 24049526
`ckachel@ohashiandhorn.com
`OHASHI & HORN LLP
`325 North Saint Paul Street, Suite 4400
`Dallas, Texas 75201
`Telephone: 214-743-4170
`Facsimile: 214-743-4179
`Attorneys for Plaintiff Godo Kaisha IP Bridge 1
`
`*Motion for pro hac vice admissionto befiled
`
`PLAINTIFF’S FIRST AMENDED COMPLAINT FOR PATENT INFRINGEMENT- Page 9
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`

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`EXHIBIT A
`
`

`

`Case 2:17-cv-00100-JRG-RSP DocumentqT 84
`
`US007893501B2
`
`az, United States Patent
`Tsutsuiet al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,893,501 B2
`*Feb. 22, 2011
`
`(54) SEMICONDUCTOR DEVICE INCLUDING
`MISFET HAVING INTERNAL STRESS FILM
`
`(56)
`
`References Cited
`US. PATENT DOCUMENTS
`
`5,023,676 A
`
`6/1991 Tatsuta
`
`(75)
`
`Inventors: Masafumi Tsutsui, Osaka (JP);
`Hiroyuki Umimoto, Hyogo (JP); Kaori
`Akamatsu, Osaka (JP)
`
`(73) Assignee: Panasonic Corporation, Osaka (JP)
`
`(*) Notice:
`
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`This patent is subject to a terminal dis-
`claimer.
`
`(21) Appl. No.: 12/170,191
`
`(22) Filed:
`
`Jul. 9, 2008
`
`(65)
`
`Prior Publication Data
`
`US 2009/0050981 Al
`
`Feb. 26, 2009
`
`Related U.S. Application Data
`
`(63) Continuation of application No. 11/730,988,filed on
`Apr. 5, 2007, now Pat. No. 7,417,289, whichis a con-
`tinuation of application No. 10/859,219, filed on Jun.
`3, 2004, now Pat. No. 7,205,615.
`
`(Continued)
`FOREIGN PATENT DOCUMENTS
`
`JP
`
`52-120776
`
`10/1977
`
`(Continued)
`OTHER PUBLICATIONS
`
`Shimizu, A., et al., “Local Mechanical-Stress Comtrol (LMC): A
`New Technique for CMOS_Performance Enhancement”, 2001,
`TEDM 01, p. 19.4.1-19.4.4.
`
`(Continued)
`
`Primary Examiner—Howard Weiss
`(74) Attorney, Agent, or Firm—McDermott Will & Emery
`LLP
`
`(57)
`
`ABSTRACT
`
`A semiconductor device includesa first-type internal stress
`Foreign Application Priority Data
`(30)
`film formed ofa silicon oxide film over source/drain regions
`ofan nMISFETandasecond-typeinternal stress film formed
`Jun. 16,2003
`(IP)
`aeeeceeecesceeeseeeeeen 2003-170335
`ofa TEOSfilm over source/drain regions ofa pMISFET.Ina
`channelregion ofthe nMISFET,a tensile stress is generated
`in the direction ofmovementofelectrons dueto the first-type
`internal stress film, so that the mobility of electrons is
`increased.Ina channel region ofthe pMISFET,a compressive
`stress is generated in the direction ofmovement ofholes due
`to the second-type internal stressfilm, so that the mobility of
`holes is increased.
`
`(51)
`
`Int. Cl.
`(2006.01)
`HOLL 29/76
`(2006.01)
`HOIL 29/494
`(2006.01)
`HOIL 31/062
`(2006.01)
`HOI 31/113
`(2006.01)
`HOIL 31/119
`(52) US. Cd.
`ooccccecccssessessseuesncnnesenees ce, 257/369
`(58) Field of Classification Search.................. 257/369
`See application file for complete search history.
`
`25 Claims, 9 Drawing Sheets
`
`
`
`

`

`Case 2:17-cv-00100-JRG-RSP Document 6-1 Filed 02/01/17 Page 3 of 21 PagelD#: 85
`
`US 7,893,501 B2
`Page 2
`
`
`
`U.S. PATENT DOCUMENTS
`
`6,437,404 B1*
`6,573,172 Bl
`6,870,230 B2*
`6,977,194 B2
`6,982,465 B2
`7,022,561 B2
`7,205,615 B2*
`7,417,289 B2*
`2003/0040158 Al
`2004/0075148 Al
`
`8/2002
`6/2003
`3/2005
`12/2005
`1/2006
`4/2006
`4/2007
`8/2008
`2/2003
`4/2004
`
`Xiang etal. occ 257/347
`En etal.
`Matsuda et al. voce 257/365
`Belyansky etal.
`Kumagai et al.
`Huang etal.
`Tsutsui et al. ooccccceeees 257/369
`Tsutsui et ab... 257/369
`Saitoh
`
`Kumagai et al.
`
`9/2005 Chan etal.
`2005/0194596 Af
`FOREIGN PATENT DOCUMENTS
`60-236209
`11/1985
`01-042840 A
`2/1989
`2003-086708
`3/2003
`2004-193166
`7/2004
`OTHER PUBLICATIONS
`
`JP
`JP
`JP
`JP
`
`Japanese Office Action, with English translation,issued in Japanese
`Patent Application No. 2003-170335, mailed Dec. 22, 2009.
`Japanese Office Action, with English translation, issued in Japanese
`Patent Application No. 2003-170335, mailed Mar. 23, 2010.
`* cited by examiner
`
`

`

`Case 2:17-cv-00100-JRG-RSP Document 6-1 Filed 02/01/17 Page 4 of 21 PagelD #: 86
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`U.S. Patent
`
`Feb. 22, 2011
`
`Sheet1 of 9
`
`US 7,893,501 B2
`
`FIG. 1
`
`Rn
`Rp
`o—A/T
`
`
`10
`
` | tate:
`TOMER
`
`
`2 3ajx | 5 4a 2
`3b ty
`5 4b 2
`
`8a
`
`

`

`Case 2:17-cv-00100-JRG-RSP Document 6-1 Filed 02/01/17 Page 5 of 21 PagelD #: 87
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`U.S. Patent
`
`US 7,893,501 B2
`
`Feb. 22, 2011
`
`Sheet2 of 9
`
`Sn
`
`FIG. 2A
`
`ee
`
`

`

`Case 2:17-cv-00100-JRG-RSP Document 6-1 Filed 02/01/17 Page 6 of 21 PagelD #: 88
`
`U.S. Patent
`
`US 7,893,501 B2
`
`Feb. 22, 2011
`
`Sheet3 of 9
`
`FIG. 3A
`
`te
`
`

`

`Case 2:17-cv-00100-JRG-RSP Document 6-1 Filed 02/01/17 Page 7 of 21 PagelD #: 89
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`U.S. Patent
`
`Feb. 22, 2011
`
`Sheet4 of 9
`
`US 7,893,501 B2
`
`Rp
`Rn
`FIG. 4A
`ao_o
`
`8a
`
`
`Naltat
`
`A ANU
`RECL
`
`
`
`2 3aix | 5 4a 2 Sbiy |) 5 4b 2
`FIG. 4B
`11 i to
`
`
`NealNaan
`
`IRsiiuiMionill
`
`Sa
`
`

`

`Case 2:17-cv-00100-JRG-RSP Document 6-1 Filed 02/01/17 Page 8 of 21 PagelD #: 90
`
`U.S. Patent
`
`Feb. 22, 2011
`
`Sheet 5 of 9
`
`US 7,893,501 B2
`
`FIG. dA
`
`Rn
`rs
`
`Rp
`A
`
`12-4 ea TRS erates Ara ace aaris rs age es
`
`8a
`
`
`
`
`
`—PKE CH
`se
`
`NAILS
`A
`
`
`
`a
`
`=
`
`IRSNCTA ENT
`
`
`2 3aix | 5 4a 2 Sbiy |
`
`

`

`Case 2:17-cv-00100-JRG-RSP Document 6-1 Filed 02/01/17 Page 9 of 21 PagelD#: 91
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`U.S. Patent
`
`Feb. 22, 2011
`
`Sheet6 of 9
`
`US 7,893,501 B2
`
`Rp
`Rn
`FIG. 6A
`—_—
`
` fh
`
`

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`Case 2:17-cv-00100-JRG-RSP Document 6-1 Filed 02/01/17 Page 10 of 21 PagelD #: 92
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`U.S. Patent
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`Feb. 22, 2011
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`Sheet 7 of 9
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`US 7,893,501 B2
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`Case 2:17-cv-00100-JRG-RSP Document 6-1 Filed 02/01/17 Page 11 of 21 PagelD #: 93
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`U.S. Patent
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`Feb. 22, 2011
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`Sheet8 of 9
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`US 7,893,501 B2
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`FIG. 8A
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`6-1 Filed 02/01/17 Page 12 of 21 PagelD #: 94
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`U.S. Patent
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`Feb. 22, 2011
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`Sheet9 of 9
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`US 7,893,501 B2
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`OHS NWs
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`Case 2:17-cv-00100-JRG-RSP Document 6-1 Filed 02/01/17 Page 13 of 21 PagelD #: 95
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`US 7,893,501 B2
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`1
`SEMICONDUCTOR DEVICE INCLUDING
`MISFET HAVING INTERNAL STRESS FILM
`
`RELATED APPLICATIONS
`
`This application is a Continuation of U‘S. application Ser.
`No. 11/730,988,filed Apr. 5, 2007, now U.S. Pat. No. 7,417,
`289, which is a Continuation of U.S. application Ser. No.
`10/859,219,filed Jun. 3, 2004, now USS.Pat. No. 7,205,615,
`and claiming priority of Japanese Application No. 2003-
`170335, filed Jun. 16, 2003, the entire contents of each of
`which are hereby incorporated by reference.
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to a semiconductor device
`including an MISFETand a methodfor fabricating the same,
`and moreparticularly relates to a measure for increasing the
`mobility of carriers.
`Whena stressis generated in a semiconductorcrystal layer,
`a crystal-lattice constant varies and a bandstructure is
`changed, so that the mobility of carriers is changed. This
`phenomenonhas been knownas the “piezo resistivity effect”.
`Whetherthe carrier mobility is increased or reduced differs
`depending on the planedirection of a substrate, the direction
`in which carriers move, and whether the stress is a tensile
`stress or a compressivestress. For example, in an Si (100)
`substrate, i.e., a silicon substrate of which the principal sur-
`face is the {100} plane, assumethat carriers move inthe [011]
`direction. When carriers are electrons, with a tensile stress
`generated in the direction in which electrons in a channel
`region move, the mobility ofthe carriers is increased. On the
`other hand, whencarriersare holes, with a compressive stress
`generated in the direction in which holes in a channel region
`move, the mobility of the carriers is increased. The increase
`rate of carrier mobility is proportional to the size ofa stress.
`In this connection, conventionally, there have been propos-
`als for increasing carrier mobility by applying a stress lo a
`semiconductorcrystal layerto increase the operation speed of
`transistors and the like. For example,in Reference1, an entire
`semiconductor substrate is bent using an external device,
`thereby generatinga stress in an active region ofa transistor.
`
`15
`
`7)S
`
`2
`Theinternalstress film is capable of covering one or both
`of source/drain regions. In an nMISFET,the internal stress
`film generates a tensile stress substantially in the parallel
`direction to a gate length direction in a channel region (i.c.,
`the direction of movementofelectrons). In a pMISFET, the
`internal stress film generates a compressive stress substan-
`tially in the parallel direction to a gate length direction in a
`channelregion(i.e., the direction of movementof holes).
`Coveringboth side surfaces or both side and uppersurfaces
`of a gate electrode, the internal stress film can generate a
`stress in the longitudinal dircction of the channel region
`through the gate electrode, thereby increasing the mobility of
`carriers.
`Moreover, covering a side surfaceofthe gate electrode and
`an upper surface of the semiconductor substrate in two
`regions of the substrate sandwiching part of the gate elec-
`trode, whether the MISFETis an nMISFETor a pMISFET,
`the internal stress film can generate a tensile stress substan-
`tially in the parallel direction to the gate width direction ofthe
`MISFET,therebyincreasing the mobility of carriers.
`A first method for fabricating a semiconductor device
`according to the present invention is a method in which an
`nMISFET and a pMISFET are formedin first and second
`active regions ofa semiconductorsubstrate, respectively, and
`thenfirst and secondinternalstress films which cover source/
`drain regions ofthe nMISFETand source/drain regions ofthe
`pMISFET,respectively, and generate a tensile stress and a
`compressive stress, respectively, substantially in the parallel
`directions to respective gate length directions of the channel
`regions are formed.
`Accordingto this method, a CMOSdevice of which the
`operation speed is increased can be obtained.
`A second method for fabricating a semiconductor device
`according to the present invention is a method in which an
`internalstress film is formedfirst, a groove is formed in the
`internal stress film, a gate insulating film and a buried gate
`electrode are formedin the groove, and thenthe internalstress
`film is removed.
`
`According to this method, a stress which increases the
`mobility of carriers in the channel region can be generated
`using a remainingstress in the gate insulating film.
`
`SUMMARY OF THE INVENTION
`
`45
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`in the above-described known structure, an
`However,
`external device is needed in addition to a semiconductor
`substrate and a stress can be generated only in the same
`direction in an entire region ofthe semiconductorsubstrate in
`whichactive regions ofa transistor and the like are provided
`and which is located in the principal surface side. For
`example, when an Si (100) substrate is used, neither the
`mobility of electrons nor the mobility of holes can be
`increased.
`It is therefore an object ofthe present inventionto provide,
`by generating a stress which increases the mobility ofcarriers
`in a semiconductor layer without using an external device, a
`semiconductor device including a pMISFET and an nMIS-
`FET ofwhichrespective operation speeds are increased and a
`methodfor fabricating the same.
`A semiconductor device according to the present invention
`includes an internalstressfilm for generatinga stress in a gate
`length direction in a channel region of an active region in
`which a MISFETis formed.
`
`Thus, the mobility of carriers in the MISFET can be
`increased by using the piezo resistivity effect.
`
`FIG.1 is a cross-sectional view illustrating a semiconduc-
`tor device according to a first embodiment of the present
`invention.
`
`FIG. 2A through 2C are cross-sectional viewsillustrating
`first halfofrespective steps for fabricating the semiconductor
`device ofthe first embodiment.
`
`35
`
`FIG. 3A through 3C are cross-sectional viewsillustrating
`latter halfofrespective steps for fabricating the semiconduc-
`tor device ofthe first embodiment.
`FIGS.4A through 4C are cross-sectional viewsillustrating
`first, second and third modified examples ofthe first embodi-
`ment.
`
`FIGS. SA through 5D are cross-sectional viewsillustrating
`respective steps for fabricating a semiconductor device
`according to the first modified example ofthe first embodi-
`ment.
`
`65
`
`FIGS. 6A through 6C are cross-sectional viewsillustrating
`respective steps for fabricating a semiconductor device
`according to the third modified exampleof the first embodi-
`ment.
`
`

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`US 7,893,501 B2
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`3
`FIGS.7A through 7D are cross-sectionalviewsillustrating
`Girst half of respective steps for fabricating a semiconductor
`device according to a second embodiment of the present
`invention.
`FIGS.8A through 8Dare cross-sectional viewsillustrating
`latter half of respective steps for fabricating the semiconduc-
`tor device of the second embodiment.
`FIGS. 9A and 9B are a plane view of an MISFET of a
`semiconductor device accordingto a third embodimentofthe
`present invention and a cross-sectional view illustrating a
`cross-sectional structure taken along the line IX-IX (a cross
`section in the gate width direction), respectively.
`
`DESCRIPTION OF THE PREFERRED-
`EMBODIMENTS
`
`First Embodiment
`
`4
`film interposed therebetween,a stress is generated in the film
`itself. As for stress, there are tensile stress and compressive
`stress. In this embodiment and other embodiments,an inter-
`nal stress film in which a tensile stress is generated substan-
`tially in the parallel directionto the directionin which carriers
`move(i.e., the gate length direction) in a channel region ofan
`MISFETisreferred to asa “first-type internalstress film” and
`an internal stress film in which a compressivestress is gen-
`erated substantially in the parallel direction to the direction in
`which carriers move (the gate length direction) in a channel
`region ofan MISFETisreferredto as a “second-type internal
`stress film”.
`Herein, the semiconductor substrate 1 is an Si substrate of
`whichthe principal surface is the {100} plane andis referred
`to as an Si (100) substrate for convenience. However, the
`{100} planeis a general namefor the (+100) plane, the (0210)
`plane andthe (00+1) plane, and therefore, even a plane which
`is not exactly the {100} plane andistilted from the {100}
`plane by a less angle than 10 degree is considered to be
`FIG.1 is a cross-sectional view illustrating a semiconduc-
`substantially the {100} plane. Moreover,in this embodiment,
`tor device according to a first embodiment of the present
`the direction in which electrons move in the nMISFET and
`invention. As shownin FIG.1, a surface region of a semicon-
`the direction in which holes movein the pMISFET(i.e., the
`ductorsubstrate 1, i.e., an Si (100) substrate is divided into a
`gate length direction ofeach MISFET) is the [011] direction.
`plurality ofactive regions 1a and 14 by an isolation region 2.
`The semiconductor device includes an nMISFET formation
`However, in this embodiment, the “[011] direction on the
`principalsurface ofan Si (100) substrate”includes equivalent
`region Rn whichincludesthe active region 1¢ and in which an
`directionsto the [011] direction, such as the [01-1] direction,
`nMISFETis to be formed and a pMISFET formation region
`the [0-11] direction, and the [0-1-1] direction, i.e., directions
`Rp which includesthe active region 18 and in which a pMIS-
`FETis to be formed.
`within the range of the <011> direction. That is, even a
`direction which is not exactly the [011] direction andtilted
`The nMISFETincludes n-type source/druin regions 3a and
`30
`from the <011> direction by a less angle than 10 degree is
`4a each of which includes an n-type lightly doped impurity
`region, an n-type heavily doped impurity region andasilicide
`considered to be substantially the [011] direction.
`Accordingto this embodiment, the followingeffects can be
`layer such as a CoSi,layer, a gate insulating film 5 formed on
`obtained.
`the active region 1a and madeofasilicon oxide film,a silicon
`In the nMISFET,whenthefirst-type internal stress film 8a
`oxynitride film or the like, a gate electrode 6a formed on the
`gate insulating film 5 and madeofpolysilicon, aluminum or
`is brought into a direct contact with a semiconductorlayeror
`made to face a semiconductorlayer with a thin film interposed
`the like, and a sidewall 7 covering a side surface of the gate
`electrode 6a and made ofan insulatingfilm. Part ofthe active
`therebetween, a stress for compressingthefirst-type intemal
`stressfilm itself, i.e., a compressivestress is generated in the
`region la located under the gate electrode 6a is a channel
`region 1x in which electrons move(travel) when the nMIS-
`first-type internal stress film 8a. As a result, by the first-type
`internalstress film 8a, the semiconductorlayer adjacentto the
`FETis in an operationstate.
`first-type internalstress film 82 can be stretched in the vertical
`The pMISFETincludes p-type source/drain regions 36 and
`direction to a boundary surface. Specifically, the first-type
`4b each of which includes a p-type lightly doped impurity
`internal stress film 8a applies a compressive stress to the
`region, a p-type heavily doped impurity r