PROCEEDINGS OF THE SYMPOSIUM ON
`
`SILICON NITRIDE AND SILICON
`, g DIOXIDE THIN INSULATING FILMS
`
`Editors
`
`M. Jamal Deen
`Simon Fraser University
`Burnaby, BC, Canada
`
`William D. Brown
`
`University of Arkansas
`Fayetteville, Arkansas, USA
`
`Kalpathy B. Sundaram
`University of Central Florida
`Orlando, Florida, USA
`
`Stanley 1. Raider
`IBM T. J. Watson Research Center
`Yorktown Heights, New York, USA
`
`DIELECTRIC SCIENCE AND TECHNOLOGYAND ELECTRONICS DIVISIONS
`
`Proceedings Volume 97-10
`
`
`
`THE ELECTROCHEMICAL SOCIETY, INC.,
`10 South Main St., Pennington, NJ 08534-2896
`
`TSMC 1325
`
`TSMC 1325
`
`

`

`Copyright 1997 by The Electrochemical Society, Inc.
`All rights reserved.
`
`This book has been registered with Copyright Clearance Center, Inc.
`For further information, please contact the Copyright Clearance Center,
`Salem, Massachusetts.
`
`Published by:
`
`The Electrochemical Society, Inc.
`10 South Main Street
`
`Pennington, New Jersey 08534-2896, USA
`
`Telephone (609) 737-1902
`Fax (609) 737-2743
`e-mail: ecs@electrochem.org
`Web site: http://www.electrochem.org
`
`ISBN 1-56677-137-4 '
`
`Printed in the United States of America
`
`

`

`This material may be protected by Copyright law (Title 17 U.S. Code)
`
`

`

`shorter channel lengths.ll Hydrogen contamination also induces some problems, such as
`the electrical passivation of the dopants of silicon and shifting VT of MOSFETs, due to
`hot-electron trappings in the gate oxide.12 The electron heating effects in silicon nitride
`and silicon oxy-nitride films were studied by DiMaria and Abernathey.7 According to
`them, the average electron energy as a function of electric field is very similar to that of
`SiOz, and the total number of electrons which can be heated to energies greater than 2 eV
`is greatly reduced owing to the increased trap centers in the nitride films compared with
`$0; The reduction of hot electrons die to increased trapping is correlated to increasing
`N2 content through the oxy-nitride phase of $0; The traps keep the carriers near the
`bottom of the condUCtion band. This makes silicon nitride and oxy-nitride very attractive
`for gate dielectrics in the case of short and narrow channels that are adversely affected by
`hot carrier generation due to high electric fields. Hence in order to eliminate the
`hydrogen contamination in the films,
`in this present work, sputter deposited silicon
`nitride and oxy-nitride films were used as the gate insulators. The fabrication process of
`n-channel metal-insulator field effect transistors is discussed and device characteristics
`are studied.
`
`EXPERIMENTAL
`
`Two types of mask patterns, as shown in Fig. 1., were used for the fabrication of
`metal insulator field effect transistors. The minimum feature size was 5pm. The mask
`contained patterns of gate lengths of 5, 10, and 20 pm. The process steps involved in the
`fabrication of the devices are shown in Fig. 2. The substrates were p~Si with resistivity 8
`Q-cm of (100) orientation. The wafers were cleaned with boiling in tricholroethane,
`acetone, methanol, deionized water (DI) and then dipped in boiling 1:1 H2804: H202 for
`3 minutes. Subsequently the wafers were etched with buffered oxide etch (BOE) (13
`NH4F: 2 HF) 9:1 diluted with water‘for 1 min. Finally, the wafers were washed with DI
`water and blown dry with nitrogen.
`'
`Field oxide of 450 nm was grown by a wet oxidation process. This thick oxide
`served as a mask for subsequent phosphorus diffusion. Waycoat HNR 120 negative
`photoresist (PR) was used for the first level clear field mask-1 to form the source and
`drain windows (Fig. 2a and 2b). Phosphorus diffusion was completed by 5 min.
`predeposition followed by 20 min. drive-in diffusions (Fig. 2c) The wafers were coated
`with Shipley 1400 positive PR. Clear field mask-2 was used to define SiN gate regions
`(Fig. 2d). Silicon nitride was sputter deposited in an r. f. sputtering system using a Si3N4
`powder pressed target of 99.95% purity (Angstrom Sciences) (Fig. 2e). The sputtering
`conditions are given in the Table 1. Oxygen was added during sputtering to deposit
`silicon oxynitride films. Using a negative photoresist and mask-3 the contact windows
`for source and drain windows were opened (Fig. 2f). Diluted buffered oxide etch (BOB)
`was used to etch silicon nitride and oxy-nitride films (Fig. 2g). Aluminum film was
`evaporated in a vacuum system (Fig. 2h). Using Shipley 1400 positive PR and clear field
`mask-4, metal patterning was completed (Fig. 2i). Finally, Al was etched using diluted
`
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`phosphoric acid at 60 °C and metal contacts were made to source, drain and gate regions
`Fig- 21')
`.
`The device measurements were initially made on unannealed wafers and later
`measurements were made on the annealed wafers. The post annealing was performed to
`anneal out the interface charges and traps in the dielectric. It was carried out in an argon
`ambient at 350 “C for one hour. The SiN film thickness was measured using an optical
`interferometer. The C-V measurements of the MIS capacitors were performed using the
`Hewlett Packard impedance analyzer (Model . HP 4192A LF). The MOS device
`characteristics were measured using Hewlett Packard semiconductor parametric analyzer
`(Model HP 4145B). The parameter analyzer was programmed to give the ID versus VDS
`and (1.3)“2 versus VGS curves
`
`RESULTS
`
`The thickness of the dielectric films ranged from 75-150 nm depending on the
`deposition conditions as described in the Table-I. The dielectric breakdown strength was
`the film was of the order of 2x105 V/cm. The measured dielectric constant ranged from
`4.0 - 5.94 for the films. Figures 3 and 4 show the typical ID versus VDS characteristics of
`10 and 20 um gate length devices. Owing to a minor misalignment during the
`fabrication process, the gate electrode overlapping the diffused region is slightly offset
`and hence the drain current was slightly smaller than the expected value. Figure 5 shows
`ID“2 versus VGS of a 20 um device. This device showed the lowest VT of nearly -0.57 V.
`Some devices showed more negative VT. A reduction in the V1- values was observed
`when the devices were annealed. Further, an increase in drain current was also observed
`for the annealed devices. A similar trend was observed by Hezel et al. for the post
`annealed nitride films deposited by chemical vapor deposited films.13 Figure 6 and 7
`show the typical ID versus VDS and ID”; versus V65 characteristics of 10 um gate silicon-
`oxynitride device respectively. The device showed a VT of nearly 0.22 V. The smaller
`devices had a smaller drain current compared with larger devices, as evident from the
`MISFET characteristics.
`
`Figure 8 shows the calculated VT versus gate dielectric thickness for various
`interface charge densities for silicon nitride. The doping concentration of the p-Si is
`assumed as in the experimental case. All the calculations were based on a dielectric
`constant of 5.94 which was the maximum value in the studies. It can be seen that the VT
`variation is high for higher interface charge density compared with lower charges. If
`speed is not the main criteria, then silicon nitride or silicon oxynitride may be used to
`reduce the threshold voltage of the devices.
`
`Electrochemical Proceedings Volume 97-10
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`

`CONCLUSIONS
`
`Sputter deposited silicon nitride and silicon nitride films were used as gate insulators
`for the fabrication of MISFET devices. The films were deposited by an R. F. magentron
`sputtering technique using silicon nitride target. Electrical measurements performed
`indicated low threshold voltages for the devices.
`
`REFERENCES
`
`T. Chikyow, S. M. Bedair, L. Tye, and N. A. El-Masry, Appl. Phystett. 65, 1030
`(1994)
`.
`K. Ohta, K. Yamada, K. Shimizu, and Y. Tarui, IEEE Trans. Electron Devices,
`ED—29, 368 (1982)
`W. Ting, J. Ahn, and D. L. Kwong, J. Appl. Phys, 70, 3934 (1991)
`L. Dori, M. Severi, M. Impronta, J. Y. C-Sun, and M. Arienzo, IEEE Trans.
`Electron Devices, ED-37, 177 (1990)
`'
`S. Nozaki and RV. Giridhar, IEEE Electron Device Lett. 7, 486 (1986)
`K. K. Young, C. Hu, and W. G. Oldham, IEEE Electron Device Lett. 9, 616 (1988)
`D. J. DiMaria and J. R. Abernathey, J. Appl. Phys. 60, 1727 (1986)
`A. G. Frangoul, K. B. Sundaram, and P. F. Wahid, J. Vac. Sci. & Tech., B-9, 181,
`(1991)
`Y. Miyahara, J. Appl. Phys, 71, 2309 (1992)
`S. Minami and Y. Kamigaki, IEEE Trans. Electron Devices, ED-38, 2519 (1991)
`C. Y. Chang, F. C. Tzeng and Y. W. Mao, IEEE Electron Device Lett. 6, 448,
`(1985)
`'
`F. C. Stedile, I. J. R. Baumvol, W. H. Schreiner, and F. L. Freire Jr., J. of Vac. Sci
`& Tech., A-10, 462 (1992)
`'
`R. Hezel, K. Blumenstock, and R. Schorner, J. of Electrochem. Soc., 131, 1679
`(1984)
`
`PE“
`
`53°F?!“
`
`10.
`11.
`
`12.
`
`13.
`
`TABLE-I RF Sputtering conditions for silicon nitride and oxy-nitride films
`
`100, 150, 200
`
`RF forward power (W)
`RF reflected power (W)
`Sputtering time (min)
`Chamber pressure (in Torr)
`Substrate temperature (°C) (after deposition)
`Gas flow ratio (szAr) SiN films
`Gas flow ratio (N21021Ar) SiNO films
`
`Target-substrate distance (cm)
`
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`
`
`Drain
`region
`
`‘Source region
`
`
`Drain
`Source contact
`re ion
`contact
`9
`
`region
`
`
`
`
`
`Source pad
`
`Drain pad
`
`Drain contact
`
`
`
`Gate contact Source contact
`\§
`
`
`Drain pad
`
`Gate area
`
`Source pad
`
`source edge
`
`Drain edge
`
`
`
`
`V
`s\
`
`_
`
`
`
`
`Figure 1 Two shapes of MISFET device mask patterns
`
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`
`
`
`
`li1l 1 ‘* uvnmm Clear field Mask #1
`
`Negative photoreslst
`Themally grown
`4500 )1 5101
`
`(I)
`
`
`
`Development of
`Phclorealat;
`Oxlde arch (EOE
`9:1)
`
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`
`diffusion at
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`
`we! drlve-ln
`
`l H le—WW
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`
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`l 4— HF Spuflerad sm,
`<— SIN fllm
`
`
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`UV Rays
`clear Held mask I 5
`lilllllll
`I:I——“+‘”l:l<—-
`(canine! mask)
`‘— Negallvs photoream
`
`(I)
`
`Figure 2 MISFET device fabrication process Steps
`
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`
`
`Develop;e!ch SIM
`and SID: with 9 :1
`EOE
`
`‘
`
`‘ Aluminum
`metalllznllon
`
`
`
`
`
`Clear fleld mask l 4
`<——(motal patterning)
`
`source
`
`Gale
`
`Drain
`
`(1)
`
`Develop:
`Aluminum alch;
`Remove PR
`
`[j
`
`- sm
`
`Silicon dioxide
`
`
`
`- Poailivapholoreslsi
`
`- Nogauvopholoreslnl - Aluminum
`
`Figure 2 MISFET device fabrication process steps (contd.)
`
`Electrochemical Proceedings Volume 97-10
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`

`ID
`
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`
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`Figure 4 Drain current-voltage characteristics for a 20 um‘device
`using silicon nitride as gate dielectric
`
`Electrochemical Proceedings Volume 97—10
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`

`

`CURSOR
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`using silicon nitride as gate dielectric
`
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`using silicon—oxynitride as gate dielectric
`
`Electrochemical Proceedings Volume 97-10
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`

`SHID
`(mA) cunson 4.sooov. 4.93E-03.
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`
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`
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`
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`600
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`Figure 8 Variation of threshold voltage with gate dielectric film
`thickness as function of interface charge density
`
`1000
`
`Electrochemical Proceedings Volume 97— 10
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`