(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2002/0000611 A1
`(43) Pub. Date: Jan. 3, 2002
`
`Hokazono et al.
`
`US 20020000611A1
`
`(54) SEMICONDUCTOR DEVICE HAVING A
`GATE ELECTRODE WITH A SIDEWALL
`INSULATING FILM AND MANUFACTURING
`METHOD THEREOF
`
`(51)
`
`Publication Classification
`
`Int. Cl.7 ........................ .. H01L 29/76; H01L 29/94;
`H01L 31/062
`......................... ..257/333; 257/336; 257/344
`
`(52) us. Cl.
`
`(75)
`
`Inventors: Akira Hokazono, Sagamihara-shi (JP);
`Mariko Takayanagi, Kawasaki-shi (JP)
`
`Correspondence Address:
`Finnegan, Henderson, Farabow,
`Garrett & Dunner, L.L.P.
`1300 I Street, NW.
`Washington, DC 20005-3315 (US)
`
`(73) Assignee: KABUSHIKI KAISHA TOSHIBA
`
`(21) Appl. N0.:
`
`09/892,574
`
`(22)
`
`Filed:
`
`Jun. 28, 2001
`
`(30)
`
`Foreign Application Priority Data
`
`Jun. 30, 2000
`
`(JP) .................................... .. 2000-199627
`
`(57)
`
`ABSTRACT
`
`Agate electrode is provided Via a gate insulating film formed
`between the source and drain regions on a semiconductor
`substrate, wherein the sidewall 0f the gate electrode exclud-
`ing the exposed part formed at the upper part thereof facing
`the source and drain regions is covered with a sidewall
`insulating film, and an epitaxial film is formed on the
`exposed part of the sidewall 0f the gate electrode but not
`formed on a top surface of the gate electrode. An element
`isolation region formed on the semiconductor substrate is
`composed of a first insulating film formed in the semicon-
`ductor substrate and a second insulating film which is
`formed inside the first
`insulating film and has a lower
`epitaxial growth rate than that of the first insulating film, and
`the surface of the source and drain regions is covered with
`a silicon layer, part of which runs onto the surface of the first
`insulating film.
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`Patent Application Publication
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`Jan. 3, 2002 Sheet 1 0f 7
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`Patent Application Publication
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`Patent Application Publication
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`Jan. 3, 2002 Sheet 5 0f 7
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`Patent Application Publication
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`Jan. 3, 2002 Sheet 6 0f 7
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`US 2002/0000611 A1
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`Patent Application Publication
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`Jan. 3, 2002 Sheet 7 0f 7
`
`US 2002/0000611 A1
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`

`

`US 2002/0000611 A1
`
`Jan. 3, 2002
`
`SEMICONDUCTOR DEVICE HAVING A GATE
`ELECTRODE WITH A SIDEWALL INSULATING
`FILM AND MANUFACTURING METHOD
`THEREOF
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`[0001] This application is based upon and claims the
`benefit of priority from the prior Japanese Patent Application
`No. 2000-199627, filed Jun. 30, 2000, the entire contents of
`which are incorporated herein by reference.
`
`BACKGROUND OF THE INVENTION
`
`[0002]
`
`1. Field of the Invention
`
`[0003] This invention relates to a semiconductor device
`with a MOS structure and a manufacturing method thereof.
`
`[0004]
`
`2. Description of the Related Art
`
`[0005] The miniaturization of semiconductor devices hav-
`ing a MOS structure, particularly a CMOS structure, has
`been in progress to meet the demands for higher operation
`speed and higher performance. This makes it necessary to
`form not only the low-concentration shallow diffused
`regions of the source and drain regions in a semiconductor
`substrate but also the high-concentration diffused regions
`after the formation of the low-concentration regions so that
`the high-concentration diffused regions may be of less deep.
`Making a high-concentration diffused layer less deep, how-
`ever, causes junction leakage currents due to a silicide layer
`formed on the high-concentration diffused layer, which also
`causes a power consumption problem.
`
`[0006] To reduce the power consumption, the approach of
`forming a monocrystalline silicon layer on only the source
`and drain diffused regions, or on these diffused layers and
`the gate electrode to make the high-concentration diffused
`layer less deep has been proposed. With this approach,
`junction leakage currents resulting from the silicide layer
`can be suppressed. The structure where monocrystalline
`silicon is selectively formed on only the diffused layers or on
`the diffused layers and the gate electrode is called an
`elevated source-drain (or simply referred to as ESD) struc-
`ture.
`
`In an example of the process of forming the ESD
`[0007]
`structure, a gate sidewall insulating film is formed after the
`formation of a low-concentration diffused layer and silicon
`monocrystalline growth is performed using hydrogen,
`dichlorosilane, and hydrogen chloride as gas sources. Then,
`high-concentration diffused layers are formed from above
`the monocrystalline silicon layer, thereby producing a MOS
`device with an ESD structure, for example, a CMOS device.
`Silicon monocrystalline growth may also be performed after
`the formation of the high-concentration diffused layers.
`
`In the approach of growing silicon in the conven-
`[0008]
`tional ESD-structure CMOS device, there are generally two
`processes.
`In a first process, epitaxial silicon growth is
`performed, with polysilicon (polycrystalline silicon) consti-
`tuting a gate electrode being exposed. In a second process,
`epitaxial silicon growth is performed, with polycrystalline
`silicon constituting a gate electrode not being exposed. Each
`process, however, has the problems explained below.
`
`[0009] FIG. 9 shows an example of the COMS structure
`formed in the first process.
`
`[0010] As shown in FIG. 9, a plurality of well regions 2
`are formed at the surface of a silicon substrate 1. The well
`
`regions 2 are so formed that they overlap partially with each
`other. An element isolation insulating film 3 constituting an
`element isolation region is formed to a specific depth from
`the surface of the silicon substrate 1 in the overlapping part.
`In the region on the silicon substrate 1 and excluding the
`element isolation insulating film 3, that is, in the active
`region or element forming region, a gate electrode 5 is
`selectively formed via a gate insulating film 4. On the
`sidewall of the gate electrode 5, a gate sidewall insulating
`film 6 is provided.
`
`In the vicinity of the surface of the silicon substrate
`[0011]
`1 where neither the gate electrode 5 nor the gate sidewall
`insulating film 6 is formed, high-concentration diffused
`layers 7a and 7b are formed so as to sandwich the region
`directly under the gate electrode 5 between them. These
`high-concentration diffused layers 7a and 7b extend from
`the edge of the gate sidewall insulating film 6 to the element
`isolation insulating film 3. At the silicon substrate 1 surface
`directly under the gate sidewall insulating film 6 in the
`region sandwiched between the high-concentration diffused
`layers 7a and 7b, low-concentration diffused layers 8a and
`8b are formed. These low-concentration diffused layers 8a
`and 8b are formed less deep than the high-concentration
`diffused layers 7a and 7b.
`
`[0012] Silicon films 10 are formed at the surface of the
`high-concentration diffused layers 7a and 7b on which
`neither the gate electrode 5 nor the gate sidewall insulating
`film 6 has been formed. The silicon films 10 are so formed
`
`that they extend from the side of the gate sidewall insulating
`film 6 to the surfaces of the high-concentration diffused
`layers 7a and 7b and cover part of the surface of the element
`isolation insulating film 3.
`
`[0013] On the top surface of the gate electrode 5, a silicon
`film 111 is grown. The upper part of the sidewall of the gate
`electrode 5 is exposed without being covered with the gate
`sidewall insulating film 6. From this exposed part, a silicon
`film 111 is also grown. The silicon film 111 is conductive and
`functions as part of the gate electrode. Thus, this silicon film
`111 and gate electrode 5 form a gate electrode structure.
`
`In the CMOS structure formed by the first process,
`[0014]
`over-etching times generally have to be provided in etching
`in the process of forming the sidewall insulating film 6 of the
`gate, taking into account a margin for process in reactive ion
`etching (RIE). This makes the upper part, or the shoulder
`part, of the gate sidewall insulating film 6 being lower than
`the top surface of the gate electrode 5. When epitaxial silicon
`growth is performed with the lower shoulder part, a problem
`arises: the gate electrode 5 assumes the structure having a
`mushroom shape as shown in FIG. 7, since the top surface
`of the gate electrode 5 and the upper part of its sidewall are
`exposed.
`
`[0015] The mushroom shape of the part acting as the gate
`electrode structure has the advantage that, even when the
`gate electrode 5 is a thin wire, the sheet resistance gets lower
`in proportion to an increase in the length of the gate
`electrode. At the same time, however, the following prob-
`lems arise: the silicon film 111 of the gate electrode structure
`
`

`

`US 2002/0000611 A1
`
`Jan. 3, 2002
`
`is liable to be short-circuited with the silicon film 10 on the
`
`source-drain regions, and the epitaxial growth of the silicon
`film 111 on the polycrystalline silicon constituting the gate
`electrode 5 increases its roughness, making the whole sheet
`resistance higher.
`
`insulating
`[0016] Furthermore, when the gate sidewall
`film 6 is thin, another problem arises: even when ion
`implantation is performed, the mushroom-shaped polycrys-
`talline 111 as shown in FIG. 9 acts as a mask, preventing
`ions from being implanted in the vicinity of the place just
`under the gate sidewall insulating film 6.
`
`[0017] FIG. 10 shows an example of the CMOS structure
`formed in the second process. FIG. 10 differs from FIG. 9
`in that the silicon oxide film 9 is formed as a cap material on
`the gate electrode 5. In the second process, to prevent silicon
`from growing epitaxially on the gate electrode 5, epitaxial
`silicon growth is performed, with the cap material 9 remain-
`ing on the gate electrode 5. The second process can avoid the
`problem of the short-circuiting of the gate electrode 5 with
`the silicon film 10 of the source-drain region as found in the
`first process.
`
`[0018] Since the polycrystalline silicon on the gate elec-
`trode 5 does not grow laterally, this prevents a T-shaped gate
`structure, an advantage of the ESD structure, from being
`formed.
`
`[0019] As described above, in the conventional ESD struc-
`ture manufacturing processes, it is difficult to solve not only
`an ion implantation problem but also the problem of the
`short-circuiting of the gate electrode structure with the
`source region or drain region, while realizing a T-shaped
`gate structure.
`
`in the process of manufacturing a
`[0020] Furthermore,
`CMOS with the ESD structure, a junction leakage current
`problem arises, which will be explained below. FIGS. 9A
`and 9B are sectional views of a MOSFET structure consti-
`
`tuting a CMOS to help explain the junction leakage current
`problem.
`
`[0021] Attention should be given to silicon epitaxial
`growth in the edge region of the element isolation insulating
`film 3 to realize the suppression of junction leakage currents,
`so as to realize an advantage of the ESD structure. Specifi-
`cally, it is desirable that the epitaxially grown silicon film 10
`should run onto the element isolation insulating film to some
`extent (20 nm to 50 nm).
`
`[0022] When an isolation band width of the element
`isolation insulating film 3 gets smaller as a result of further
`miniaturization, the element forming regions isolated by the
`element isolation insulating film 3 are liable to be short-
`circuited and incapable of operating as a device.
`
`[0023] Furthermore, it is difficult to control the process of
`causing the silicon film 10 to run onto the element isolation
`insulating film 3 about 20 nm to 50 nm, while keeping
`selectivity. For this reason, it is often that the silicon hardly
`runs onto the silicon film 10 as shown in FIG. 11A. The
`
`same problem arises in the cases of FIGS. 9 and 10.
`
`[0024] For instance, when a silicide film 131 is formed on
`the basis of the silicon film 10 from the structure of FIG.
`
`11A, 3 silicide reaction might occur at also the sidewall of
`the epitaxial silicon film 10 in the edge region of the element
`isolation insulating film 3. For this reason, the silicide film
`
`131 might be formed to a deep position from the surface of
`the substrate 1 in the edge region of the element isolation
`insulating film 3 as shown in FIG. 11B. This causes junction
`leakage currents to flow significantly. That is, this causes a
`problem in which a merit of using the ESD structure does
`not produce much effect in the edge region of the element
`isolation insulating film 3.
`
`[0025] As described above, in the process of manufactur-
`ing CMOS devices with the conventional ESD structure, it
`is difficult to realize such a structure as avoids not only an
`ion implantation problem but also the problem of the short-
`circuiting of the gate with the source region or drain region,
`while realizing a T-shaped gate structure.
`
`It is, accordingly, an object of the present invention
`[0026]
`to provide a semiconductor device with a T-shaped gate
`structure and a manufacturing method thereof.
`
`[0027] Another object of the present invention is to pro-
`vide a semiconductor device with a silicide film whose
`
`shape is highly controllable and a manufacturing method
`thereof.
`
`BRIEF SUMMARY OF THE INVENTION
`
`[0028] According to a first aspect of the present invention,
`there is provided a semiconductor device comprising: a gate
`insulating film formed on a semiconductor substrate; a gate
`electrode formed on the gate insulating film and having a
`shape defined by a sidewall and a top surface thereof; a
`sidewall insulating film which is formed on a lower part of
`the sidewall of the gate electrode excluding an exposed part
`formed at an upper part of the sidewall of the gate electrode
`and which is formed on a specific region of the surface of the
`semiconductor substrate adjacent to the gate electrode; and
`an epitaxial film formed on the exposed part, the epitaxial
`film being not formed on the top surface of the gate
`electrode.
`
`[0029] With this configuration, no epitaxial film is formed
`at the top of the gate electrode, and an epitaxial film is
`formed horizontally only on the exposed part at the upper
`part of the sidewall of the gate electrode. This epitaxial film
`and gate electrode forms a T-shaped gate structure. Such a
`T-shaped gate structure helps decrease the sheet resistance of
`the gate electrode.
`
`[0030] The top of the gate electrode has no epitaxial film
`grown, with the result that the gate electrode structure does
`not take the form of a mushroom as found in the prior art and
`therefore the silicide layer formed on the source and drain
`regions is prevented from being short-circuited with the gate
`electrode structure.
`
`[0031] According to another aspect of the present inven-
`tion, there is provided a semiconductor device comprising:
`a silicon semiconductor substrate; a groove section formed
`to a specific depth from a surface of the semiconductor
`substrate so as to separate the silicon semiconductor sub-
`strate into a plurality of regions; an element isolation region
`which is formed by burying at least a first and second
`insulating films differing in silicon epitaxial growth rate
`sequentially in the groove section and which defines element
`forming regions on the silicon semiconductor substrate; a
`gate electrode selectively formed on a first region of the
`element forming region of the silicon semiconductor sub-
`strate defined by the element isolation region via a gate
`
`

`

`US 2002/0000611 A1
`
`Jan. 3, 2002
`
`insulation film; a source region and a drain region formed in
`a second region of the element forming region of the surface
`of the silicon semiconductor substrate, the first region being
`sandwiched between the source region and the drain region;
`and a silicide film formed so as to cover from the source
`
`region and drain region to the first insulating film in the
`element isolation region of the silicon semiconductor sub-
`strate, wherein the first insulating film is made of a material
`whose silicon epitaxial growth rate is higher than that of the
`second insulating film.
`
`[0032] With this configuration, a silicon film formed on
`the surface of the source region and drain region runs onto
`the first insulating layer in the element isolation region, but
`not onto the second insulating layer. As a result, junction
`leakage currents do not occur. Moreover, the silicon film is
`prevented effectively from being short-circuited with a sili-
`con film formed on the transistors made in adjacent element
`forming regions in the element isolation region.
`
`[0033] Additional objects and advantages of the invention
`will be set forth in the description which follows, and in part
`will be obvious from the description, or may be learned by
`practice of the invention. The objects and advantages of the
`invention may be realized and obtained by means of the
`instrumentalities and combinations particularly pointed out
`hereinafter.
`
`BRIEF DESCRIPTION OF THE SEVERAL
`VIEWS OF THE DRAWING
`
`[0034] The accompanying drawings, which are incorpo-
`rated in and constitute a part of the specification, illustrate
`presently embodiments of the invention, and together with
`the general description given above and the detailed descrip-
`tion of the embodiments given below, serve to explain the
`principles of the invention.
`
`[0035] FIG. 1 is a longitudinal sectional view showing the
`overall configuration of a semiconductor device according to
`a first embodiment of the present invention;
`
`[0036] FIGS. 2A to 2D are sectional views to help explain
`the processes in a method of manufacturing the semicon-
`ductor device of the first embodiment;
`
`[0037] FIG. 3 is a sectional view showing a configuration
`of a semiconductor device according to a modification of the
`first embodiment;
`
`[0038] FIG. 4 is a sectional view showing a configuration
`of a semiconductor device according to a second embodi-
`ment of the present invention;
`
`[0039] FIGS. 5A to 5D are sectional views to help explain
`the processes in a method of manufacturing the semicon-
`ductor device of the second embodiment;
`
`[0040] FIG. 6 is a sectional view showing a configuration
`of a semiconductor device according to a modification of the
`second embodiment of the present invention;
`
`[0041] FIG. 7 is a longitudinal sectional view showing the
`overall configuration of a semiconductor device according to
`a third embodiment of the present invention;
`
`[0042] FIGS. 8A to SF are sectional views to help explain
`the processes in a method of manufacturing the semicon-
`ductor device of the third embodiment;
`
`[0043] FIG. 9 is a sectional view to help explain a
`problem of the gate structure of a conventional semicon-
`ductor device;
`
`[0044] FIG. 10 is a sectional view to help explain another
`problem of the gate structure of the conventional semicon-
`ductor device; and
`
`[0045] FIGS. 11A and 11B are sectional views to help
`explain a problem of the silicide film extending into the
`element isolation region of the conventional semiconductor
`device.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`[0046] Hereinafter, referring to the accompanying draw-
`ings, embodiments of
`the present
`invention will be
`explained. Although the embodiments will be explained
`using the n-type or p-type conductivity, these conductivity
`types are interchangeable. Explanation will be given using
`only one conductivity type for the sake of clarity.
`
`[0047]
`
`(First Embodiment)
`
`[0048] FIG. 1 is a sectional view showing the overall
`configuration of a semiconductor device according to a first
`embodiment of the present invention. As shown in FIG. 1,
`numeral 1 indicates a p-type silicon substrate. In the silicon
`substrate 1, a plurality of well regions 2 obtained by diffus-
`ing n-type impurities are formed. The well regions 2 are so
`formed that they overlap with each other. Element isolation
`regions 3 are formed to a specific depth from the surface of
`the silicon substrate 1 in the overlapping parts.
`
`[0049] A gate electrode 5 is selectively formed via a gate
`insulating film 4 above the silicon substrate 1 and in an
`element forming region excluding the element
`isolation
`region 3. On the sidewall of the gate electrode 5, a gate
`sidewall insulating film 6 is provided. In the vicinity of the
`surface of the silicon substrate 1 where neither the gate
`electrode 5 nor the gate sidewall insulating film 6 is pro-
`vided, high-concentration diffused layers 7a and 7b are
`formed so as to sandwich the region directly under the gate
`electrode 5 between them. These high-concentration dif-
`fused layers 7a and 7b extend from the edge of the gate
`sidewall insulating film 6 to the element isolation regions 3.
`
`[0050] At the surface of the silicon substrate 1 just under
`the gate sidewall insulating film 6 and in the region sand-
`wiched between the high-concentration diffused layers 7a
`and 7b, low-concentration diffused layers 8a and 8b are
`formed. The depth of the low-concentration diffused layers
`8a and 8b is less than the depth of the high-concentration
`diffused layers 7a and 7b.
`
`[0051] On the surface of the silicon substrate 1 where
`neither the gate electrode 5 nor the gate sidewall insulating
`film 6 is formed, a silicide film 16 is formed. The silicide
`film 16 is so formed that it extends from the side of the gate
`sidewall insulating film 6 onto the high-concentration dif-
`fused layers 7a and 7b and further covers part of the surface
`of the element isolation region 3.
`
`[0052] The top surface region of the gate electrode 5 is
`formed as a silicide region 5a. The upper part of the sidewall
`of the gate electrode 5 is exposed without being covered
`with the gate sidewall insulating film 6 and the exposed
`portion is provided with silicide films 17. The silicide films
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`US 2002/0000611 A1
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`Jan. 3, 2002
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`17 are so formed at exposed parts that they project in both
`directions of gate length. The height of each of the silicide
`films 17 in the direction of gate length is 10 nm to 50 nm,
`preferably 10 nm to 20 nm.
`
`[0053] The silicide films 17 are conductive and functions
`as part of a gate electrode structure. This silicide film 17 and
`the gate electrode 5 form a T-shaped gate electrode structure.
`
`[0054] On the gate electrode structure, silicide films 16,
`and element isolation regions 3, an interlayer insulating film
`12 is formed. In the interlayer insulating film 12, a contact
`hole reaching the silicide film 16 is made. In the contact
`hole, a contact plug 13 made of, for example, Ti or TiN or
`W is formed so as to fill the hole. On the interlayer insulating
`film 12 and contact plug 13, an interlayer insulating film 14
`is formed. In the interlayer insulating film 14, a groove
`section reaching the contact plug 13 is made. A wire 15 is
`buried in the groove section. These realize a MOS device
`structure of one conductivity type constituting, for example,
`a CMOS device. That is, although not shown, combining
`such a MOS device structure of the p-type with that of the
`n-type produces a COMS device structure.
`
`[0055] Using sectional views of processes in FIGS. 2A to
`2D, a method of manufacturing a semiconductor device of
`the first embodiment shown in FIG. 1 will be explained.
`First, as shown in FIG. 2A, for example, 350-nm-deep
`groove sections are made in the p-type silicon substrate 1.
`The element isolation insulating films 3 made of a silicon
`nitride film are buried in the groove sections by a buried
`element isolating method, thereby forming element isolation
`regions. Then, n-type impurities, such as phosphorus, are
`ion-implanted into the regions where the element isolation
`insulating films 3 have not been formed and onto the silicon
`substrate 1. Then, using active RTA, an n-type well 2 is
`formed to a specific depth. The condition for
`the ion
`implantation is, for example, at 500 Kev with a dose of
`3.0><10 cm'z'
`
`In the adjacent active region, a well of the opposite
`[0056]
`conductivity type, for example, the p-type is formed. The
`condition for ion implantation of, for example, boron into
`the p-type well is at 260 KeV with a dose of 2.0><1013 cm'2.
`
`[0057] After the formation of the well 2, for example,
`boron is ion-implanted to a specific depth from the surface
`of the silicon substrate 1 to form a region that is to function
`as a channel. The condition for the ion implantation is, for
`example, at 50 KeV with a dose of 1.5><1013 cm'2. There-
`after, using active RTA, the impurities are diffused, thereby
`forming a channel region 2a.
`
`[0058] Then, by thermal oxidation techniques or LPCVD
`techniques, a gate insulating film 4 is formed to a thickness
`of, for example, 1.5 nm to 6.0 nm. On the gate insulating
`film 4, a gate electrode 5 made of, for example, polysilicon
`is formed to a thickness of, for example, 100 nm to 200 nm.
`Furthermore, on the gate electrode 5, a silicon oxide film 9
`is formed to a thickness of 20 nm to 70 nm, preferably about
`20 nm, by LPCVD techniques.
`
`[0059] The gate insulating film 4 may be not only a silicon
`oxide film but also SiON, SiN, or TazOs, high dielectric
`material. The gate electrode 5 may be made of not only
`polysilicon but also a metal gate structure using W with TiN
`and WN as a barrier metal.
`
`[0060] Thereafter, using photolithography, X-ray lithog-
`raphy, or electron-beam lithography, a resist mask is formed,
`leaving the gate insulating film 4, gate electrode 5, and
`silicon oxide film 9, for example, 50 nm to 150 nm in width.
`Then, etching is done by reactive ion etching (RIE) tech-
`niques. This forms a stacked structure composed of the gate
`insulating film 4, gate electrode 5, and silicon oxide film 9
`each with a gate length of 50 nm to 150 nm, on the
`semiconductor substrate 1. The silicon oxide film 9 func-
`
`tions as a cap material in growing a silicon film 11 formed
`later at the upper part of the sidewall of the gate electrode 5.
`
`[0061] Next, with the gate electrode 5 as a mask, ions are
`implanted into the element forming region where the ele-
`ment isolation insulating film 3 has not been formed, thereby
`forming low-concentration diffused layers 8a and 8b. In the
`case of n-type diffused layers, boron is ion-implanted at 1 to
`5 Kev in a dose range from 5.0><1014 cm"2 to 1.0x1015 cm'2.
`In the case of p-type diffused layers, BF2 is ion-implanted at
`1 to 3 Kev in a dose range from 5.0><1014 cm"2 to 1.0><1015
`cm'2. After the ion implantation, active RTA is performed.
`
`[0062] Then, as shown in FIG. 2B, a silicon nitride film
`is deposited on the whole surface of the device by LPCVD
`techniques. The silicon nitride film is etched back by reac-
`tive ion etching (RIE) techniques or the like. The etch-back
`process is continued until the height of the top surface of the
`silicon nitride film formed on the sidewall of the gate
`electrode 5 has become lower than that of the top surface of
`the gate electrode 5. This allows the upper part of the
`sidewall of the gate electrode 5 etched back earlier to be
`exposed from the silicon nitride film and thereafter the
`surface of the diffused layers 8a and 8b to be exposed,
`causing the gate sidewall insulating film 6 to remain on the
`sidewall of the gate electrode 5. It is desirable that the silicon
`oxide film 9 should have such a thickness as remains even
`
`after the upper part of the sidewall of the gate electrode 5 has
`been exposed by etch-back.
`
`In etching back the silicon nitride film, silicon is
`[0063]
`exposed to RIE at the surface of the diffused layers 8a and
`8b. This permits damage layers or carbon layers to get mixed
`with the diffused layers 8a and 8b. Thus, it is desirable that
`damage to the surface of the diffused layers 8a, 8b should be
`removed by oxidizing the substrate surface by RIE using O2
`gas and then eliminating the oxidized surface portion using
`dilute fiuoric acid. It is further desirable that the silicon
`oxide film 9 should have such a thickness as remains after
`
`the surface of the diffused layers 8a and 8b has been
`processed.
`
`[0064] Next, after the surface of the silicon substrate 1 is
`subjected to high-temperature processing in an atmosphere
`of hydrogen to remove the natural oxidation film, monoc-
`rystalline epitaxial growth is performed at the surface of the
`silicon substrate 1 as shown in FIG. 2C. Specifically, the
`device is heated in an atmosphere of hydrogen at a high
`temperature higher than 800° C. and the reactive gas, such
`as SiH4, SinClz, or SiHCl3,
`is supplied together with
`hydrogen to the device. As a result, the silicon film 11 is
`formed horizontally at the part where the polycrystalline
`silicon of the gate electrode, that is, at the upper part of the
`sidewall of the gate electrode 5. Furthermore, the silicon
`film 10 is formed on the diffused layers 8a and 8b.
`
`[0065] On the top surface of the gate electrode 5, the
`silicon oxide film 9 is remained as a cap material. The
`
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`US 2002/0000611 A1
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`Jan. 3, 2002
`
`remaining silicon oxide film 9 prevents silicon from growing
`on the top surface of the gate electrode 5. Consequently,
`silicon is prevented from growing into the shape of a
`mushroom as in the conventional manufacturing method
`shown in FIG. 9, eliminating the danger of short-circuiting
`with the silicon film 10. Therefore, there is no possibility
`that the gate electrode structure of the present embodiment
`will be short-circuited with the source-drain region.
`
`[0066] Only the upper part of the sidewall of the gate
`electrode 5 is exposed. At its lower part, a silicon nitride film
`is provided as the gate sidewall insulating film 6. This allows
`silicon to grow only from the exposed upper part of the gate
`electrode 5. As a result, silicon grows from the sidewall of
`the gate in the directions of gate length and gate width. That
`is, silicon selectively grows only horizontally, or in the
`direction of gate length as shown in FIG. 2C and also in the
`direction of gate width perpendicular to the direction of the
`gate length. This growth in the horizontal direction is based
`on the fact that the epitaxial growth rate on the polycrys-
`talline silicon is so fast than that of the silicon nitride film 6
`or the silicon oxide film 9.
`
`In the epitaxial growth device used for selective
`[0067]
`epitaxial growth, the shape of the reactive chamber may be
`of the upright type, the barrel type, or the cluster type. The
`heating system may be of the resistance heating type, the
`high-frequency heating type, or the lamp heating type. The
`wafer processing system may be of the sheet type or the
`batch type. This epitaxial growth may be performed after the
`formation of high-concentration diffused layers 7a and 7b
`explained later.
`
`[0068] Through the process of such epitaxial growth, a
`T-shaped gate structure as shown in FIGS. 2C and 2D is
`obtained. The T-shaped structure is such that
`the gate
`electrode 5 is formed in the direction perpendicular to the
`surface of the silicon substrate 1 and the silicon film 11
`
`extends from the upper part of the sidewall of the gate
`electrode 5 in the direction of gate length. Both of the gate
`electrode 5 and silicon film 11 are conductive and as a whole
`
`function as a gate electrode structure. This gate electrode
`structure makes it possible to realize a MOSFET structure
`with high resistance to the short-circuiting of the gate
`electrode with the source-drain region, that is, high bridging
`resistance. Therefore, even when the gate electrode 5 has a
`fine-wire structure, the silicide sheet resistance of the silicide
`layer 17 on the gate electrode 5 can be made low as will be
`explained below.
`
`[0069] Then, as shown in FIG. 2D, after t