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`PATENT
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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
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`In re Application of
`Masafumi TSUTSUI, et al.
`Application No.: 12f170,191
`Filed: July 09, 2008
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`:
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`Customer Number: 53080
`Continuation Number: 1644
`Group Art Unit: 2814
`Examiner: Howard Weiss
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`For:
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`SEMICONDUCTOR DEVICE INCLUDING MISFET HAVING INTERNAL STRESS
`FILM (as amended)
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`AMENDMENT
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`Mail Stop Amendment
`Commissiorler for Patents
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`PO. Box 1450
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`Alexandria, VA 22313-1450
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`Sir:
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`In response to the Office Action dated May 10, 2010, wherein a three-month shortened
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`statutory period for response is set to expire on August 10, 2010, Applicants respectfully request
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`reconsideration of the above-identified application in View of the following amendments and
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`remarks.
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`WDC99 [9032764 .0T9195.0566
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`TSMC 1303
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`TSMC 1303
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`Application No.: 12i170,l9l
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`IN THE CLAIMS:
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`This listing ofclaims will replace all prior versions and listings ofclaims in the application
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`Listing of Claims
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`1-14.
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`(Cancelled)
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`15,
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`(Currently Amended) A semiconductor device, comprising a MISFET, wherein
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`the MISFET includes:
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`an active region made of a semiconductor substrate;
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`a gate insulating film formed on the active region;
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`a gate electrode formed on the gate insulating film;
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`sourcez’drain regions formed in regions of the active region located on both sides of the
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`gate electrode; and
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`a silicon nitride film formed over from side surfaces of the gate electrode to upper
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`surfaces of the sourceidrain regions, wherein;
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`the silicon nitride film is not formed on an upper surface of the gate electrode, at
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`the gate electrode protrudes upward from a surface level of parts of the silicon nitride
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`film located at both side surfaces of the gate electrode.
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`Application No.: 12;“ 170,191
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`16.
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`(Previously presented) The semiconductor device of claim 15, wherein
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`the silicon nitride film is for generating a stress in a substantially parallel direction to the
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`gate length direction in a channel region located in the active region under the gate electrode.
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`1?.
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`(Previously presented) The semiconductor device of claim 16, wherein
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`the substantially parallel direction of the stress includes a direction tilted by an angle of
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`less than 10 degree from a direction in which carriers move.
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`18.
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`(Previously presented) The semiconductor device of claim 15, wherein
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`the silicon nitride film is directly in contact with the sourcefdrain regions,
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`19.
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`(Previously presented) The semiconductor device of claim 15, wherein
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`the silicon nitride film is formed ab0ve the sourcefdrain regions with a thin film
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`interposed therebetween.
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`20.
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`(Currently amended) The semiconductor device of claim 15, wherein
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`the source/drain regions include lightly doped impurity regions formed in regions of the
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`active region located on both sides of the gate electrode, heavily doped impurity regions formed
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`in regions of the active region respectively extending outwardly from the lightly doped impurity
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`regions to be in contact with the lightly doped impurity regions and having a higher impurity
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`concentration than that of the lightly doped impurity regions, and a silicide layer.
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`21.
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`(Currently amended) The semiconductor device of claim 15, further comprising:
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`Application No.: 12f170,191
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`a sidewall formed on the side surface of the gate electrode wherein
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`the silicon nitride film is formed over the side surfaces of the gate electrode with the
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`sidewall interposed between the silicon nitride film and the side surface of the gate electrode.
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`22.
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`(Previously presented) The semiconductor device of claim 15, wherein
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`a principal surface of the semiconductor substrate is substantially a {100} plane, and
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`the gate length direction of the gate electrode is substantially a <011> direction.
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`23.
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`(Previously presented) The semiconductor device of claim 15, further
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`comprising:
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`an interlevel insulating film formed on the silicon nitride film; and
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`a contact plug provided so as to pass through the interlevel insulating film and the silicon
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`nitride film and to be connected to the sourcefdrain regions.
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`24.
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`(Currently amended) The semiconductor device of claim 15, wherein;
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`the active region is divided by an isolation region formed in the semiconductor substrate,
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`fli
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`the silicon nitride film is formed to extend over the isolation region as well as the
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`sourcer'drain regions.
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`25.
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`(Previously presented) The semiconductor device of claim 15, wherein
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`the gate insulating film is a silicon oxide film.
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`26.
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`(Previously presented) The semiconductor device of claim 15, wherein
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`the gate insulating film is a silicon oxynitride film.
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`27.
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`(Previously presented) The semiconductor device of claim 15, wherein
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`the gate electrode has a polysilicon film.
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`28.
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`(Previously presented) The semiconductor device of claim 15, wherein
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`the gate electrode has a metal film.
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`29.
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`(Previously presented) The semiconductor device of claim 15, wherein
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`the silicon nitride film is provided so as to cover at least part of at least one of the
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`sourcer’drain regions.
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`30.
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`(Previously presented) The semiconductor device of claim 15, wherein
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`the silicon nitride film covers at least respective parts of the sourcel'drain regions.
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`31.
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`(Previously presented) The semiconductor device of claim 15, wherein
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`the silicon nitride film covers at least respective parts of both side surfaces of the gate
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`electrode.
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`32.
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`(Previously presented) The semiconductor device of claim 15, wherein
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`the MISFET is an nMISFET and
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`the source/drain regions are n—type sourcefdrain regions.
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`33.
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`(Previously presented) The semiconductor device of claim 32, wherein
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`the silicon nitride film is for generating a tensile stress in a substantially parallel direction
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`to the gate length direction in a channel region located in the active region under the gate
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`electrode.
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`34.
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`(Previously presented) The semiconductor device of claim 32, wherein
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`the n—type sourcefdrain regions include an n-type lightly doped impurity region, an n-type
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`heavily doped impurity region and a silicide layer.
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`35.
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`I
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`(Previously presented) The semiconductor device of claim 15, wherein the silicon
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`nitride film directly contacts with the side surfaces of the gate electrode.
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`36.
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`(Previously presented) The Semiconductor device of claim 24, wherein a lower
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`Surface of the isolation region is located in the semiconductor substrate and is in direct contact
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`with the semiconductor substrate.
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`3?.
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`(New) The semiconductor device of claim 15, wherein
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`an upper surface of the gate electrode is higher than an upper surface of the parts of the
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`silicon nitride film located at both side surfaces of the gate electrode.
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`Applicatiori No.: 12f170,191
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`38.
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`(New) The semiconductor device of claim 15, wherein
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`the gate insulating film is formed only under a lower surface of the gate electrode.
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`39,
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`(New) The semiconductor device of claim 15, further comprising:
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`a sidewall formed on the side surface of the gate electrode;
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`an inter-level insulating film formed on the silicon nitride film;
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`an isolation region formed in the semiconductor substrate to divide the active regiori; and
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`a contact plug provided so as to pass through the interlevel insulating film and the silicon
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`nitride film and to be connected to the sourcer'drain regions, wherein
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`the silicon nitride film is formed over the side surfaces of the gate electrode with the
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`sidewall interposed between the silicon nitride film and the side surface of the gate electrode and
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`to extend over the isolation region as well as the source!drain regions.
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`Application No.: 12i170,191
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`Status of Claims
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`REMARKS
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`Claims 15-39 are pending, of which claim 15 is independent.
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`Claims 15, 20, 21 and 24 have been amended to correct informalities in the claim
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`language and to more clearly define the claimed subject matter. Claims 37-39 have been added.
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`Support for the amendment and the new claims is found at, for example, FIGS. 1 and 4A. Care
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`has been taken to avoid introducing new matter.
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`Rejection under 35 U.S.C. § 103
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`Claims 15-21, 23-34 and 36 were rejected under 35 U.S.C. § 103(a) as being
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`unpatentable over Xiang et al. (US 6,43 7,404) and Matsuda et al. (US 6,870,230). Claims 22
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`and 35 were rejected under 35 U.S.C. § 103(a) as being unpatentable over Xiang et al. and
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`Matsuda et al., and further in View of Tatsuta (US 5,023,676). These rejections are traversed for
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`at least the following reasons.
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`Applicants respectfully submit that, at a minimum, none of the cited references discloses
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`or suggests that “the gate electrode protrudes upwardfiom a surface level ofparts office silicon
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`nitridefilm located at both side surfaces ofthe gate electrode,” as recited by amended claim 15.
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`In the present subject matter, as shown in, for example, FIGS. 1 and 4A, the gate electrode 6a, 6b
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`protrudes upward from a surface level of parts of the silicon nitride film 8a, 8b located at both
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`side surfaces of the gate electrode 6a, 6b. In other words, a height of the gate electrode from the
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`surface of the substrate is higher than a height of the silicon nitride film disposed at the sides of
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`the gate electrode.
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`Application No.: 12f170,191
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`In contrast, as shown in FIG. 1 of Xiang, it is clear that the upper surface of the gate
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`electrode 56 is at the same level as that of an upper end surface of the etch stop layer 80, 82 Ge,
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`the alleged silicon nitride film) located at both side surfaces of the gate electrode 56. As such, in
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`Xiang, the gate electrode 56 does not protrude from a surface level of the parts of the silicon
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`nitride film 80, 82 located at the both side surfaces of the gate electrode 56.
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`In Matsuda, as shown in FIG. 9A, it is also clear that the upper surface of the gate
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`electrode 6a is at the same level as that of an upper end surface of the parts of the protective
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`insulating film 9a (i.e., the alleged silicon nitride film) located at both side surfaces of the gate
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`electrode 6a. As such, it is clear that Matsuda also fails to disclose or suggest that the gate
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`electrode protrudes upward from a surface level of parts of the silicon nitride film located at both
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`side surfaces of the gate electrode.
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`Accordingly, it is clear that the combination of Xiang and Matsuda still fails to disclose
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`the above identified features of amended claim 15. Further, it is also clear that the remaining
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`cited reference does not cure the deficiencies of Xiang and Matsuda, and it would not have been
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`obvious to add these features to any combination of the cited references. Thus, Applicants
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`submit that claim 15 and all claims dependent thereon are patentable over the cited references.
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`New claims
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`Since new claims 37-39 depend upon claim 15, claims 37-39 are patentable for at least
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`the same reasons as claim 15.
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`Application No: 12/170,191
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`W
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`Having fully responded to all matters raised in the Office Action, Applicants submit that
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`all claims are in condition for allowance, an indication for which is respectfully solicited. If
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`there are any outstanding issues that might be resolved by an interview or an Examiner’s
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`amendment, the Examiner is requested to call Applicants’ attorney at the telephone number
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`shown below.
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`To the extent necessary, a petition for an extension of time under 37 C.F.R. § 1.136 is
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`hereby made. Please charge any shortage in fees due in connectiou with the filing of this paper,
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`including extension of time fees, to Deposit Account 500417 and please credit any excess fees to
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`such deposit account.
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`Respectfully submitted,
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`McDERMOTT WILL & EMERY LLP
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`Takashi Saito
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`Limited Recognition No. L0123
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`Please recognize our Customer N0. 53080
`as our correspondence address.
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`600 13:lh Street, NW.
`Washington, DC 20005-3096
`Phone: 202.756.8000 TS:MaM
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`Facsimile: 202.756.8087
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`Date: August 6, 2010
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`-10-
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