`Filed By: David L. Cavanaugh, Reg. No. 36,476
`Dominic E. Massa, Reg. No. 44,905
`Michael H. Smith, Reg. No. 71,190
`1875 Pennsylvania Ave. NW
`Washington, DC 20006
`Tel: (202) 663-6000
`Email: David.Cavanaugh@wilmerhale.com
`Dominic.Massa@wilmerhale.com
`MichaelH.Smith@wilmerhale.com
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
`Petitioner
`
`v.
`
`GODO KAISHA IP BRIDGE 1
`Patent Owner.
`
`Case IPR2017-01844
`
`
`PETITIONER’S UPDATED EXHIBIT LIST
`
`
`
`
`U.S. Patent 7,893,501
`IPR2017-01844
`Petitioner’s Updated Exhibit List
`
`
`
`
`Pursuant to the Board’s Order dated December 29, 2017, Petitioner hereby
`
`submits the December 19, 2017 Conference Call Transcript as Exhibit 1334 and
`
`the infringement contentions dated February 1, 2017 for U.S. Patent 7,893,501
`
`from Godo Kaisha IP Bridge 1 v. Xilinx, Inc., Case No. 2:17-cv-00100 (E.D. Tex.)
`
`as Exhibit 1335. Petitioner also hereby submits an updated exhibit list.
`
`
`
`
`
`Respectfully Submitted,
`
`/ Michael Smith/
`
`_______________________________
`Michael H. Smith
`Registration No. 71,190
`Wilmer Cutler Pickering
`Hale & Dorr LLP
`Tel: 202-663-6000
`Fax: 202-663-6363
`
`1
`
`
`
`U.S. Patent 7,893,501
`IPR2017-01844
`Petitioner’s Updated Exhibit List
`
`
`CERTIFICATE OF SERVICE
`I hereby certify that, on January 9, 2018, I caused a true and correct copy of the
`
`foregoing materials:
`
` Petitioner’s Updated Exhibit List
` Petitioner’s List of Exhibits
` Exhibits 1334 and 1335
`
`to be served via email on the following counsel of record as listed in Patent
`
`Owner’s Mandatory Notices:
`
`Gerald B. Hrycyszyn, Registration No. 50,474
`GHrycyszyn-PTAB@wolfgreenfield.com
`
`Richard F. Giunta, Registration No. 36,149
`RGiunta-PTAB@wolfgreenfield.com
`
`Edmund J. Walsh, Registration No. 32,950
`EWalsh-PTAB@wolfgreenfield.com
`
`Wolf, Greenfield & Sacks, P.C.
`600 Atlantic Avenue
`Boston, Ma 02210
`
`
`Respectfully Submitted,
`
`/ Michael Smith/
`
`___________________________
`Michael H. Smith
`Registration No. 71,190
`
`1
`
`
`
`U.S. Patent 7,893,501
`IPR2017-01844
`Petitioner’s Updated Exhibit List
`
`
`PETITIONER’S LIST OF EXHIBITS FOR
`IPR2017-01844
`
`Exhibit
`1301
`
`U.S. Patent No. 7,893,501
`
`Description
`
`1302
`
`1303
`
`1304
`
`1305
`
`1306
`
`1307
`
`1308
`
`1309
`
`1310
`
`1311
`
`1312
`
`1313
`
`1314
`
`1315
`
`Declaration of Stanley R. Shanfield, Ph.D. Regarding U.S. Patent
`No. 7,893,501, Claims 6, 12, 13, 19 and 21 (“Shanfield Decl.”)
`
` Applicant’s Amendment and Response dated August 6, 2010
`
`U.S. Patent No. 5,960,270 to Misra et al. (“Misra”)
`
`U.S. Patent No. 5,472,890 to Oda (“Oda”)
`
`U.S. Patent Publication No. 2002/0000611 to Hokazono et al.
`(“Hokazono”)
`
`U.S. Patent Publication No. 2002/0145156 to Igarashi et al.
`(“Igarashi”)
`
`U.S. Patent No. 6,072,237 to Jang et al. (“Jang”)
`
`J. Plummer et al., Silicon VLSI Technology: Fundamentals,
`Practice, and Modeling, (1st ed. 2000)
`
`K. Maex et al, Simply irresistible silicides, Physics World, at 35-39
`(Nov. 1995)
`
` J. Rabaey et al., Digital Integrated Circuits, at 40-44 (2d ed. 2003)
`(“Rabaey”)
`
`U.S. Patent Application No. 2003/0011043 (“Roberts”)
`
`U.S. Patent No. 4,951,100 (“Parrillo”)
`
`U.S. Patent No. 6,110,827 to Chien et al. (“Chien”)
`
`U.S. Patent No. 6,444,566 to Tsai et al. (“Tsai”)
`
`i
`
`
`
`Exhibit
`1316
`
`1317
`
`1318
`
`1319
`
`1320
`
`1321
`
`1322
`
`1323
`
`1324
`
`1325
`
`1326
`
`1327
`
`U.S. Patent 7,893,501
`IPR2017-01844
`Petitioner’s Updated Exhibit List
`
`
`Description
`
`Togo, M. et al. “Low Leakage and High Reliability 1.5 nm SiON
`Gate-Dielectric Using Radical Oxynitridation for Sub-0.1 µm
`CMOS,” 2000 Symposium on VLSI Technology Digest of
`Technical Papers (2000) (“Togo”)
`
` U.S. Patent No. 6,228,777 (“Arafa”)
`
`U.S. Patent No. 6,509,234
`
`U.S. Patent No. 5,726,479
`
`U.S. Patent No. 6,512,266
`
`U.S. Patent No. 6,806,584
`
`J. Moon et al., A New LDD Structure: Total Overlap with
`Polysilicon Spacer (TOPS), IEEE Electron Device Letters, Vol. 11,
`No. 5, at 221-223 (May 1990)
`
`D. Baglee et al., Reduced Hot-Electron Effects in MOSFET’s with
`an Optimized LDD Structure, IEEE Electron Device Letters, Vol.
`EDL-5, No. 10, at 389-391 (Oct. 1984)
`
`U.S. Patent No. 6,383,906 to Wieczorek et al. (“Wieczorek”)
`
`K.B. Sundaram et al., Fabrication of Metal Field Effect Transistors
`Using Silicon Nitride and Silicon-Oxynitride as Gate Insulators,
`Electrochemical Proceedings, vol. 97-10 (1997) (“Sundaram”)
`
`Kastenmeier et al., “Remote plasma etching of silicon nitride and
`silicon dioxide using NF3/O2 gas mixtures,” J. Vac. Sci. Technol. A
`16(4), Jul/Aug 1998 (“Kastenmeier”)
`
`High k dielectrics – Current status and Materials Properties
`Considerations, Wilk, G.D., et al., J. App. Phy. Vol. 89, No. 10,
`May 15, 2001
`
`ii
`
`
`
`U.S. Patent 7,893,501
`IPR2017-01844
`Petitioner’s Updated Exhibit List
`
`
`Description
`Exhibit
`1328 W.O. Publication No. 2002/043151 with certified English
`translation (“Shimizu”)
`
`1329
`
`1330
`
`1331
`
`1332
`
`1333
`
`1334
`
`1335
`
`
`
`U.S. Patent No. 5,286,344 to Blalock et al. (“Blalock”)
`
`Interaction of Transition Metals with Silicon (100): The Ni-Si, Co-
`Si and Au/Si(100) Systems, by Steven Naftel, Graduate Program in
`Chemistry, The University of Western Ontario, July 1999 (Naftel).
`
`Notice of Allowance dated October 15, 2010
`
`U.S. Patent No. 6,326,301 to Venkatesan et al. (“Venkatesan”)
`
`M. Green et al., Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric
`layers for silicon microelectronics: Understanding the processing,
`structure, and physical and electrical limits, J. Appl. Phys., Vol.
`90, No. 5, at 2057-2121 (Sep. 1, 2001)
`
`December 19, 2017 Conference Call Transcript
`
`Infringement contentions dated February 1, 2017 for U.S. Patent
`7,893,501 from Godo Kaisha IP Bridge 1 v. Xilinx, Inc., Case No.
`Case No. 2:17-cv-00100 (E.D. Tex.)
`
`
`
`iii
`
`