`
`584
`
`IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 38, NO. 3, MARCH 1993
`
`Hot-Carrier Injection Suppression Due to the
`Nitride-Oxide LDD SpacerStructure
`
`Tomohisa Mizuno, Member, IEEE, Shizuo Sawada, Yoshikazu Saitoh, and Takeshi Tanaka
`
`Ahstract—Hot carrier effects in silicon nitride LDD spacer MOS-
`FET’s have been investigated. It is found that the oxide thickness un-
`der the nitride film spacer affects hot-carrier effects. The thinner the
`LDD spacer oxide becomes, the larger the initial drain current deg-
`radation becomes at dc stress test and,
`in addition, the smaller the
`stress time dependence becomes. Moreover, after the de stress test,
`reduced drain current recovers at room temperature. These phenom-
`ena are due to the large hot-carrier injection into the LDD nitride
`spacer, because the nitride film barrier height is much less than the
`silicon oxide barrier height. Therefore,it is necessary to form the ILDD
`spacer oxide, in order to suppress the large hot-carrier injection in the
`nitride film LDD spacer MOSFET. Furthermore, the drain current
`shift mechanism in the nitride LDD spacer MOSFET’s is also dis-
`cussed, considering the lucky electron model.
`
`I.
`
`INTRODUCTION
`
`
`
`
`GATE
`
`SigNg
`
`GATE
`
`CVD-Si0, Si0g~
`
`AS
`
`ee gG, Nora
`
`P-well
`ENERALLY, CVD-SiO, material has been used as the
`(b)
`LDD spacer [1]. Recently, LDD MOSFET’s withasilicon
`nitride spacer were studied [2], [3]. However, the nitride spacer
`is reported to cause large degradation in LDD MOSFET’s, the
`mechanism of which is not quite clear [2]. Moreover, while it
`is known that LDD MOSFETdegradation is due to the hot-
`carrier injection into the LDD spacer [4], the LDD spacer ma-
`terial influence on hot-carrier effects has not been investigated
`in detail.
`It has been previously reported that the dielectric constant of
`LDDspacer affects LDD MOSFETperformance [5]. In addi-
`tion, when the dielectric constant of LDD spacerincreases, the
`gate-fringing field becomes large. Therefore, because of this
`large gate-fringing field, high reliability and high current driv-
`ability can be realized in high dielectric LDD spacer MOS-
`FET’s (HLDD). However, with increasing the dielectric con-
`stant for an insulator,
`its bandgap energy decreases [6]. As a
`result,
`the barrier height for the high dielectric insulator de-
`creases, which causes a large hot-carrier injection into its LDD
`spacer. Therefore, it is important to form the large barrier height
`insulator such as SiO, under the high dielectric LDD spacer.
`in this paper, the authors discuss the influence of the sidewall
`SiO, thickness on the hot-carricr effects in Si,N, or SiO, LDD
`spacer structure [7], which can be explained by the luckey elec-
`tron model, and the LDD spacer oxide thickness is believed to
`play an important role in the MOSFETreliability. Moreover,
`we show relaxation phenomena of the MOSFET degradation
`after de stress test.
`
`(c)
`Fig. 1. Schematic cross sections of three different LDD spacer structures.
`(a) Si; N, on SiO, LDD spacer structure (ONLDD). (b) Only Si, N, film
`structure (NLDD). (c) Conventional SiO, LDD spacer (OLDD).
`
`TI]. EXPERIMENTAL PROCEDURE
`
`Three types of LDD spacer structures were fabricated as
`shown in Fig. 1: (a) an LPCVD-Si,N, film on thermal oxide
`(which is called the sidewall oxide) spacer (ONLDD), (b) an
`LPCVD-Si;N, film spacer (N-LDD), and (c) a conventional
`CVD-Si0, film on a thermal oxide spacer and an only CVD-
`SiO, film spacer (O-LDD). An n-channel LDD MOSFETwith
`the ONLDDstructure was fabricated by reactive ion etching of
`Q.2-um-thick deposited LPCVD-Si;N, on the sidewall oxide.
`In both the nitride and the oxide film LDD spacer structures,
`the sidewall oxide was formed by dry O, oxidation just atter
`forming the gate electrode and LDD n- region. Sidewall oxide
`thickness 7,, conditions at the Si surface were changed by dry
`QO, oxidation time and are 0, 15, and 25 nm. The ONLDD hot-
`carrier effects were investigated, comparing to those of the
`NLDDstructure (2.5-nm-thick native oxide) and the OLDD
`structure. LDD spacer width is about 0.2 sm. The gate poly-
`silicon length and the channel width are 0.8 and 10 pm, re-
`spectively. The p-well region and the LLD n™ region concen-
`tration are about 2
`xX
`10!7 cm™? and 5 x 10’ em™?,
`respectively. Gate oxide thickness T, is 15 nm.
`
`Manuscript received May 23, 1990; revised September 18, 1990. The
`review of this paper was arranged by Associate Editor R. B. Fair.
`T. Mizuno, S. Sawada, and T. Tanaka are with the Semiconductor De-
`vice Engineering Laboratory, Toshiba Corporation, 1, Komukai Toshiba-
`cho, Saiwai-ku, Kawasaki 210, Japan.
`Y. Saitoh is with Toshiba Microelectronics Corporation, 1, Komukai,
`Toshiba-cho, Saiwai-ku, Kawasaki 210, Japan.
`IEEE Log Number 9041427.
`
`0018-9383/9 1/0300-0584$01.00 © 1991 IEEE
`
`TSMC 1226
`
`TSMC 1226
`
`

`

`
`
`MIZUNO ef al.: HOT-CARRIER INJECTION SUPPRESSION
`
`585
`
`10.0
`
`Ala/Iq
`
`(Vg#6V, Vg=3V STRESS) T*300K
`_____—_e-__———*
`NLDD
`a
`Co
`OLDD-*0 Oe
`RO
`_-ONLOD
`QF
`
`(%) Oo
`
`10°
`
`103
`107
`10!
`STRESS TIME (SEC)
`Fig. 2. Drain current degradation rate at dc stress test
`V,=3V).
`
`104
`
`(V,; = 6 V,
`
`
`
`Alp/Ip(%)
`
`
`Vg =3V, Va=6¥ STRESS
`o
`eee
`
`AO
`
`10°
`
`.on
`
`Po
`
`®\
`
`_—oO
`
`ONLDD
`L poly 70.8 wm
`10°72
`1
`1
`1
`L
`io?
`ig!
`10°
`10!
`102
`103
`STRESS TIME (SEC}
`
`Fig. 3. Substrate current degradation rate at the same dcstress test as in
`Fig. 2.
`-
`
`
`100
`
`Vg + 3V, Vd=6V STRESS
`
`S—
`<= 10
`
`x +4
`
`1
`
`10°
`
`
`
`L
`\
`1
`10%
`10?
`io!
`STRESS TIME (SEC)
`
`104
`
`Fig. 4. Threshold voltage shift versus stress time at the same dcstress test
`as in Fig. 2.
`
`oxidation process and depend on the sidewall oxide as men-
`tioned above. This is considered to be dueto the reasonthat the
`gate to n” region overlap length is longer than that of the gate
`bird’s beak [17].
`The band diagram at the LDD spacer is shownin Fig. 5. It
`shows the schematic energy band diagram across the electric
`field from the drain n~ region to the gate electrode in ONLDD
`or NLDD. Thetrap level in Si;N, film is reported to be very
`shallow and be about 0.8 eV by Svensson et al. [9}. Therefore,
`the injected hot electron cannot be trapped in the nitride film or
`the trapped hot electron can be detrapped. Namely, the injected
`hot clectron can be trapped only in the oxide. Since the hot
`carrier is mainly injected into the LDD sidewall region and is
`trapped only in the LDD sidewall oxide, the V,, shift is caused
`by the trapped charge in the LDD sidewall oxide. In addition,
`since the injected hotcarrier is considered to be uniformly trap-
`ped in the LDD sidewall oxide, the V,, shift is condsidered to
`be proportional to the square of the LDD sidewall oxide thick-
`ness [10]. Therefore, V,, does not shift in the case of NLDD as
`shown in Fig. 4, because of its very thin sidewall oxide.
`2) Stress Time Dependence in the Nitride LDD Spacer
`Structure: Generally, Z, degradation rate is experimentally
`
`Drain current characteristics of LDD MOSFETsafter de
`stress test were measured at the drain and gate biases of 3.3 V
`in the reverse modeto the stress condition. The substrate bias
`is —1.5 V, in order to improve the subthreshold characteristics.
`The ONLDD and the OLDD data are mainly those with 25-
`nm-thick sidewall oxide.
`
`III. RESULTS AND DISCUSSION
`
`A, Drain-Current Degradation Phenomena
`
`1) DC Stress Test: Fig. 2 shows the drain-current degrada-
`tion rate AL, /I4 versus stress time ¢ at de stress test of V, = 6
`V, V, = 3 V. NLDDdata show the large degradation of the
`drain current at very small stress time. As LDD spacer oxide
`thickness becomesthick, such as ONLDD and OLDD, theini-
`tial drain current degradation becomes small. On the contrary,
`the stress time dependence of drain current degradation be-
`comes small when the LDD spacer oxide becomesthin, such as
`NLDD. Fig. 3 shows the substrate current reduction rate as a
`function of the stress time at the same dc stress conditions as in
`Fig. 2. The substrate current was measuredat the samedestress
`biases in the forward mode. It is also found that the stress time
`dependenceof the substrate-current shift is affected by the LDD
`spacer oxide thickness, and the substrate-current shift depen-
`dence on stress time in NLDD is about two magnitudes faster
`than the ONLDD data. The substrate current shift in NLDD
`starts at about 10 ms.
`On the other hand, in the case of an NLDD, when the LDD
`spacer oxide thickness is nearly equal to zero, V,, values are not
`changed at dc stress test, as shown in Fig. 4. However, Vy,
`shifts in the case of both ONLDD and OLDD. These phenom-
`ena can be explained by the following discussion.
`According to the discussion by Katto [8], trapped charges in
`the LDD spacer also cause the Vy, shift even in an LDD MOS-
`FET. Therefore, NLDD data shown in Figs. 2 and 4 indicate
`that in NLDD the injected hot electron does not get trapped and
`can generate only the interface state in NLDD sidewall struc-
`ture. This generated interface state is considered to cause the
`transconductance degradation in NLDD, resulting in the drain
`current shift in NLDD shownin Fig. 2.
`Weestimate the J, shift rate due to the only trapped charge.
`Since the drain current is proportional to (V, — V,,) in a short-
`channel MOSFET[14], the Z, shift rate due to the trapped charge
`can be expressed as follows:
`Ala _
`ly
`
`AVin
`&
`Ve — Vn
`
`(1)
`
`where Ad, and AV,, are the /, shift and V,,, shift, respectively.
`According to the V,, shift data at 1 h shown in Fig. 4, the ly
`shift rate for NLDD, ONLDD, and OLDD canbe calculated to
`be about 0%, 0.7%, and 0.7%, respectively. Since the /, shift
`for NLDD, ONLDD, and OLDDare about 4%, 3%, 1.5%,
`respectively, as.shown in Fig. 2, the trapped charge causes less
`than one half of the total /, shift. Therefore, it is found that the
`7, shift is mainly caused by the interface state generation.
`However, the OLDD data with 0 and 15-nm-thick sidewall
`oxide were almost the same as those at 7,, = 25 nm shownin
`Figs. 2 and 4. In the case of OLDD, sidewall! oxide thickness
`did not affect the hot-carrier effects. Namely, the gate bird’s
`beak does not affect hot-carrier effects in OLDD. Therefore, it
`is found that hot-carrier effects in both ONLDD and NLDDare
`not affected by the gate bird’s beak formed framthe sidewall
`
`

`

`
`
`586
`
`IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 38, NO 3, MARCH 1991
`
`10.0
`
`Alg/Ig(%
`
`102
`
`103
`
`SUBSTRATE CURRENT (pA)
`Fig. 6. Drain current degradation, as a function of the initial substrate cur-
`tent at the i-h de stress test (V, = 3 V, V, = 6 V) in various gate
`lengths.
`
`
`
`20
`
`1.0
`08
`e OG
`x 0.4
`
`3z
`
`02
`Vyt 6V STRESS
`
`L
`!
`On
`1o
`{oo
`SIDE-WALL Si0z THICKNESS(nm)
`Fig. 7. Index m in (2) versus the LDD spacer oxide thickness at the dc
`stress test (V, = 3 V, V, = 6 V). The solid lines show the T,, power law
`of index m.
`
`
`
`STRESS GATE BIAS (V)
`
`Fig. 8. Parameters § and my in (3) versus stress gate bias. Closed and open
`circles show 8 and mo, respectively.
`
`NLDD, in order to reduce the substrate current dependence of
`the index m.
`Next, according to Fig. 2, parameters A and q in (2) are de-
`pendent on the LDD spacer oxide thickness under the nitride
`film spacer. Moreover, as the LDD spacer oxide becomesthin,
`the initial degradation parameter 4 becomes large. On the con-
`trary, the stress time coefficient a becomes small. By fitting the
`I, shift data at various stress gate bias values to (2), we have
`determined the LDD spacer oxide thickness dependenceof pa-
`rameters A and a.
`Fig. 9 showsthe initial degradation parameter A as a function
`of T,,. According to Fig. 9, A is clearly proportional to the
`inverse of the power of 7... That is.
`
`A= ATS
`
`(5)
`
`where Ap and 6 are parameters.
`
`TRAP STATE
`
`A
`
`GATE
`
`~nN
`INTERFACE
`STATE
`
`
`
`
`SiO,
`
`Side
`Fig. 5. Schematic band diagramof the $i; N, /SiO, spacer structure across
`the electric field from the drain n~ region to the gate electrode. Interface
`states exist at both the Si;N,/SiO, and the SiO, /Si interfaces. Moreover,
`trap levels also exist in both the Si;N, and the SiO,films.
`
`given by the stress time power law as follows [11]:
`
`4a
`
`mM
`Al,
`afd = pat
`(2)
`r
`where J, is the substrate current and A, «, and m are parameters.
`Physical meaning of these parameters has not been clear, but
`these parameters are very important to predict the lifetime for
`the devices in the hot-carrier effects. Moreover, these parame-
`ters are obtained by fitting (2) to the data as shown in Fig. 2.
`This section discusses the LDD spacer oxide thickness de-
`pendence of parameters in (2) at the fixed stress drain bias of 6
`¥V. Morcover, it is shown that all parameters in (2) can be ex-
`pressed by a function of the sidewall oxide thickness. Since the
`LDDspaceroxide thickness is relatively small in this study and
`the dielectric constantfor the nitride film is not large, the gate-
`fringing field in both NLDD and ONLDD [5]is not affected by
`the LDD spacer oxide thickness and is notlarge.
`Index m in (2) is determined by changing the gate length.
`Fig. 6 shows the drain current degradation rate for a 1-h de
`stress test versus the substrate current at various gate lengths.
`It is clear that the Z, shift is proportional to the power of the
`substrate current. However,
`index m is changed by the LDD
`spacer oxide thickness. Fig. 7 shows index m versus LDD
`spacer oxide thickness. As shown in Fig. 7, m becomes small,
`when the LDD spacer oxide becomes thin. At V, = 3 V, pa-
`rameter m of the thicker sidewall oxide devices is about 1 and
`is almost the same as that of Kinugawaet al. (~0.9) [11]. In
`addition, index m is proportional to the power of the LDD spacer
`oxide thickness T,, as follows:
`
`m= Mo Tox
`
`(3)
`
`where mp and @ are parameters.
`If T,, becomes zero, the 1, shift does not depend on the sub-
`strate current. Therefore,
`the Z, shift in NLDD remains con-
`stant,
`in spite of an incrcase in the stress drain bias and the
`shrinking gate length.
`Fig. 8 shows the stress gate bias dependence for parameters
`my and 8 in (3). Accordingto Fig. 8, since 8 is about 0.5 at V,
`< 4 V, index m can be expressed as follows:
`
`m = mT®,
`
`(4)
`
`Since, in the case of V, > 4 V, my is constant at 0.3 and @
`decreases in V, > 4 V, T,, dependence of index m becomes
`small. This is due to the large hot-electron injection rate in large
`stress gate bias. As a result, at shorter channel length, it is im-
`portant
`to reduce the LDD spacer oxide thickness, such as
`
`

`

`MIZUNOet al.: HOT-CARRIER INJECTION SUPPRESSION
`
`587
`
`
`
`INDEX, 3
`
`Lpoly = 0.8 pm lo?
`
`
`102
`10!
`10°
`SIDE-WALL SiQz THICKNESS (nm)
`
`Fig. 11. Stress time coefficient a versus 7,,. Solid lines show the T,, power
`law of a.
`
`STRESS GATE BIAS (V)
`
`Fig. 12, Parameters n and ay in (6) versus stress gate bias. Closed and
`open circles show n and ao, respectively.
`
`Consequently, parameters m, A, and & in (2) strongly depend
`on LDD spacer oxide thickness. In addition, the initial degra-
`dation parameter dependence on the LDD spacer oxide thick-
`ness is opposite to the stress time coefficient dependence.
`Therefore,
`it
`is important to optimize the LDD spacer oxide
`thickness in orderto realize highly reliable LDD MOSFET’s.
`According to the above discussion, drain current shift equa-
`tion (1) can be expressed by the LDD spacer oxide thickness,
`in the case of the maximum substrate current de stress test con-
`ditions, as follows:
`
`Al, = protFox Ao potox
`I,
`Tox
`
`(7)
`
`Onthe other hand, it is clear that the dependenceofall pa-
`rameters in (2) on T,, becomes smaller at a larger stress gate
`bias. This is probably due to the high hot-carrier injection rate
`at larger stress gate bias conditions. In the case of other drain
`stress bias conditions, parameters in (2) can be also obtained by
`fitting data to (2), but parameters in (2) are considered to be
`different from the values in (7) because oftheir different hot-
`carrier injection rate.
`3) Stress Drain Bias Dependence: Fig. 13 showsthe stress
`drain bias dependence of the /, shift at the maximum substrate
`current de stress test for | h. In the case of NLDD, the /, shift
`does not increase and remains constant,
`in spite of increasing
`stress drain bias at V,; > 5 V. This is caused by the weak sub-
`strate current dependence and small stress time coefficient in
`NLDDas mentionedbefore.
`
`Moreover, the 7, shift of NLDD is observed in a small stress
`drain bias region of NLDD, compared to ONLDD data. This
`indicates that the interface state in NLDD can be generated by
`low-energy hot carriers. On the other hand, no /, shift
`in
`
`
`
`INITIALDEGRADATIONPARAMETER,A lol
`
`
`INDEX,8 0
`
`Va=6V STRESS
`
`o° LA.ont \ A & Tox?
`
`A\
`
`vg26¥
`
`lo?
`
`4
`
`100
`10
`SIDE-WALL SiOz THICKNESS (nm)
`
`woh
`
`103
`
`Fig. 9. Initial degradation parameter A versus the LDD spaceroxide thick-
`ness. Solid lines show the T,, power law of A.
`
`4
`2
`STRESS GATE BIAS (V)
`
`6
`
`Fig. 10. Parameters 6 and Ap in (5) versus stress gate bias. Closed and
`open circles show 6 and Ag, respectively.
`
`Fig. 10 shows parameters Ag and 6 as a function ofstress gate
`bias. By fitting data to (5), 6 is about 2 in Vi, < 4V, resulting
`in A « 1/T2,, as shownin Fig. 10. Asa result, the initial deg-
`radation parameter A becomeslarge in decreasing T,, by the
`1/T2, law. Moreover, Ag and 6 suddenly decreasein V. > 4
`Vv.
`
`Consequently, in order to reducethe initial degradation, it is
`necessary to thicken the LDD spacer oxide, such as OLDD
`structure.
`
`Finally, Fig. 11 shows the stress time coefficient a versus the
`LDDspacer oxide thickness T,,. In thicker sidewall oxide de-
`vices, a is about 0.2 andis almost the sameas that of Kinugawa
`et al, (~0.2) [11]. It is obvious that @ is proportional to the
`powerof T,,. Therefore, a can be expressed as follows:
`
`a= A Tox
`
`(6)
`
`where og and # are parameters.
`The stress time coefficient ~ becomes small with a decrease
`in T,, and becomeszero in the case of LDD structure without
`the oxide. This meansthat the Z, shift of a no-oxide LDD spacer
`becomesconstant, in spite of the increase of the stress time.
`By fitting data to (6),
`index
`in (6) is shown by the open
`circles in Fig. 12. Index n is a constant unity in V, < 4 V,
`resulting in a « T,,. However, n decreases varied from 1
`to
`0.2 in V, > 4 V. On the other hand, ap is almost constant at
`V, < 3 V, but increases at V, > 3 V.
`
`

`

`
`
`588
`
`IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 38, NO. 3, MARCH 1991
`
`
`
`10
`55
`Vg = Va = Vsup = OV
`~ VgetVa IN-STRESS—Lopoly=O8 nm
`Penna
`400K
`8
`6
`soft - ~~ BEESE==8 300K
`3
`E 6
`fad
`~
`> 4
`3
`
`RECOVERY TIME (xl074SEC)
`
`Fig. 14. Relaxation phenomenaof the drain currentshift rate to the initial
`current, after de stress test (V, = 3 V, V, = 6 V) for 5h. The relaxation
`bias conditionsare all terminal grounded in MOSFET’s.
`
`4
`
`STRESS
`CNLOO]
`
`kG
`p
`£ 3
`On
`2
`\
`S
`|
`7
`Ve
`~ 2r
`he
`{
`<q
`\ ||
`|
`4
`5
`TIME (xt04 SEC)
`Fig. 15. Drain current shift rate behavior, at and after de stress test, as a
`parameter of stress drain bias. DC stress test at t < 0 stops at t = 0 and
`the relaxation lest is carried out in# > 0. By the way, the result of NLDD
`around ¢ = 0 s is the data fort = ~—10s.
`
`O
`
`oO
`
`2
`
`(Lpoly 0.8m) oo*
`
`10
`
`3=
`
`3
`
`2~
`
`oO
`
`NLOD
`
`°
`
`9
`;
`
`é
`P/
`
`ost
`L o6f
`gfce
`na
`> O4F
`:
`& O02,
`Oo
`eos
`# oo
`10
`8
`6
`4
`2
`0
`STRESS DRAIN VOLTAGE (V)
`
`Fig. 16. Relaxationrate of J, shift versus stress drain bias at the maximum
`substrate current de stress test. Sidewall oxide thickness of ONLDDis 15
`nm in this figure. Relaxation rate is defined as the 7, shift rate after the
`relaxation test minus the maximum J,shift at the de stress test.
`
`Fig. 16 showsthe /, shift relaxation rate as a function of de
`stress drain bias at the maximum substrate current destress test.
`The 1, shift can recover, when the stress drain bias becomes
`larger than 5 V, and is not observed at a stress V,; < 5 V. In
`addition, the relaxation rate of the J, shift approaches a satu-
`rated value (about 1%) with increasing stress drain bias and
`
`Fig. 13. Drain current shift versus stress drain bias at the maximum sub-
`strate current de stress test for 1h.
`
`ONLDDis observed in small stress drain bias, which indicates
`that LDD spacer oxide suppresses the low-energy hot-carrier
`injection. However, stress drain bias dependence of the drain
`current shift becomes large in ONLDD and OLDD. Especially
`in OLDD, the drain current at 7 V stress drain bias becomes
`larger than that of NLDD, because of the former’s large stress
`time coefficient.
`Consequently, high reliability in the ONLDD structure can
`be realized by both the LDD spacer oxide suppression of hot-
`carrier injection and the gate-fringing field effects [5].
`
`B. L-Shift-Relaxation Phenomena in NLDD
`Generally, the J, shift in MOSFET does not recover after de
`Stress test. Here, Fig. 14 shows the reduced drain current re-
`laxation phenomenaafter 5-h de stress test (V, = 3 V, V, = 6
`V), where all terminals biases for MOSFET’s are 0 V. In
`NLDD, reduced drain current is recovered at room temperature.
`Morcover,its relaxation time constant 7 at room temperature is
`nearly equal to that at high temperature (400 K ). These results
`indicate that
`the activation energy for the interface state in
`NLDDis very small and is considered to be almost equal to the
`room temperature thermal energy, According to this small ac-
`tivation energy in NLDD, the interface state between Si, N, and
`the native oxide is considered to be generated by low-energy
`hot-carrier injection, which causes the large initial degradation
`parameter, shown in Fig. 9, and the 7, shift in low stress drain
`bias, shown in Fig. 13.
`On the contrary, in the OLDDstructure, reduced drain cur-
`rent does not recover, even at high temperature. According to
`these data, the time constant is very large in OLDD, which is
`considered ta be due to high activation energy of the SiO, /Si
`interface. Therefore, high activation energy in OLDD sup-
`presses the initial degradation parameter, compared to that in
`NLDD.
`Moreover, new recovery data for the 7, shift in NLDD are
`also shownin Fig. 15, which shows the /, shift phenomena as
`a parameter of de stress drain bias, at and after the dc stress
`test. In Fig. 15, the de stress test at f < Q stops att = Oanda
`relaxation test is carried out att > O. It has been recently found
`that reduced drain current docs not recover at all in low stress
`drain bias conditions. That is, at V, = 4 V stress test reduced
`drain current does not recoverat all, in spite of the same J, shift
`as that at V, = 6 V dc stress test. Moreover, according to Figs.
`14 and 15, reduced drain current cannot completely recover and
`its relaxation rate (which is defined by the /, shift rate after
`relaxation test minus the maximum J, shift at the dc stress test)
`is about 1%.
`
`
`
`oLoD /
`/
`/
`t
`o-——0—
`NLDD_” Ap
`c
`a
`
`/‘ L 07ONLOD
`
`1
`
`J
`|
`|
`6
`4
`2
`STRESS DRAIN VOLTAGE ty)
`
`2
`
`1
`
`8
`
`a
`
`%
`
`45
`
`
`
`Ala/Ig(%)
`
`
` 5
`ofONLDD
` LoL AFTER Vg=-Ve-STRESS
`
`

`

`
`
`MIZUNOet al.: HOT-CARRIER INJECTION SUPPRESSION
`
`589
`
`RELAXATIONOFIa(%)
`
`
`
`lo-4e
`
`ax 2
`
`AFTER DC STRESS
`
`a[
`
`-»9{-(seq)}]
`Lp=O0.8um
`
`io!
`
`lo*
`108
`102
`RELAXATION TIME (SEC)
`
`108
`
`Fig. 17. Recovery rate of 7, shift versus relaxation time in NLDD.
`
`10°
`
`/
`
`4
`
`|
`Vg "3Vd STRESS
`| —— :SigNq/SiO2
`— = $i02/Si
`7
`3 (0?)--— -HOT-HOLE
`Wwbl
`L
`
`°Ee
`qt
`J
`4G |St ONLDD
`oO
`(To, 2 Sn)
`
`
`
`“8
`0 Qo
`
`l
`8
`6
`4
`2
`STRESS DRAIN VOLTAGE (v)
`
`ou
`
`Fig. 18. Arbitrary interface state generation rate for Si,N,/SiO, and
`SiO, /Si interfaces. Solid lines and dotted and dashedlines show the cal-
`culated results of the Si; N,/SiO, and the SiO, /Si interfaces by hot-elec-
`tron injection, respectively. Dashed line shows the calculated results of the
`Si; N4/SiO, interface by the hot-hole injection.
`
`almost all hot-electrons can be injected into the Si;N,/SiO,
`interface by the tunneling mechanism. Therefore, the term exp
`(—T,,/%o) in (10) is nearly equal to unity in NLDD. More-
`aver, according to the data in Fig. 14, ¢,, in (10) is about the
`thermal energy at room temperature and can be expressed as
`follows:
`
`(11)
`
`bn = kT = 0.03 eV
`where k is the Boltzmann constant.
`On the other hand, the activation energy for SiO, /Si inter-
`face state 4,9 is considered to be muchlarger than 9;,,, according
`to OLDD data in Fig. 14. Therefore, in this study, Gio in (9) is
`adopted as the SiH bond energy 0.3 eV reported by Huet ai.
`[12]. As a result, the SiO, /Si interface state generation energy
`is ten times as large as that of the Si; N,/SiO,. Moreover, C;
`in (9) is assumed to be equal to C, in (10).
`Using (9) and (10), Fig. 18 shows the calculated Si; N, /SiOz
`interface state generation rate P,, in both NLDD and ONLDD
`with 15-nm-thick LDD spacer oxide. P,, in ONLDDis reduced
`to about five magnitudes smaller than that in NLDD. Moreover,
`P,, in ONLDD with 25-nm-thick LDD spacer oxide is also cal-
`culated by (10) and is about eight magnitudes smaller than
`NLDDdata, determined by the term exp (~T,,/Xo). So P,, in
`ONLDDwith a 25-nm-thick LDD spacer oxide is considered to
`
`there is a turning point at around V, = 5 V. On the other hand,
`even in the ONLDDstructure, the /, shift is also recovered at
`stress V, > 6 V in thinner LDD spacer SiO, (15 nm) structure.
`This result indicates that the Si,N,/SiO, interfacestate is also
`generated by higher energy hot-electron injection even in
`ONLDD. However,
`in a thicker LDD spacer oxide structure
`(25 nm), no J, shift relaxation was observed in this study.
`Next, the relationship between the /, shift relaxation rate and
`the relaxation time is shown. Fig. 17 shows the relaxation rate
`value versus the relaxation time. This relaxation rate R(t) can
`be expressed as the following function, by fitting the data:
`
`R(t) = nf — exp )
`
`(8)
`
`where r, is a constant and 7 is the time constant.
`The time constant 7 in NLDD is not affected by dc stress
`conditions and is about 3600 s (1 h). The physical meaning for
`this 7 value is not so clear, but it is probably considered to be
`a detrapping rate for the Si, N, /SiO, interface state.
`
`C. Hot-Carrier Injection Mechanism
`According to Section IJI-Ai,
`the drain current shift at the
`peak substrate current conditions is considered to be mainly
`caused by interface generation. This section discusses the hot-
`carrier mechanism in both NLDD and ONLDD, considering the
`interface generation rate by using the lucky electron model[12],
`in order to explain the /, shift versus the stress drain bias shown
`in Fig. 13.
`According to the discussion in the previous sections, there
`are two interface state generation regions in the ONLDDstruc-
`ture, such as the Si;N,/SiO, and the SiO,/Si interfaces, as
`shown in Fig. 5.
`Generally, interface state generation rate P can be given as
`follows [12]:
`
`_
`
`_ by + 9
`
`where C, is a constant, /, is the substrate current, A,is the elec-
`tron mean free path in the $i (7.5 nm) [14]. Z,,, is the maxi-
`mum lateral drain field, ¢, and @; are the barrier height and the
`generation energy for the interface state, respectively. In (9),
`experimental J, is used and E£,,,, is calculated by the 2D device
`simulator MOS2C [16].
`In the case of the ONLDD, the injected hot-carrierrate from
`the Si into the Si; N,/SiO, is reduced by the LDD spacer oxide,
`obeying the function exp (~T,,/Xo), where Ao is the electron
`mean free path in the SiO, film. Therefore, according to (9),
`the Si,N,/SiO, interface state generation rate P,, can be ex-
`pressed as follows:
`
`P, = Cyl, exp (-*) exp (-*2422)
`
`in
`+
`e max
`
`Tox
`‘0
`
`(10)
`
`where C, is constant, @q (3.2 eV) [12] and @,, are the barrier
`height of the SiO, /Si and the generation energy of the Si, Ny
`interface state, respectively. The barrier height of the Si; N, to
`the Si is 2.05 eV [13].
`Since,
`in the case of NLDD, the threshold voltage does not
`shift at the de stress test, shown in Fig. 4 and the LDD spacer
`oxide (natural oxide) thickness is almost the same as the elec-
`tron mean free path in SiO, (1.5 nm) [15], it ts considered that
`
`

`

`be negligibly small. Therefore, this low generation rate for the
`Si,;N, /SiO, interface state suppresses the /, shift in ONLDD at
`low stress drain bias, shown in Fig. 13, and the initial degra-
`dation parameter, shown in Fig. 9. However, Fig. 18 indicates
`that, even in ONLDD, the Si, N,/SiO, interface state can be
`generated with increasing stress drain bias. In addition, P,,
`in
`NLDDis almost the same as that in ONLDDatabout 4 V higher
`stress bias. This can be well explained by the 7, shift recovery
`difference between NLDD and ONLDD, that is, why the relax-
`ation rate for ONLDDis almost the same as that for NLDD at
`about 3.5 V lower stress drain bias, as shown in Fig. 16. Con-
`sequently, the LDD spacer oxide suppresses the hot-carrier in-
`jection into the Si; N,/SiO, interface
`The dashed line in Fig. 18 showsthe calculated SiO, /Si in-
`terface state generation rate Py for ONLDD, using (9). Com-
`pared to Py in ONLDD, it is found that P, in NLDD is much
`larger and is almost the same as Py in ONLDDat about 2 V
`higher stress bias, which can explain the difference between the
`1, shift dependence on the stress drain voltage for NLDD and
`ONLDD, as shown in Fig. 13. This high interface state gen-
`eration rate in NLDD causesthe large /, shift in low bias stress
`test and a large initial degradation parameter, compared to the
`ONLDDstructure.
`
`Onthe other hand, the barrier height of the hole injection is
`only 1.95 eV in NLDD [13] and is almost equal to that of the
`electron injection. Here, substituting the hole mean free path
`(5.5 nm) [14] into (9), P,, by hot-hole injection can be calcu-
`lated and is shown bythe dotted and dashed line in Fig. 18. P,
`by the hot-hole injection is about one tenth as large as P,, by the
`hot-electron injection, because of smaller mean free path of the
`hole, but is two magnitudes larger than the interface state gen-
`eration rate in ONLDD. This high hot-hole injection in NLDD
`is not physically understood in detail now, but it is considered
`that high hot-hole injections affects the large initial degradation
`parameter shown in Fig. 9, the large Z, shift in low bias stress
`test shown in Fig. 13, and the /, shift relaxation phenomena
`shownin Fig. 14.
`
`IV. CONCLUSION
`
`{1] S. Ogura, P. J. Tsang, W. W. Walker, D. J. Critchlow, and J.
`F. Shepard,
`‘‘Design and characteristics of the lightly doped
`drain-source (LDD) insulated gate field effect transistor,’’ JEEE
`Trans. Electron Devices, vol. ED-27, p. 1359, 1980.
`(2] F.-C. Hsu and K. Y. Chiu, ‘‘Effects of device processing on hot-
`carrier induced device degradation,’* in Symp. VLSI Tech Dig.,
`p. 108, 1985.
`[3] G. A. Sai-Halasz, M. R. Wordeman, D. P. Hern, E. Ganin, S.
`Rishton, H. Y. Ng, D. S. Zickerman, D. Mog, T. H. P. Chan,
`and R. H. Dennard, ‘‘Experimental technology and characteri-
`zation ofself-aligned 0. 1m-gate-length low-temperature opera-
`tion NMOSdevices,’’ in JEDM Tech. Dig., p. 397, 1987.
`[4] F.-C. Hsu and H. R. Grinolds, ‘*Structure-enhanced MOSFET
`degradation due to hot-carrier injection,’ IEEE Electron Device
`Lett., vol. EDL-5, p. 71, 1984.
`{5] T. Mizuno, T. Kobori, Y. Saitoh, S. Sawada, and T. Tanaka,
`‘‘High dielectric LDD spacer technology for high performance
`MOSFETusing gate-fringing ficld effects,’* in JEDM Tech. Dig.,
`p. 613, 1989.
`[6] P. J. Hanop and D. S. Campbell, Thin Solid Films, vol. 2, p.
`273, 1968.
`/
`and
`S. Sawada, Y. Saitoh,
`[7] T. Mizuno,
`S. Shinozaki,
`**Si, N, /SiO, spacer inducedhighreliability in LLDMOSFETand
`its simple degradation model,’’ in JEDM Tech. Dig., p. 234,
`1988.
`[8] H. Katto, K. Okuyama, S. Meguro, R. Nagai, and S. Ikeda, ‘*Hot
`carrier degradation modes and optimization of LDD MOS-
`FETS,” in JEDM Tech. Dig., p. 774, 1984.
`[9] C. Svensson and I. Lundstrom, ‘‘Trap-assisted charge injection
`in NMOSstructures,” J. Appl. Phys., vol. 44, p. 5675, 1973.
`[10} M. Yashida, D. Tohyama, K. Maeguchi, and K. Kanzaki, ‘‘In-
`crease of resistance to hot carriers in thin oxide MOSFETS,”’ in
`IEDM Tech. Dig., p. 254, 1985.
`(111 M. Kinugawa, M. Kakumu, S. Yokogawa, K. Hashimoto, and
`J. Mastunaga, ‘‘Submicron MLDD NMOSFETsfor 5V opera-
`tion,’’ in Symp. VLSI Tech. Dig., p. 116, 1985.
`[12] C. Hu, S. C. Tam, F.-C. Hsu, P.-K. Ko, T. Y. Chan, and K.
`W. Terrill,
`‘‘Hot-electron induced MOSFET degradation—
`Model, monitor, and improvement,’’ IEEE Trans. Electron De-
`vices, vol. ED-32, p. 375, 1985.
`[13] M. Aminzadeh, S. Nozaki, and R. V. Giridhar, ‘‘Conduction and
`charge trapping in polysilicon-silicon nitride-oxide-silicon struc-
`It is found that LDD spacerstructure influences hot-carrier
`tures under positive gate bias,’ JEEE Trans. Electron Devices,
`vol. 35, p. 459, 1988.
`effects. In the Si; Ny LDD spacer structure (NLDD), large hot-
`New York, NY:
`[14] S. M. Sze, Physics of Semiconductor Devices.
`electron and hole injection into the nitride LDD spacer cause
`Wiley, 1981.
`the large /, shift at low stress drain bias andalarge initial deg-
`[15]
`I. C. Chen, S. Holland, and C. Hu, ‘‘Oxide breakdown depen-
`radation parameter, compared to both ONLDD and OLDD, be-
`dence on thickness and hole-current-enhanced reliability of ultra
`cause of the small barrier height in the Si,N, film. Moreover,
`thin oxides,