(10) Patent No.:
`a2) United States Patent
`Tsutsui et al.
`(45) Date of Patent:
`
`
`US 7,893,501 B2
`*Feb. 22, 2011
`
`US007893501B2
`
`(54) SEMICONDUCTOR DEVICE INCLUDING
`MISFE
`WING INTERNAL STRESS FILM
`MRR Rn
`Inventors: Masafumi Tsutsui, Osaka (JP);
`Hiroyuki Umimoto, Hyogo(JP); Kaori
`Akamatsu, Osaka(JP)
`
`(75)
`
`(56)
`
`(73) Assignee: Panasonic Corporation, Osaka (JP)
`(*) Notice:
`Subject to any disclaimer, the termofthis
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`IP
`
`This patent is subject to a terminal dis-
`claimer.
`
`References Cited
`U.S. PATENT DOCUMENTS
`6/1991 Tatsuta
`5,023,676 A
`
`(Continued)
`
`FOREIGN PATENT DOCUMENTS
`§2-120776
`10/1977
`
`(Continued)
`OTHER PUBLICATIONS
`
`(21) Appl. No.: 12/170,191
`
`(22)
`
`Filed:
`
`Jul. 9, 2008
`
`(65)
`
`Prior Publication Data
`
`US 2009/0050981 Al
`
`Feb. 26, 2009
`
`Related U.S. Application Data
`(63) Continuation of application No. 11/730,988, filed on
`Apr. 5, 2007, now Pat. No. 7,417,289, whichis a con-
`tinuation of application No, 10/859,219, filed on Jun.
`3, 2004, nowPat, No. 7,205,615.
`
`Foreign Application Priority Data
`(0)
`Jun, 16,2003
`(IP)
`ceeseecsssesevsreesevevereeee 2003-170335
`
`(51)
`
`Int. CL
`HOLL 29/76
`(2006.01)
`HOIL 29/494
`(2006.01)
`HOIL 31/062
`(2006.01)
`TOIL 31/113
`(2006.01)
`HOIL 31/119
`(2006.01)
`cuene 257/369
`(52): USiCh, ssscouscais
`(58) Field of ClassificationSeaich
`vevsene 297/369
`See applicationfile for completesearch history.
`
`Shimizu, A., et al., “Local Mechanical-Stress Comtrol (LMC): A
`New Technique for CMOS_Performance Enhancement’, 2001,
`IEDM 01, p. 19.4.1-19.4.4.
`
`(Continued)
`
`Primary Examiner—Howard Weiss
`(74) Attorney, Agent, or Firm—McDermott Will & Emery
`il
`(57)
`
`ABSTRACT
`
`A semiconductor device includes a first-type internal stress
`film formed ofa silicon oxide film over source/drain regions
`ofan nMISFETand a second-type internalstress film formed
`ofa TEOSfilm over source/drain regions ofa pMISFRT.Ina
`channel region ofthe nMISFE, a tensile stress is generated
`in the direction ofmovementofelectrons dueto thefirst-type
`internal stress film, so that
`the mobility of electrons is
`increased. Ina channel region ofthe pMISFET, a compressive
`stress is generated in the direction of movementofholes due
`to the second-type internalstress film, so that the mobility of
`holes is increased.
`25 Claims, 9 Drawing Sheets
`
`IPR2017-01843
`
`
`
`IP Bridge Exhibit 2211
`IP Bridge Exhibit 2211
`TSMC v. Godo Kaisha IP Bridge 1
`TSMCv. Godo Kaisha IP Bridge 1
`IPR2017-01843
`
`

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`US 7,893,501 B2
`Page 2
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`U.S. PATENT DOCUMENTS
`
`6,437,404
`6,573,172
`6,870,230
`6,977,194
`6,982,465
`7,022,561
`7,205,615
`7,417,289
`2003/0040158
`2004/0075148
`
`BI*
`Bl
`B2*
`B2
`B2
`B2
`B2*
`B2*
`Al
`Al
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`8/2002
`6/2003
`3/2005
`12/2005
`L/2006
`4/2006
`4/2007
`8/2008
`2/2003
`4/2004
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`Miangetal. ww... 257/347
`En etal.
`Matsuda etal.
`
`...........0 257/365
`
`Belyansky etal.
`Kumagaiet al.
`Huanget al.
`Tsutsui et al.
`Tsutsui ct al.
`Saitoh
`
`...ccceeere 257/369
`...cccceere 257/969
`
`Kumagaiet al.
`
`9/2005 Chanet al.
`2005/0194596 Al
`FOREIGN PATENT DOCUMENTS
`60-236209
`11/1985
`01-042840 A
`2/1989
`2003-086708
`3/2003
`2004-193 166
`7/2004
`
`JP
`JP
`JP
`JP
`
`OTHER PUBLICATIONS
`
`Japanese Office Action, with English translation,issued in Japanese
`Patent Application No. 2003-170335, mailed Dec. 22, 2009,
`Japanese Office Action, with English translation, issued in Japanese
`Patent Application No, 2003-170335, mailed Mar, 23, 2010.
`* cited by examiner
`
`

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`U.S. Patent
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`Feb. 22, 2011
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`Sheet 1 of 9
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`US 7,893,501 B2
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`rLe, J
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`U.S. Patent
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`Feb. 22, 2011
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`Sheet 2 of 9
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`US 7,893,501 B2
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` FIG. 2A en es
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`U.S. Patent
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`Feb. 22, 2011
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`Sheet 3 of 9
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`US 7,893,501 B2
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`FIG. 3A
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`U.S. Patent
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`Feb. 22, 2011
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`Sheet 4 of 9
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`US 7,893,501 B2
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`U.S. Patent
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`Feb. 22, 2011
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`Sheet 5 of 9
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`US 7,893,501 B2
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`FIG. 5A
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`U.S. Patent
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`Feb. 22, 2011
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`Sheet6 of 9
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`US7,893,501 B2
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`U.S. Patent
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`Feb.22, 2011
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`Sheet 7 of 9
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`US 7,893,501 B2
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`FIG. 7A
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`U.S. Patent
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`Feb. 22, 2011
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`Sheet 8 of 9
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`US 7,893,501 B2
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`

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`U.S. Patent
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`Feb. 22, 2011
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`Sheet 9 of 9
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`US7,893,501 B2
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`US 7,893,501 B2
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`1
`SEMICONDUCTOR DEVICE INCLUDING
`MISFET HAVING INTERNAL STRESS FILM
`
`RELATED APPLICATIONS
`
`This application is a Continuation of U.S. application Ser.
`No. 11/730,988,filed Apr. 5, 2007, now U.S. Pat. No. 7,417,
`289, which is a Continuation of U.S. application Ser. No.
`10/859,219,filed Jun. 3, 2004, now U.S. Pat. No. 7,205,615,
`and claiming priority of Japanese Application No. 2003-
`170335, filed Jun. 16, 2003, the entire contents of each of
`which are hereby incorporated by reference.
`
`BACKGROUND OF THE INVENTION
`
`2
`The internal stress film is capable of covering one or both
`ofsource/drain regions. In an nMISFET, the internal stress
`film generates a tensile stress substantially in the parallel
`direction to a gate length direction in a channelregion (i.e.,
`the direction of movement of electrons). In a pMISFET, the
`internal stress film generates a compressive stress substan-
`tially in the parallel direction to a gate length direction in a
`channelregion (i.e., the direction of movementofholes).
`Covering bothside surfaces or both side and upper surfaces
`of a gate electrode, the internal stress film can generate a
`stress im the longitudinal direction of the channel region
`through the gate electrode,thereby increasing the mobility of
`carriers.
`
`The present invention relates to a semiconductor device
`including an MISFET and a method for fabricating the same,
`and more particularly relates to a measure for increasing the
`mobility of carriers.
`Whena stress is generated ina semiconductorcrystal layer,
`a crystal-lattice constant varices and a band structure is
`changed, so that the mobility of carriers is changed. This
`phenomenonhas been knownasthe “piezoresistivity effect”.
`Whether the carrier mobility is increased or reduced differs
`depending on the plane direction ofa substrate, the direction
`in Which carriers move, and whether the stress is a tensile
`stress or a compressive stress. For example, in an Si (100)
`substrate,i.e.. a silicon substrate of which the principal sur-
`face is the {100} plane, assumethat carriers move in the [011]
`direction. When carriers are electrons, with a tensile stress
`generated in the direction in which electrons in a channel
`region move, the mobility of the carriers is increased. On the
`other hand, whencarriers are holes, with a compressive stress
`generated in the direction in which holes in a channel region
`move, the mobility of the carriers is increased, The increase ~
`rate of carrier mobility is proportional to the size of a stress.
`In this connection, conventionally, there have been propos-
`als for increasing carrier mobility by applying a stress to a
`semiconductor crystal layerto increase the operation speed of
`transistors andthe like. For example, in Reference 1, an entire
`semiconductor substrate is bent using an external device,
`thereby generating a stress in an active region ofa lransistor.
`
`SUMMARY OF THE INVENTION
`
`Moreover, covering a side surface ofthe gate electrode and
`an upper surface of the semiconductor substrate in two
`regions of the substrate sandwiching part of the gate elec-
`trode, whether the MISFET is an nMISFETor a pMISFET,
`the internalstress film can generate a tensile stress substan-
`tially in the parallel directionto the gate width direction ofthe
`MISFET,thereby increasing the mobility of carriers.
`A first method for fabricating a semiconductor device
`according to the present invention is a method in which an
`nMISFETand a pMISFETare formedin first and sccond
`5 active regions of a semiconductor substrate, respectively, and
`thenfirst and second internal stress films which cover source/
`drain regions ofthe nMISFETandsource/drain regions ofthe
`pMISFET,respectively, and generate a tensile stress and a
`compressive stress, respectively, substantially in the parallel
`directions to respective gate length directions ofthe channel
`regions are formed.
`According to this method, a CMOSdevice of which the
`operation speed is increased can be obtained.
`A second method for fabricating a semiconductor device
`according to the present invention is a method in which an
`internal stress film is formed first, a groove is formed inthe
`internal stress film, a gate insulating film and a buried gate
`electrode are formed inthe groove,and thentheinternal stress
`film is removed.
`
`According to this method, a stress which increases the
`mobility of carriers in the channel region can be generated
`using a remaining stress in the gate insulating film.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`in the above-described known structure, an
`However,
`external device is needed in addition to a semiconductor
`substrate and a stress can be generated only in the same
`direction in an entire region of the semiconductor substrate in
`whichactive regions ofa transistor andthe like are provided
`and which is located in the principal surface side. For
`example, when an Si (100) substrate is used, neither the
`mobility of clectrons nor the mobility of holes can be
`increased.
`
`It is therefore an object ofthe present inventionto provide,
`by generating a stress which increases the mobility ofcarriers
`in a semiconductor layer without using an external device, a
`semiconductor device including a pMISFET and an nMIS-
`FET ofwhichrespective operation speeds are increased and a
`method for fabricating the same.
`Asemiconductor device according to the present invention
`includes an internalstressfilmfor generating a stress ina gate
`length direction in a channel region of an active region in
`which a MISFETis formed.
`
`‘Thus, the mobility of carriers in the MISFE! can be
`increased by using the piezo resislivily effect.
`
`FIG. 1 is a cross-sectional view illustrating a semiconduc-
`tor device according to a first embodiment of the present
`invention.
`
`FIG, 2A through 2C are cross-sectional viewsillustrating
`first half of respective steps for fabricating the semiconductor
`device of the first embodiment.
`
`FIG. 3A through 3C are cross-sectional viewsillustrating
`latter halfofrespective steps for fabricating the semiconduc-
`tor device of the first embodiment.
`
`FIGS.4A through 4C are cross-sectional viewsillustrating,
`first, second and third modified cxamples ofthefirst cmbodi-
`ment.
`
`60
`
`FIGS. 5A through 5D are cross-sectional viewsillustrating
`respective steps for fabricating a semiconductor device
`according to thefirst modified example of the first embodi-
`ment.
`
`FIGS. 6A through 6C are cross-sectional viewsillustrating,
`respective steps for
`fabricaling a semiconductor device
`according to the third modified example of the first embodi-
`ment,
`
`

`

`US 7,893,501 B2
`
`3
`FIGS. 7A through 7D are cross-sectional viewsillustrating
`first half of respective steps for fabricating a semiconductor
`device according to a second embodiment of the present
`invention.
`FIGS. 8A through8Dare cross-sectional viewsillustrating,
`latter half of respective steps for fabricating the semiconduc-
`tor device of the second embodiment.
`
`FIGS. 9A and 9B are a plane view of an MISIET ofa
`semiconductor device according to a third embodiment ofthe
`present invention and a cross-sectional view illustrating a
`cross-sectional structure taken along the line IX-IX (a cross
`section im the gate width direction), respectively.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`First Embodiment
`
`5
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`5
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`23
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`at
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`film interposed therebetween,a stress is generatedinthe film
`itself. As for stress, there are tensile stress and compressive
`stress. In this embodiment and other embodiments, an inter-
`nal stress film in whicha tensile stress is generated substan-
`tially in the parallel directionto the direction in whichcarriers
`move(i.e., the gate length direction) in a channel regionofan
`MISFETis referred to as a “first-type internalstress film” and
`an internal stress film in which a compressive stress is gen-
`erated substantially in the parallel directionto the direction in
`whichcarriers move (the gate length direction) in a channel
`region of an MISFETisreferred to as a “second-typeinternal
`stress film”.
`Herein, the semiconductor substrate 1 is an Si substrate of
`whichthe principal surface is the {100} plane and is referred
`to as an Si (100) substrate for convenience. However, the
`{100} planeis a general name for the (+100)plane,the (0410)
`plane and the (00+1) plane,and therefore, even a plane which
`is not exactly the {100} plane andis tilted from the {100}
`plane by a less angle than 10 degree is considered to be
`substantially the {100} plane. Moreover,in this embodiment,
`the direction in whichelectrons move in the nMISFET and
`the direction in which holes move in the pMISFET (.e., the
`gate lengthdirection ofeach MISFET)is the [011] direction.
`However, in this embodiment, the “[011] direction on the
`principal surface ofanSi (100) substrate” includes equivalent
`directionsto the [011] direction, such as the [01-1] direction,
`the [0-11] direction, and the [0-1-1] direction,ie., directions
`within the range of the <011> direction. That
`is, even a
`direction whichis not exactly the [011] directionandtilted
`from the <011> direction by a less angle than 10 degreeis
`considered to be substantially the [011] direction.
`According to this embodiment,the following effects can be
`obtained.
`In the nMISFET,whenthefirst-type internalstressfilm 8a
`is broughtinto a direct contact with a semiconductor layer or
`made to facea semiconductor layer witha thin film interposed
`therebetween, a stress for compressing, thefirst-type internal
`stress film itself, i.e., a compressive stress is generated in the
`first-type internal stress film 8a. As a result, by the first-type
`internalstress film 8a, the semiconductorlayer adjacent to the
`first-type internalstress film 8a can be stretchedin the vertical
`direction lo a boundary surface. Specifically, the first-lype
`internal stress film 8a applies a compressive stress to the
`source region 3a and the drain region 4a inthe active region
`la of the nMISFETin the parallel direction to the principal
`surface. Asa result, a tensile stress 1s applied to a region of the
`substrate located betweenthe source region 3a and the drain
`regionda, i.e., the channelregion 1y in the gate length direc-
`tion (the direction in which electrons move whenthe nMIS-
`FETis in an operation state). Then, with this tensile stress,
`electrons are influenced by the piezo resistivity effect, so that
`the mobility of electrons is increased. [lerein, “substantially
`in the parallel direction”also meansina directiontilted by an
`angle of less than 10 degree from the direction in which
`5 electrons move.
`For example, assume that the substrate 1 is an Si (100)
`substrate and the direction in which electrons move is the
`[011] direction. When the internal stress of the first-type
`internal stress film 8a adjacent to the semiconductor layer is
`a general level for a silicon nitride film, i.c., 1.5 GPa, the
`thicknessofthe firsi-type internal stress film 8a is 20 nm, a
`space between respective parts ofthe source and drainregions
`3a and 4a being in contact with the first-iype internal stress
`film 8a,i.e., the length ofthe channel region 1y, is 0.2 pm.a
`tensile stress in the gate length direction generated ala depth
`of 10 nm fromthesurface ofthe substrate is 0.3 GPa (J. Appl.
`Phys., vol. 38-7, p. 2913, 1967) and the improvementrate of
`
`FIG. 1 is a cross-sectional view illustrating a semiconduc-
`tor device according to a first embodiment of the present
`invention. As shownin FIG. 1, a surface region of a semicon-
`ductor substrate 1. i.2., an $i (100) substrate is divided into a
`plurality ofactive regions 1a and 16 byanisolation region 2.
`The semiconductor device includes an nMISFET formation
`region Rn whichincludes the active region 1a and in which an
`nMISFET is to be formed and a pMISFET formation region
`Rp whichincludesthe active region 16 and in which a pMIS-
`FRT is to be formed.
`The nMISFETincludes n-type source/drain regions 3a and
`4a each of which includes an n-type lightly doped impurily
`region, an. n-type heavily doped impurity region and a silicide
`layer suchas a CoSi, layer, a gate insulating film 5 formed on
`the active region 1a and madeofa siliconoxide film, a silicon
`oxynitride filmor the like, a gate electrode 6a formed on the
`35
`gate insulating film 5 and made ofpolysilicon, aluminum or
`the like, and a sidewall 7 covering a side surface of the gate *:
`electrode 6a and madeofan insulatingfilm. Part ofthe active
`region la located underthe gate electrode 6a is a channel
`region Lx in which electrons move(travel) when the nMIS-
`FETis in an operationstate.
`The pMISFETincludesp-type source/drain regions 35 and
`46 each of which includes a p-type lightly doped impurity
`region, a p-type heavily doped impurity region and a silicide
`layer such as a CoSi, layer, a gate insulating film 5 formed on
`the active region 1b and made ofa silicon oxidefilm, a silicon
`oxynitride filmorthe like, a gate electrode 64 formed on the
`gate insulating film 5 and made of polysilicon, aluminum or
`the like, and a sidewall 7 covering a side surface of the gate
`electrode 6b and made ofaninsulatingfilm. Part ofthe active
`region 14 located under the gate electrode 66 is a channel
`region Ly in which holes move(travel) when the pMISFFTis
`in an operationstate.
`Moreover, providedarea first-type internal stress film 8a
`formed on the source/drain regions 3@ and 4a ofthe nMIS-
`FET, madeofa siliconnitride film or the like, and having a
`thickness ofabout 20 nm, a second-type internalstressfilm 8b
`formed on the source/drain regions 34 and 44 of the pMIS-
`FET, made ofa‘lEOS filmorthelike, and having a thickness
`of aboul 20 nm, an interlevel insulating film 9 covering the
`nMISFET and pMISFET and having a surface flattened, a
`lead electrode 10 formed onthe interlevel insulating film 9,
`and a contact 11 connecting each of the source/drain regions
`3a, 3b, 4a and 4b with the lead electrode 10 through the
`interlevel insulating film 9.
`Herein, an “internal stress film” is a film characterized in
`that where the internalstress film is directly in contact with
`some olher memberor Jaces some other member with a thin
`
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`US 7,893,501 B2
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`In general, in any substrate plane directions, there 1s a direc-
`the mobility of electrons is +10% (Phys. Rev., vol. 94, p. 42,
`tion of movementofelectronsor holes, which allows increase
`1954). To obtain a larger change in the mobility thanthis, the
`tensile stress of a semiconductor can be increased. Thus, a
`in the mobility of electrons or holes accordingto the direction
`ofa stress.
`film having a large internal stress can be used as thefirst-type
`In this embodiment, the internal stress films 8a and 84 exist
`internal stress film 8a, the thickness ofthefirst-type internal
`on the source/drain regions 3@ and 4a and the source/drain
`stress film 8a canbe increased, or the space between the parts
`ofthe source anddrain regions 3a and4a being in contact with
`regions 35 and 44, respectively. However, even when the
`internal stress film 8a exists only on one of the source/drain
`the first-type internal stress film 8a, i.e.. the length of the
`regions 3a and 4a andthe internalstressfilm 84 exists only on
`channel region Lv, can be reduced for a larger change in the
`one of the source/drain regions 3b and 4, the effect of
`mobility. For example, when the thickness of the first-type
`increasing the mobility of carriers can be obtained. Inthis
`internal stress film 8a is doubled, the space betweenthe parts
`case, the improvementrate of the mobility is reducedto half.
`ofthe source and drain regions 3a and 4q@ being in contact with
`In eachof the following embodiments, when an internal stress
`the first-type internal stress film 8a, i.e., the length of the
`channel region Ly is reducedto half, the improvementrate of
`film exits only on one of source/drain regions, the improve-
`5 ment rate of the mobility is reduced to half, compared to the
`the mobility of electrons is +40%. As another way to obtain a
`large mobility,
`the direction in which electrons move is
`case where internal stress films exist on source/drainregions,
`but the mobility is increased.
`changed from the [011] direction to the [010] direction to
`FIGS.2A through 2C and FIGS. 3A through 3C are cross-
`change the improvementrate ofthe mobility ofelectrons with
`respect lo a lensile stress. As a result, with the same lensile
`secional views illustrating respective steps for fabricating a
`semiconductor device according to the first embodiment of
`stress, the improvementrate ofthe mobility becomes about
`the present invention.
`3.5 times large. Although the source and drain regions 3a and
`First, in the process step of 1G. 2.4,a trench and a buried
`da receive compressive stresses by the first-type internal
`oxide filmare formed inpart of a semiconductor substrate 1,
`stress film 8a, influence ofthe piezo resistivity effect is small
`i.€.,
`an. $i (100) substrate, thereby forming anisolation region
`because a low-resistant heavily doped semiconductor device
`23
`andasilicide film are used. Moreover, influence ofthe inter-
`2 for dividing the substrate into active regions la, 14 and so.
`on. Thereafter, after a gate insulatingfilm 5 has been formed
`nal stress of the interlevel insulating film 9 on the channel
`region can be neglected. This is because with the substrate
`by thermal oxidation of respective surfaces of the active
`regions la and 16 and a polysilicon film for forming gate
`covered bytheinterlevel insulating film 9, internalstresses in
`the interlevel insulating film 9 are cancelled off with each
`electrodes has been deposited, the polysiliconfilm and the
`other, so that the function of applying stress to the active
`gate insulating film 5 are etched by patterning using lithog-
`regions la and 14 is small.
`raphy and anisotropic dry etching, thereby forming gate elec-
`In the pMISFET, when the second-typeinternalstress film
`trodes 6a and 6b. The gate length direction ofeach ofthe gate
`electrodes 6a and 66 is the [011] direction, Next, using the
`85 is brought into a direct contact with the semiconductor
`gate electrode 6a of the nMISFETasa mask,ion implantation
`layer or made to face a semiconductorlayer witha thin film
`interposed thercbctween, a stress for stretching the second-
`of an n-tvpe impurity (¢c.g,, arsenic) at a low concentrationis
`performed to an nMISFET formation region Rn at aninjec-
`type internalstress filmitself,i.¢., a tensile stress is generated
`tion energy of 10 keV anda dose of 1x10'*/cm?, and using the
`in the second-type internal stress film 8). As a result, by the
`second-type internal stress film 84, the semiconductor layer
`gate electrode 65 of the pMISFETasa mask, ion implantation
`adjacent to the second-type internal stress film 85 is com-
`of a p-type impurity (e.g., boron) at a low concentrationis
`pressed in the vertical direction to a boundary surface. Spe-
`performed to apMISFET formation region Rp at an injection
`energy of 2 keV and a dose of 1x10'°/cm?*. Thereatier, an
`cifically, the second-type internal stress film 8b applies a
`insulating film which is for forming a sidewall and bas a
`tensile stress (o the source region 36 and the drain region 46 in
`the active region 16 of the pMISFET inthe parallel direction
`thickness of about 50 nm is deposited on the substrate and
`then a sidewall 7 is formed on side surfaces of the gate
`to the principal surface. As a result, a compressive stress is
`applied to aregionofthe substrate located between the source
`electrodes 6a and 6b by etch back. Next, using the gate
`electrode 6a of the nMISFET and the sidewall 7 as masks, ion
`region 3and the drain region44,i.e., the channel region Ly
`substantially in the parallel direction to the gate length direc-
`implantation of an n-type impurity (e.g., arsenic) at a high
`tion (the direction in which holes move when the pMISFETis
`concentrationis performed to thenMISFET formation region
`Rnataninjection energy of20 keVand a dose of|x10'*/em?,
`in an operation state). Then, with this compressive stress,
`holes are influenced by the piezo resistivity effect, so that the
`and ion implantation of a p-type impurity (e.g., boron) at a
`mobility ofholes is increased. Herein, “substantially in the -
`high concentration is performed to the pMISFET formation
`parallel direction” also meansin a directiontilted by an angle
`region Rp at an injection energy of 5 keV and a dose of
`1x10'°/cm*. Thereafter, thermal treatment (RTA)for activat-
`ofless than 10 degree from the direction in whichelectrons
`move.
`ing impurities is performed. By the above-described process-
`ing, source/drain regions 3¢ and da including an n-type
`lightly doped impurity region and an n-type heavily doped
`impurity region are formed in the nMISFET formation region
`Rn and source/drain regions 3b and 44 including a p-type
`lightly doped impurity region and a p-type heavily doped
`impurity region are formed in the pMISFETformation region
`Rp.
`Next, in the process step ofFIG. 2B, a silicon nitride film 8x
`is formed on the substrate sothat the silicon nitride [ilm 8x has
`a relatively large thickness and a surfacethereofis flatted. At
`this point of time, the silicon nitride film &x covers respective
`upper surtaces of the gate electrodes 6a and 64 of the MIS-
`PETs. Thereafter, a resist film 12 is formed onthesilicon
`
`Notethat, insteadofthe internal stress films 8a and 84,the
`semiconductor film itself in which the source and drain
`regions 3a, 4a, 35 and 44 are formed may bea film having an
`internal stress, for example, an uppermost semiconductor
`~~ layer in an SOT substrate.
`Furthermore, cach ofthe internal stress films 8a and 85
`does not have to be a single layer but may include multiple
`layers, as long as each of the internal stress films 8a and 84
`can apply a stress to the substrate as a whole.
`ieee,
`Moreover.
`in this embodiment, an Si (100) substrate is
`used. However, even ifan Si (111) substrate is used, with the
`direction in which electrons moveset to be the |001| direc-
`tion, the mobility ofelectronsis increased bya tensile stress.
`
`fi wa
`
`ey
`
`

`

`US 7,893,501 B2
`
`’
`7
`nitride film 8x by lithography and the silicon nitride film8xis
`patterned using theresist film 12 as a mask so that the silicon
`nitride film8y is left only on the nMISFET formation region
`Rn.
`Next, in the process step of FIG. 2C,after the resistfilm 12
`has been removed, thesiliconnitridefilm 8xis etched back,
`part ofthe siliconnitride film 8xlocated on the gate electrode
`6a is removed and the thicknessof the silicon nitride film 8x
`is further reduced. Thus, a first-type internal stress film8a is
`formed. Thatis, the first-type internal stress film 8a does not
`exist on the gate electrode 6a of the nMISFETbutexits only
`onthe source/drain regions 3a and 4a.
`Next, in the process step of FIG. 3A, a TEOSfilm 8}is
`formed on the substrate so that the TEOS film 8) has a
`relatively large thickness and a surface thereofis flatted. At
`this point oftime, the TEOSfilm 8) covers respective upper
`surfaces of the gate electrodes 6a and 64 of the MISFETs.
`Thereatter, a resist film (not shown) is formed on the TEOS
`film 8y by lithography and the TEOS film 8y is patterned
`using the resist film as a mask so that the TEOSfilm 8} is left
`only on the pMISFETformation region Rp.
`Next, in the processstep of FIG, 38,after the resist film has
`been removed, the TEOSfilm 8yis etched back, parts of the
`TEOSfilm 8y located on the gate electrodes 6a and 66 are
`removed and the thickness of the TEOS film 8y is further
`reduced, Thus, a second-type internal stress film 85 having
`substantially the same thicknessas that ofthe first-type inter-
`nal stress film 8a is formed. That is, the second-type internal
`stress film 8 does not exist on the gate electrode 6b of the
`pMISFET andthe first-type internal stress film 8a but exists
`only on the source/drain regions 36 and 46.
`By the above-described process steps, the internal stress
`films 8a and 84 for applying stresses in opposite directions to
`each other are formed onthe source/drain regions 3a and 4a
`ofthenMISFETandthe source/drain regions 3b and 44 ofthe
`pMISFET,respectively.
`Next, in the process step of FIG. 3C, on the substrate, an
`interleve] insulating film 9 is formed and then contact holes
`are formed so as to pass throughthe interlevel insulating film
`9 and reachthe source/drain regions 3a and 4a of the nMIS-
`FET by lithography and dry etching, the source/drain regions
`36 and 44, and the gale electrodes 6a and 64, respectively.
`‘Lhereatier, each of the contact holesis filled with metal (e.g.,
`tungsten), thereby forming contact pluys 11. Furthermore, a
`metal film such as an aluminumalloy film is deposited on the
`interlevel insulating film 9 and then the metal filmis pat-
`terned, thereby forming a lead electrode 10 connectedto each
`of the contact plugs 11. Thus, the respective source/drain
`regions 3a, 4a, 35 and 4b of the MISFETs and the gate
`electrodes 6a and 6b are madeto beelectrically connectable
`from the outside.
`In the fabrication method ofthis embodiment, cither one of
`the two types ofinternalstress films 8a and 8b may be formed
`first. And the internal stress films 8a and 8b may overlap with
`each other over the isolation region 2 and the source/drain
`regions 3a, 4a, 36 and 44.
`
`First Modified Example of First Embodiment
`
`FIGS. 4A through 4C are cross-sectional viewsillustrating
`first through third modified examples of thefirst embodiment.
`A semiconductor device according to a first modified
`example shown in FIG. 4A has a structure in which the
`sidewall 7 ofthe first embodimentis omitted. Moreover, each
`of the source/drain regions 3a, da, 34 and 44 does not include
`a lightly doped impurity region and includes only a heavily
`doped impurily region, Other part has the samestructure as
`
`.
`
`)
`
`30
`
`°
`
`At)
`
`50
`
`55
`
`60
`
`8
`that of the semiconductor device ofthe first embodiment. In
`this modified example, no sidewall exists in forming an inter-
`nal stress film, so that a space betweenrespective parts of the
`source/drain regions 3a and 4a being in contact with the
`first-type internal stress film8a is small. Thus, a stress applied
`to eachof the channel regions Lx and 1) is increased, so that
`the effect of improving the carrier mobility hecomes larger
`than that ofthe first embodiment.
`
`A semiconductor device according to a second modified
`example showninFIG,4Bhasa structure inwhichinstead of
`the sidewall 70:ofthefirst embodiment, which is made of a
`“siliconoxidefilm,the first-type internalstress film 8a made of
`a silicon nitridefilm coversasidesurfaceofthe pateelectrode_
`6a ofthe aMISFE'Tand the second-type internal stress film8b
`made of a TEOSfilmcoversa side surface ofthegate elec-
`trode 64 of the pMISFET. Moreover, eachofthe source/drain
`regions 3a, 4a, 34 and 4b does not include a lightly doped
`impurily region and includes only a heavily doped impurily
`region. Other part has the samestructure as that ofthe semi-
`conductor device of the first embodiment.
`
`In this modified example, in addition to the effect of the
`first modified example, the following effect can be obtained.
`In the nMISFET,thefirst-type internal stress film 8a and the
`gate electrode 6a are in contact with each other substantially
`at the entire side surface ofthe gate electrode 6a, so that the
`gate electrode 6a is compressed downwardlybythefirst-type
`internal stress film 8a. With the gate electrode 6a compressed
`downwardly, then, in the channel region Lr, a compressive
`stress is generated in the vertical direction to the principal
`surface and the mobility of electrodes in the nMISFET is
`further improved.
`Moreover, in the pMISFET,the second-typeinternal stress
`film 84 andthe gate electrode 6b are in contact with each other
`substantially at the entire side surface ofthe gate clectrode 64,
`so that the gate electrode 64 is stretched upwardly by the
`second-typeinternalstress film 8b. Withthe gate electrode 6b
`stretched upwardly, then, in the channel region 1y, a tensile
`stress is generated in the vertical direction to the principal
`surface and the mobility of holes in the pMISFFTis further
`improved.
`‘Therefore, in this structure,