`
`DOCKET NO.: 2003195-00123US3
`Filed By: David L. Cavanaugh, Reg. No. 36,476
`Dominic E. Massa, Reg. No. 44,905
`Michael H. Smith, Reg. No. 71,190
`1875 Pennsylvania Ave. NW
`Washington, DC 20006
`Tel: (202) 663-6000
`Email: David.Cavanaugh@wilmerhale.com
`Dominic.Massa@wilmerhale.com
`MichaelH.Smith@wilmerhale.com
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
`Petitioner
`
`v.
`
`GODO KAISHA IP BRIDGE 1
`Patent Owner.
`
`Case IPR2017-01843
`
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 7,893,501
`CLAIMS 1, 4-5, 7, 9-11, 15-18, and 23-25 (Petition #3)
`
`

`

`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`TABLE OF CONTENTS
`
`Page
`INTRODUCTION ............................................................................................. 1 
`I. 
`II.  MANDATORY NOTICES ............................................................................... 2 
`A. 
`Real Parties-in-Interest .......................................................................... 2 
`B. 
`Related Matters ...................................................................................... 2 
`C. 
`Counsel .................................................................................................. 2 
`D. 
`Service Information ............................................................................... 2 
`E. 
`Fee for Inter Partes Review ................................................................... 3 
`III.  CERTIFICATION OF GROUNDS FOR STANDING .................................... 3 
`IV.  OVERVIEW OF CHALLENGE AND RELIEF REQUESTED ...................... 3 
`A.  Grounds for Challenge .......................................................................... 4 
`B. 
`Prior Art Patents and Printed Publications Relied Upon ...................... 4 
`C. 
`Relief Requested .................................................................................... 4 
`PERSON OF ORDINARY SKILL IN THE ART ............................................ 4 
`V. 
`VI.  TECHNOLOGY BACKGROUND .................................................................. 5 
`VII.  OVERVIEW OF THE ’501 PATENT .............................................................. 8 
`A. 
`Priority Date of the ’501 Patent........................................................... 15 
`B. 
`Summary of the Prosecution History .................................................. 15 
`VIII. CLAIM CONSTRUCTION ............................................................................ 17 
`IX.  GROUNDS FOR FINDING THE CHALLENGED CLAIMS INVALID ..... 18 
`A.  Ground 1: Claims 1, 4-5, 7, 9-11, 15-18, and 23-25 are rendered
`obvious by Misra in view of Tsai ........................................................ 18 
`1. 
`Independent Claim 1 ................................................................. 18 
`2. 
`Dependent Claim 4 ................................................................... 44 
`3. 
`Dependent Claim 5 ................................................................... 45 
`4. 
`Dependent Claim 7 ................................................................... 51 
`5. 
`Dependent Claim 9 ................................................................... 53 
`6. 
`Dependent Claim 10 ................................................................. 55 
`7. 
`Dependent Claim 11 ................................................................. 57 
`8. 
`Dependent Claim 15 ................................................................. 59 
`9. 
`Dependent Claim 16 ................................................................. 60 
`
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`10.  Dependent Claim 17 ................................................................. 61 
`11.  Dependent Claim 18 ................................................................. 63 
`12.  Dependent Claim 23 ................................................................. 65 
`13.  Dependent Claim 24 ................................................................. 67 
`14.  Dependent Claim 25 ................................................................. 70 
`X.  CONCLUSION ............................................................................................... 72 
`
`
`
`
`ii
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`
`I.
`
`INTRODUCTION
`Petitioner Taiwan Semiconductor Manufacturing Company Ltd.
`
`(“Petitioner”) respectfully requests inter partes review (“IPR”) of claims 1, 4-5, 7,
`
`9-11, 15-18, and 23-25 of U.S. Patent No. 7,893,501 (“the ’501 patent”) (Ex-
`
`1201).
`
`The ’501 patent claims a conventional MISFET device. The claim
`
`limitations of claim 1 (the sole independent claim) are directed to features that
`
`were standard to many, if not all, MISFET devices – an active region made of a
`
`semiconductor substrate, a gate insulating film, a gate electrode, source/drain
`
`regions, and a silicon nitride film.
`
`Applicant obtained allowance of the claims after multiple rejections by
`
`amending claim 1 to require that the gate electrode protrude upward from the
`
`silicon nitride film. The Examiner’s reason for allowance stated the protruding
`
`gate electrode was not in the “prior art of record.” However, the Examiner did not
`
`have the benefit of references Misra (Ex-1204) and Igarashi (Ex-1207), which are
`
`two examples of MISFETs with a protruding gate electrode.
`
`There was nothing novel about having a protruding gate electrode. The
`
`specification of ’501 patent does not even mention this feature, let alone identify
`
`any purported advantages. Moreover, MISFETs with a protruding gate electrode
`
`1
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`

`

`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`are disclosed in prior art references such as Misra and Igarashi. Claim 1 thus
`
`recites nothing more than a conventional MISFET with widely used features.
`
`The dependent claims merely recite conventional aspects of MISFETs that
`
`are disclosed and rendered obvious by the prior art – e.g., the choice of gate
`
`electrode material and the inclusion of standard structures like thin films, interlevel
`
`insulating films, and sidewalls.
`
`Each of the challenged claims is therefore unpatentable.
`
`II. MANDATORY NOTICES
`A. Real Parties-in-Interest
`Taiwan Semiconductor Manufacturing Company Ltd. is the real party-in-
`
`interest.
`
`B. Related Matters
`Petitioner is filing three other inter partes review petitions challenging the
`
`claims of the ’501 patent. The following litigation would affect or be affected by a
`
`decision in this proceeding: Godo Kaisha IP Bridge 1 v. Xilinx, Inc., Case No.
`
`2:17-cv-00100 (E.D. Tex.).
`
`C. Counsel
`Lead Counsel: David L. Cavanaugh (Registration No. 36,476)
`
`Backup Counsel: Dominic E. Massa (Registration No. 44,905)
`
`Backup Counsel: Michael H. Smith (Registration No. 71,190)
`
`D.
`
`Service Information
`
`2
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`

`

`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`Email: David L. Cavanaugh, David.Cavanaugh@wilmerhale.com
`
`Dominic E. Massa, Dominic.Massa@wilmerhale.com
`
`Michael H. Smith, MichaelH.Smith@wilmerhale.com
`
`Post and Hand Delivery: WilmerHale, 1875 Pennsylvania Ave. NW
`Washington, DC 20006
`Telephone: 202-663-6000
`Facsimile: 202-663-6363
`
`Pursuant to 37 C.F.R. § 42.10(b), Powers of Attorney accompany this
`
`Petition. Please address all correspondence to lead and backup counsel. Petitioner
`
`consents to service of all documents via email.
`
`E.
`Fee for Inter Partes Review
`The undersigned authorizes the PTO to charge the fee set forth in 37 C.F.R.
`
`§ 42.15(a) for this Petition to Deposit Account No. 08-0219. Review of 14 claims
`
`is requested. The undersigned authorizes payment for additional fees that may be
`
`due with this petition to be charged to the above-referenced Deposit Account.
`
`III. CERTIFICATION OF GROUNDS FOR STANDING
`Petitioner certifies pursuant to Rule 42.104(a) that the patent for which
`
`review is sought is available for inter partes review and that Petitioner is not
`
`barred or estopped from requesting an inter partes review challenging the patent
`
`claims on the grounds identified in this Petition.
`
`IV. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED
`
`3
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`Pursuant to Rules 42.22(a)(1) and 42.104(b)(1)-(2), Petitioner challenges
`
`claims 1, 4-5, 7, 9-11, 15-18, and 23-25 (“the challenged claims”) of the ’501
`
`patent and requests that each challenged claim be cancelled.
`
`A. Grounds for Challenge
`This Petition, supported by the declaration of Dr. Stanley Shanfield
`
`(“Shanfield Decl.,” Ex-1202), demonstrates that there is a reasonable likelihood
`
`that Petitioner will prevail with respect to at least one of the challenged claims and
`
`that each of the challenged claims is unpatentable for the reasons cited in this
`
`petition. See 35 U.S.C. § 314(a).
`
`B.
`Prior Art Patents and Printed Publications Relied Upon
`Petitioner relies upon the following patents and printed publications:
`
`1.
`
`U.S. 5,960,270 (“Misra,” Ex-1204), issued September 28, 1999, is prior art
`
`to the ’501 patent under 35 U.S.C. §§ 102(a), 102(b), and 102(e).
`
`2.
`
`U.S. 6,444,566 (“Tsai,” Ex-1215), filed on April 30, 2001 and issued on
`
`Sep. 3, 2002, is prior art under 35 U.S.C. §§ 102(a), 102(b), and 102(e).
`
`C. Relief Requested
`Petitioner requests that the Patent Trial and Appeal Board cancel the
`
`challenged claims because they are unpatentable under 35 U.S.C. § 103.
`
`V.
`
`PERSON OF ORDINARY SKILL IN THE ART
`A person of ordinary skill in the art (POSITA) at the time of the alleged
`
`invention of the ’501 patent would have had the equivalent of a Master’s degree in
`
`4
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`electrical engineering, physics, chemistry, materials science, or equivalent training,
`
`and two years of work experience in field of semiconductor manufacturing.
`
`Additional graduate education could substitute for work experience, and additional
`
`work experience/training could substitute for formal education. (Shanfield Decl.
`
`¶¶34-36 (Ex-1202).)
`
`VI. TECHNOLOGY BACKGROUND
`The challenged claims relate to semiconductor devices, which existed long
`
`before the filing of the application that became the ’501 patent. The claims recite
`
`features that were standard to many, if not all, MISFET transistors, such as an
`
`active region made of a semiconductor substrate, a gate insulating film, a gate
`
`electrode, source/drain regions, and a silicon nitride film. (Shanfield Decl. ¶37
`
`(Ex-1202).)
`
`Metal–insulator–semiconductor field effect transistors (MISFETs) were
`
`developed long before the ’501 patent. The small size of MISFETs as compared
`
`with prior vacuum tube technologies helped enable much of the modern computer
`
`and electronics industry that developed from the 1970s and 1980s through the
`
`present. (Shanfield Decl. ¶38 (Ex-1202).)
`
`MOS transistors are a type of MISFET where the insulating film is an oxide,
`
`such as silicon dioxide or silicon nitride oxide (silicon oxynitride). MOS
`
`transistors are by far the most common type of MISFET. (Shanfield Decl. ¶39
`
`5
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`

`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`
`(Ex-1202).)
`
`The figure below from Plummer at 86 (Ex-1209) shows an example of a
`
`MISFET, and more particularly, a MOS transistor.1 (Shanfield Decl. ¶39 (Ex-
`
`1202).)
`
`
`
`MISFETs include active regions made of a semiconductor substrate. The active
`
`regions are found between the shallow trench isolation regions (STI). (See Rabaey
`
`at 42-43 (Ex-1211).) The active regions are where the transistors are formed. (Id.
`
`at 42.) The source and drain regions (green), the channel (area between the source
`
`and drain regions), and the well (“N Well” and “P Well”) are formed in regions of
`
`the active regions. The gate electrode (orange) is formed above the channel.
`
`1 Color and labels have been added to facilitate the description.
`
`6
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`

`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`
`(Shanfield Decl. ¶¶39-44 (Ex-1202).)
`
`The gate electrode (orange) is separated from the channel by an insulating
`
`film (red). The doped regions of the source and drain regions (green) are formed
`
`by doping the substrate with impurities. It was common and conventional for
`
`source and drain regions (green) to have a lightly-doped region, a heavily doped
`
`region, and a silicide film, as shown in the figure above. (Shanfield Decl. ¶¶42-46
`
`(Ex-1202).)
`
`Silicon nitride films were commonly included over the source and drain
`
`regions (green) in MISFET devices, with the gate electrode (orange) protruding
`
`above the silicon nitride film. (E.g., Igarashi at [0117-0118] (describing protruding
`
`gate electrode illustrated in Fig. 12), Fig. 12 (Ex-1207); Misra at 5:52-55; 6:67-
`
`7:15 (describing formation of protruding gate illustrated in Fig. 7), Fig. 7 (Ex-
`
`1204).) Silicon nitride films were used for applications like etch stops. (E.g.,
`
`Igarashi at [0047] (etch stop) (Ex-1207); Misra at 5:24-27 (etch stop) (Ex-1204).)
`
`The use of silicon nitride films in MISFET devices and design choices about what
`
`portions of the device to cover and how to locate the height of the gate relative to
`
`the nitride film were well understood before the alleged invention of the ’501
`
`patent. (Shanfield Decl. ¶47 (Ex-1202).)
`
`
`
`
`
`7
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`

`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`
`VII. OVERVIEW OF THE ’501 PATENT
`The challenged claims are directed to a transistor with the standard
`
`structures of conventional MISFETs at the time. As depicted in Figure 1 of the
`
`’501 patent, reproduced below, the claimed device of the ’501 patent includes: (1)
`
`an active region 1a made of a substrate 1, (2) a gate insulating film 5 (red), (3) a
`
`gate electrode 6a (orange), (4) source and drain regions 3a, 4a including a silicide
`
`layer (green), (5) a silicon nitride film 8a (blue), and (6) the gate electrode 6a that
`
`protrudes from the silicon nitride film 8a. (’501 patent at 3:19-64 (Ex-1201).) The
`
`active region 1a is located between the isolation regions 2 and is where the
`
`transistor is formed. (’501 patent at 3:19-64, Fig. 1 (Ex-1201).) (Shanfield Decl.
`
`¶48 (Ex-1202).)
`
`
`
`8
`
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`

`

`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`The allegedly distinguishing feature of the claims of the ’501 patent is gate
`
`6a protruding above the silicon nitride film 8a.2 (See Summary of the Prosecution
`
`History below.) The specification of ’501 patent, however, does not even mention
`
`the protruding gate electrode, let alone identify any purported advantages.
`
`(Shanfield Decl. ¶49 (Ex-1202).)
`
`When the application that led to the ’501 patent was filed, there was nothing
`
`new about these standard transistor features. Multiple prior art references
`
`disclosed MISFETs with the same elements as the ’501 patent, including a
`
`protruding gate. (Shanfield Decl. ¶50 (Ex-1202).)
`
`For example, Misra, the primary reference for this petition, discloses a
`
`MISFET with the claimed features of the ’501 patent. Figure 7 in Misra,
`
`reproduced below, shows: (1) an active region made of a semiconductor substrate
`
`(active areas of semiconductor substrate 12 where the transistor is formed) (Misra
`
`at 4:21-28, 4:31-33, 4:42-50, 6:16-19 (Ex-1204)), (2) a gate insulating film
`
`2 The alleged invention described in the specification of the ’501 patent involves
`
`generating stress in the transistor channel by using tensile and compressive stresses
`
`of various layers. (See, e.g., ’501 patent, Abstract, 1:20-23 (Ex-1201).) However,
`
`the stress limitations are only recited in claims 2, 3, and 20. The challenged claims
`
`in this IPR petition do not recite any stress limitations. (Shanfield Decl. at n. 3
`
`(Ex-1202).)
`
`9
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`

`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`(thermal gate oxide 27) (red) (id. at 6:59-67), (3) a gate electrode (gate electrode
`
`28b) (orange) (id. at 6:66-7:2, 7:14-20), (4) source and drain regions (silicide
`
`regions 18 formed on source and drain electrodes 26, 28) (green) (id. at 4:42-46,
`
`6:16-33), (5) a silicon nitride film (plasma enhanced nitride layer 20) (blue) (id. at
`
`5:20-27), and (6) the gate electrode 28b protruding upward from the silicon nitride
`
`film (plasma enhanced nitride layer 20) (id. at 5:52-55; 6:67-7:15, Fig. 7):
`
`
`
`
`Misra at Fig. 7 (Ex-1204). (Shanfield Decl. ¶51 (Ex-1202).)
`
`A POSITA would have understood that the relevant disclosure as described
`
`in the specification of Misra and illustrated in the figures is the same as the ’501
`
`patent. While there may be differences in how the illustrators choose to draw
`
`various features, a POSITA would have understood from the specifications that the
`
`relevant disclosures are the same. For example, Misra shows the silicide layer 18
`
`and the source/drain electrodes 26 and 28 in Fig. 7, whereas the ’501 patent shows
`
`10
`
`

`

`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`the source and drain regions 3a/4a in Fig. 1, but does not illustrate the silicide
`
`layer. However, in both cases, the specifications state that the source/drain regions
`
`include a silicide layer. (Compare Misra at 6:30-33 (“the silicide regions 18
`
`remain as a portion of the source and drain electrodes”), 9:45-50 (disclosing
`
`formation of “upper silicide layer 116 as a portion of the source and drain
`
`regions”) (Ex-1204)) with (’501 patent at 3:29-32 (“n-type source/drain regions 3 a
`
`and 4 a each of which includes … a silicide layer”) (Ex-1201).) (Shanfield Decl.
`
`¶52 (Ex-1202).)
`
`A POSITA would have understood that the relevant disclosure – e.g., a
`
`source/drain region with a silicide layer formed in regions of the active region – is
`
`the same even if the schematic illustrations are not identical. In both cases, the
`
`silicide layer is formed by reacting metal with the silicon substrate and the silicon
`
`from the active region of the substrate is consumed forming the silicide. This
`
`results in part of the silicide being buried in the active region because it has
`
`consumed some of the silicon substrate in the active region. (E.g., Naftel at 140,
`
`Fig. 5.11 (illustrating NiSi2 or NiSi (silicides) being buried in the Si Substrate by
`
`consuming part of the Si Substrate); 5, Fig. 1.3 (Ex-1223).) (Shanfield Decl. ¶52
`
`(Ex-1202).)
`
`Misra discloses the silicide layer is formed through a selective growth
`
`process and thus the active areas contain a layer 18 silicide. (Misra at 4:43-47
`
`11
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`

`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`(disclosing “a selective growth process is used to selectively form a silicide region
`
`18”) (Ex-1204); see also id. at 5:8-11 (disclosing “p-channel active areas in n-type
`
`wells contain a layer 18 that is ion implanted with p-type impurities (e.g., boron),
`
`an n-channel active areas within p-wells contain a layer 18 that is implanted with
`
`n-type impurities”).) The ’501 patent is silent as to the process used to form the
`
`silicide because a POSITA would have understood that it was formed through the
`
`known selective growth process. (Shanfield Decl. ¶53 (Ex-1202).)
`
`Naftel illustrates the selective growth process used in Misra and the ’501
`
`patent in more detail and shows how the silicide forming the upper surface of the
`
`source/drain regions is formed in the active region by burying into the active
`
`region. Figure 5.11 in Naftel shows that the silicide (NiSi2 or NiSi) buries into the
`
`Si Substrate by consuming part of the Si Substrate.
`
` (Naftel at 140, Fig. 5.11 (annotated); 5, Fig. 1.3 (Ex-1223).) Naftel illustrates the
`
`CMOS device that results from this selective growth process in Figure 1.2, with the
`
`
`
`12
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`

`

`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`silicide portion of the source/drain regions depicted below the surface of the silicon
`
`substrate.
`
`
`
`(Naftel at 4, Fig. 1.2 (Ex-1223).) The ’501 patent illustrates the source and drain
`
`regions 3a/4a in Fig. 1, but omits the silicide layer from the illustration, whereas
`
`Misra shows the source/drain electrodes 26 and 28, silicide layer 18, and the
`
`substrate 12. (Misra at Fig. 7 (Ex-1204); ’501 patent at Fig. 1 (Ex-1201).) Other
`
`references, such as Wieczoerek and Plummer, disclose the same process and
`
`illustrate the silicide as being formed partially above and partially below the
`
`surface of the substrate. (E.g., Wieczoerek at 1:63-2:4 and Fig. 2 (disclosing a
`
`13
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`

`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`“rapid thermal anneal” where “reaction of the metal with the silicon forms a
`
`silicide 24”) (Ex-1213); Plummer at 86, Fig. 2-39 (illustrating part of the silicide
`
`buried in active areas) (Ex-1209).) Thus, while the schematic illustrates the
`
`silicide layers may differ, or even omit the silicide as in the case of the ’501 patent,
`
`a POSITA would have understood that the disclosure is the same because the same
`
`processes are used to form the silicide in the active region. (Shanfield Decl. ¶54
`
`(Ex-1202).)
`
`Similarly, Figure 12 of Igarashi, the primary reference in related petitions,
`
`shows a transistor incorporating the claimed features of the ’501 patent, including
`
`the gate electrode 3 (orange) protruding upward from the silicon nitride film 8
`
`(blue):
`
`
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`14
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`

`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`(Igarashi at Fig. 123; [0117-18] (Ex-1207) (Shanfield Decl. ¶55 (Ex-1202).)
`
`In fact, these are just a few of the many references that had the conventional
`
`feature of a protruding gate electrode. (See also, e.g., U.S. Patent Nos. 6,509,234
`
`(Ex-1218); 5,726,479 (Ex-1219); 6,512,266 (Ex-1220); 6,806,584 (Ex-1221).)
`
`(Shanfield Decl. ¶56 (Ex-1202).)
`
`A.
`
`Priority Date of the ’501 Patent
`
`The ’501 patent claims priority to a Japanese patent, JP 2003-170335, filed
`
`June 16, 2003, and to U.S. Patent Application No. 10/859,219, filed June 3, 2004.
`
`(Shanfield Decl. ¶57 (Ex-1202).)
`
`Because each of the prior art references is prior art to the ’501 patent’s
`
`earliest claimed U.S. and foreign priority dates, Petitioner does not address
`
`whether the ’501 patent is entitled to its claimed priority dates. However,
`
`Petitioner reserves the right to challenge the priority claims of the ’501 patent.
`
`(Shanfield Decl. ¶58 (Ex-1202).)
`
`B.
`
`Summary of the Prosecution History
`
`The ’501 patent was allowed following multiple rounds of rejection after
`
`amending the claims to recite a gate electrode that protrudes upward from a silicon
`
`nitride film. The reason for allowance stated this feature was not in the “prior art
`
`3 Fig. 12 has been annotated with the reference numeral 8 for clarity. (See Igarashi
`
`at [0117-0118] (Ex-1207).) (Shanfield Decl. at ¶55 n.4 (Ex-1202).)
`
`15
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`of record,” but the prior art of record did not include Misra or Igarashi, which are
`
`two examples disclosing the claimed protruding gate electrode. (Shanfield Decl.
`
`¶59 (Ex-1202).)
`
`The ’501 patent issued from U.S. Patent Appl. No. 12/170,191, filed on July
`
`9, 2008. Following multiple rejections, Applicant amended pending claim 15
`
`(issued claim 1) to add “the gate electrode protrudes upward from a surface level
`
`of parts of the silicon nitride film located at both side surfaces of the gate
`
`electrode.” (August 6, 2010 at 2 Response (Ex-1203).) (Shanfield Decl. ¶60 (Ex-
`
`1202).)
`
`Applicant characterized the amendment as follows:
`
`In the present subject matter, as shown in, for example, FIGS. 1 and
`4A, the gate electrode 6a, 6b protrudes upward from a surface level of
`parts of the silicon nitride film 8a, 8b located at both side surfaces of
`the gate electrode 6a, 6b. In other words, a height of the gate electrode
`from the surface of the substrate is higher than a height of the silicon
`nitride film disposed at the sides of the gate electrode.
`
`(August 6, 2010 Response at 8 (Ex-1203).) Applicant argued that the applied
`
`references failed to show a protruding gate. (August 6, 2010 Response at 9 (Ex-
`
`1203).) (Shanfield Decl. ¶61 (Ex-1202).)
`
`On October 15, 2010, the claims were allowed in a Notice of Allowance.
`
`The Examiner provided the following reason for allowance: “A MISFET as
`
`16
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`claimed including a gate electrode protruding upward form [sic] a surface level of
`
`parts of a silicon nitride film located on the gate electrode’s sides could not be
`
`anticipated nor, in combination, be rendered obvious over the prior art of record.”
`
`(October 15, 2010 Notice of Allowance at 2 (Ex-1222).) (Shanfield Decl. ¶62 (Ex-
`
`1202).)
`
`The Examiner did not have the benefit of Misra or Igarashi, which each have
`
`a gate electrode that protrudes. Thus, this petition introduces new art that was not
`
`before the Examiner during prosecution. (Shanfield Decl. ¶63 (Ex-1202).)
`
`VIII. CLAIM CONSTRUCTION
`In an inter partes review, the terms in the challenged claims should be given
`
`their plain meaning under the broadest reasonable interpretation standard. Cuozzo
`
`Speed Technologies, LLC v. Lee, 136 S. Ct. 2131, 2139, 2141 (2016). Petitioner
`
`adopts that standard for this proceeding, but reserves the right to pursue different
`
`constructions in a district court, where different claim construction standards
`
`apply.
`
`Should the Patent Owner, seeking to avoid the prior art, contend that the
`
`claims have a construction different from their broadest reasonable construction,
`
`the appropriate course is for the Patent Owner to seek to amend the claims to
`
`expressly correspond to its contentions in this proceeding. See 77 Fed. Reg.
`
`48,764; 48,766-67 (Aug. 14, 2012).
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`17
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`

`

`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`IX. GROUNDS FOR FINDING THE CHALLENGED CLAIMS INVALID
`Pursuant to Rule 42.104(b)(4)-(5), specific grounds for finding the
`
`challenged claims invalid are identified below and discussed in the Shanfield
`
`Declaration (Ex-1202). These grounds demonstrate in detail that claims 1, 4-5, 7,
`
`9-11, 15-18, and 23-25 are not patentable under 35 U.S.C. § 103. (Shanfield Decl.
`
`¶65 (Ex-1202).)
`
`A. Ground 1: Claims 1, 4-5, 7, 9-11, 15-18, and 23-25 are rendered
`obvious by Misra in view of Tsai
`Claims 1, 4-5, 7, 9-11, 15-18, and 23-25 are rendered obvious by Misra in
`
`view of Tsai. Misra and Tsai were not considered by the Examiner during
`
`prosecution of the ’501 patent. (Shanfield Decl. ¶66 (Ex-1202).)
`
`1.
`Independent Claim 1
`As illustrated in the chart below and in the discussion that follows, Misra in
`
`view of Tsai renders independent claim 1 of the ’501 patent obvious. (Shanfield
`
`Decl. ¶67 (Ex-1202).)
`
`18
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`

`

`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`Misra
`Tsai
`Misra at 2:41-44.
`
`
`Misra at 4:21-28,
`4:31-33, Fig. 7.
`Misra at 6:59-67,
`Fig. 7.
`Misra at 6:66-7:2,
`7:14-20, Fig. 7.
`Misra at Abstract,
`4:42-46, 6:30-33,
`7:14-20, Fig. 7.
`Misra at 5:20-27,
`5:52-55, 6:30-33,
`6:40-42, 6:67-7:15,
`Fig. 7.
`Misra at 5:52-55,
`6:67-7:15, Fig. 7.
`
`Misra at 6:67-7:15,
`Fig. 7.
`
`
`
`
`
`
`
`
`
`Tsai at 2:24-27,
`2:29-32, 2:51-
`59, Figs. 2.
`
`
`
`
`
`’501 Patent Claim 1
`[1p] 1. A semiconductor device,
`comprising a MISFET, wherein the
`MISFET includes:
`[1a] an active region made of a
`semiconductor substrate;
`[1b] a gate insulating film formed on the
`active region;
`[1c] a gate electrode formed on the gate
`insulating film;
`[1d] source/drain regions formed in
`regions of the active region located on
`both sides of the gate electrode; and
`[1e] a silicon nitride film formed over
`from side surfaces of the gate electrode to
`upper surfaces of the source/drain regions,
`wherein:
`[1f] the silicon nitride film is not formed
`on an upper surface of the gate electrode,
`and
`[1g] the gate electrode protrudes upward
`from a surface level of parts of the silicon
`nitride film located at both side surfaces
`of the gate electrode.
`
`
`a)
`
`Claim 1 – Preamble (element [1p])
`
`19
`
`

`

`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`The preamble of claim 1 recites “[a] semiconductor device, comprising a
`
`MISFET, wherein the MISFET includes.” (’501 patent, claim 1 (Ex-1201).)
`
`Misra discloses the preamble. (Shanfield Decl. ¶68 (Ex-1202).)
`
`For example, Misra discloses “a metal-gated metal-oxide semiconductor
`
`(MOS) transistor.” (Misra at 2:41-44 (Ex-1204).) A MOS transistor is a type of
`
`MISFET where the insulator is an oxide. (E.g., Shimizu at 59 (“A MISFET having
`
`a gate insulating film made of a silicon oxide film is usually called a MOSFET
`
`(Metal Oxide Semiconductor Field Effect Transistor).”) (Ex-1225).) Thus, by
`
`disclosing a MOS transistor, Misra discloses a MISFET. (Shanfield Decl. ¶69 (Ex-
`
`1202).)
`
`Therefore, Mira discloses the preamble. (Shanfield Decl. ¶70 (Ex-1202).)
`
`b)
`Claim 1 – Active Region (element [1a])
`Claim 1 recites “an active region made of a semiconductor substrate.” (’501
`
`patent, claim 1 (Ex-1201).) Misra discloses this limitation. (Shanfield Decl. ¶71
`
`(Ex-1202).)
`
`For example, Misra discloses “a semiconductor substrate 12.”
`
`20
`
`

`

`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`
`
`
`
`
`(Misra at 4:21-28 (disclosing “semiconductor substrate 12”); Fig. 7 (Ex-1204).)
`
`(Shanfield Decl. ¶72 (Ex-1202).)
`
`Misra also discloses an active region made of the semiconductor substrate
`
`12: “These isolation trenches 14 are filled with a dielectric material in order to
`
`provide field isolation between active areas of the semiconductor device 10.”
`
`(Misra at 4:31-33 (Ex-1204).) A POSITA would have understood that the “active
`
`areas of the semiconductor device 10” in Misra are “made of” the semiconductor
`
`substrate 12 because the “active areas” (active region) are formed in the
`
`semiconductor substrate 12 and defined by “isolation trenches 14.” (Shanfield
`
`Decl. ¶73 (Ex-1202).)
`
`Misra’s disclosure of an active region made of a semiconductor substrate is
`
`essentially identical to the disclosure in the specification of the ’501 patent. Like
`
`21
`
`

`

`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`Misra, the ’501 patent describes the active region as a region of the semiconductor
`
`substrate that is divided by isolation regions: “[A] semiconductor substrate 1, i.e.,
`
`an Si (100) substrate is divided into a plurality of active regions 1 a and 1 b by an
`
`isolation region 2.” (’501 patent at 3:21-23 (Ex-1201).) The ’501 patent also, like
`
`Misra, describes the active region as the region where the device is formed: “The
`
`semiconductor device includes an nMISFET formation region Rn which includes
`
`the active region 1 a and in which an nMISFET is to be formed and a pMISFET
`
`formation region Rp which includes the active region 1 b and in which a pMISFET
`
`is to be formed.” (’501 patent at 3:23-27 (Ex-1201).) Thus, Misra and the ’501
`
`patent both describe the active region made of the substrate as the region bounded
`
`by isolations regions where the transistor is formed. (Shanfield Decl. ¶74 (Ex-
`
`1202).)
`
`
`
`Therefore, Misra discloses this limitation. (Shanfield Decl. ¶75 (Ex-1202).)
`
`c)
`Claim 1 – Gate Insulating Film (element [1b])
`Claim 1 recites “a gate insulating film formed on the active region.” (’501
`
`patent, claim 1 (Ex-1201).) Misra discloses this limitation. (Shanfield Decl. ¶76
`
`(Ex-1202).)
`
`For example, Misra discloses in Figure 7 that the thermal gate oxide 27 (gate
`
`insulating film) (red) is formed below the gate electrode 28b and on the active
`
`region of semiconductor substrate 12:
`
`22
`
`

`

`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`
`
`(Misra at Fig. 7 (annotated) (Ex-1204); see also, e.g., id. at 6:59-61 (disclosing “a
`
`thermal gate oxide 27.”).) A POSITA would have understood that the thermal
`
`gate oxide 27 is a “gate insulating film” because it is formed between the gate
`
`electrode 28b and the semiconductor substrate 12 and because it insulates the gate
`
`electrode 28b from the active region. The thermal gate oxide 27 insulates the gate
`
`electrode 28b from the active region because oxide films are insulating films.
`
`Additionally, a POSITA would have understood that the thermal gate oxide 27
`
`(gate insulating film) is formed “on the active region” because it is formed on the
`
`region of the semiconductor substrate 12 between the isolation trenches 14 where
`
`the devi