(12) United States Patent
`(10) Patent N0.:
`US 6,326,301 B1
`
`Venkatesan et al.
`(:45) Date of Patent:
`Dec. 4, 2001
`
`U8006326301B1
`
`(54) METHOD FOR FORMING A DUAL INLAID
`COPPER INTERCONNECT STRUCTURE
`
`(75)
`
`.
`.
`.
`.
`Inventors' 3:1:31:11:12]:algal? i:$311811?'Ofsmlth’
`Austin, TX (US)
`
`(73) Assignee: Motorola, Inc., Schaumburg, IL (US)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`.
`(21) Appl' No" 09/352’134
`(22)
`Filed;
`Jul, 13,1999
`
`
`H01L 21/4763; H01L 21/44
`Int- Cl-7 -
`(51)
`(52) US. Cl.
`........................ .. 438/638; 438/618; 438/634;
`438/687; 438/970
`(58) Field of Search ................................... .. 438/618, 638,
`438/634, 620, 637, 671, 687, 970
`_
`REferences Clte‘l
`U S PATENT DOCUMENTS
`'
`'
`.......................... .. 438/622
`6/2000 Ong et a1.
`.
`438/638
`8/2000 Zhao et al.
`8/2000 Lai
`..................................... .. 438/638
`
`6,077,768 *
`6,100,184 *
`6,103,619 *
`
`(56)
`
`OTHER PUBLICATIONS
`
`Nakamura et al., “High Performance Al Dual Damascene
`Process with Elevated Double Stoppers,” Microelectronics
`Engineering Laboratory, Toshiba Corporation, IEEE (1998).
`* cited by examiner
`Primary Examiner—Richard Elms
`Assistant Examiner—Adam J. Pyonin
`(74) Attorney, Agent, or Firm—Keith E. Witek; Patricia S.
`GOddard
`(57)
`
`ABSTRACT
`
`A dual inlaid copper interconnect structure uses a plasma
`enhanced nitride (PEN) bottom capping layer and a silicon
`rich silicon oxynitride intermediate etch stop layer. The
`interfaces (16a, 16b, 20a, and 20b) between these layers (16
`and 20) and their adjacent dielectric layers (18 and 22) are
`positioned in the stack (13) independent of the desired
`aspect ratio of trench openings of the copper interconnect in
`order to improve optical properties of the dielectric stack
`(13). Etch processing is then used to position the layers (16)
`and (20) at locations Within the inlaid structurc depth that
`result
`in one or more of reduced DC leakage current,
`improved optical performance, higher
`frequency of
`operation, reduced cross talk, increased flexibility of design,
`or like improvements.
`
`16 Claims, 5 Drawing Sheets
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`FIG. 1
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`US. Patent
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`Dec. 4, 2001
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`Sheet 1 0f 5
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`US 6,326,301 B1
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`Dec. 4, 2001
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`Dec. 4, 2001
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`US 6,326,301 B1
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`US. Patent
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`Dec. 4, 2001
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`US 6,326,301 B1
`
`1
`METHOD FOR FORMING A DUAL INLAID
`COPPER INTERCONNECT STRUCTURE
`
`FIELD OF THE INVENTION
`
`The present invention relates generally to semiconductor
`manufacturing, and more particularly to, forming a dual
`inlaid copper interconnect within an integrated circuit (IC).
`BACKGROUND OF THE INVENTION
`
`10
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`2
`be adequate diffusion barriers to prevent copper and asso-
`ciated impurities within the copper from diffusing through
`the film and contaminating adjacent dielectric layers or
`underlying electrical devices.
`In addition to chemical reactions, engineers who are
`designing copper-based interconnects should also be con-
`cerned with the optical properties of the dielectric stack used
`to define a dual
`inlaid or inlaid structure. Chemically
`mechanically polished (CMP) copper has a highly reflective
`top surface which may readily reflect light/energy during
`lithographic operations. Furthermore, the plurality of dielec-
`tric layers in the dielectric stack of a copper interconnect
`creates many interfaces of different materials that can
`adversely reflect light and cause distortion of critical dimen-
`sions (CDs) and/or destructive interference whereby photo-
`resist is not properly exposed and developed. In other words,
`at certain depths of lithographic focus, wavelengths of light,
`and thicknesses of material, light reflected from a surface of
`a copper interconnect or dielectric interfaces may destruc-
`tively interfere or distort various lithographic feature sizes
`resulting in reduced yield and/or reduced performance of an
`integrated circuit. Therefore, various etch stop and capping
`layers within an inlaid copper structure should be geometri-
`cally and chemically designed with adequate anti-reflective
`coating (ARC) properties so that a high yield integrated
`circuit can be manufactured in an effective manner.
`
`Specifically, the thicknesses of the dielectric and etch stop
`layers within the dielectric inlaid stack must be carefully
`engineered to reduce reflectance and/or ensure that any
`reflectance that occurs is primarily destructive interference
`when some level of reflection is unavoidable. In addition,
`the index of refraction (N) and the extinction coefficient (K)
`of the materials within the dielectric stack need to be
`
`carefully considered in order to tune the optical properties of
`the stack to the wavelength of lithographic light utilized. In
`addition, the interface between different materials within the
`dielectric stack must be carefully placed to avoid the various
`optical problems associated with unwanted reflection.
`In addition to the chemical
`interaction concerns and
`
`optical concerns discussed above, various electrical proper-
`ties of films within the dielectric stack must also be consid-
`
`ered. Since the etch stop layers, ARC layers, and/or capping
`layers of the dielectric stack generally contact the intercon-
`nect metallurgy, the etch stop/ARC layers need to be mate-
`rially engineered and physically placed within the dielectric
`stack to prevent unacceptable levels of leakage current
`between adjacent interconnects within an integrated circuit.
`In addition, the dielectric constants of these materials and/or
`the physical placement and cross sectional geometry of these
`materials need to be carefully engineered and considered in
`order to ensure that
`the IC may be operated at a high
`frequency of operation absent of significant cross talk and/or
`parasitic capacitance. In addition,
`the above engineering
`should strive to solve these problems while not to compli-
`cating the etch chemistries or the etch steps of the dielectric
`stack in a manner that is unacceptable.
`The various layers contained within a dielectric stack of
`a dual inlaid copper interconnect create various mechanical
`concerns as well. The materials used in the dielectric stack
`must be engineered to provide adequate adhesion between
`silicon dioxide, copper, and various copper barrier materials.
`In addition, the stress exerted by these various films on the
`integrated circuit structure should be at or below an accept-
`able threshold. Further, the geometric aspect ratio of the via
`openings and the trench interconnect openings of the dual
`inlaid structure need to adjusted in order to ensure reduced
`keyhole formation, reduced voiding, and improved copper
`electromigration (EM) resistance.
`
`In the integrated circuit (IC) industry, aluminum intercon-
`nects are now being replaced with copper-based inlaid
`interconnect structures. Copper interconnects are fairly new
`to the semiconductor industry and are very different from the
`more commonly used aluminum-based systems. For this
`reason, copper interconnects have uncovered new problems
`not before anticipated or addressed by integrated circuit
`manufacturing facilities. Specifically, a dual inlaid copper
`interconnect structure comprises at least two etch stop layers
`interleaved between at
`least
`two thicker silicon dioxide ,
`layers for a total of four layers of dielectric where aluminum
`usually required only one dielectric material made via one
`deposition step. The stack of at least two dielectric layers
`and at least two etch stop layers used by copper intercon-
`nects is lithographically patterned and etched in multiple
`photo steps and via multiple etch processes where aluminum
`interconnects generally need no such processing. Further the
`copper metallurgy itself usually requires multiple materials
`(e.g., barrier layers, seed layers, bulk layers, etc.), multiple
`deposition steps, and/or one or more chemical mechanical
`polishing (CMP) processes where aluminum processes
`needs only a single and simple deposition step.
`In order to make these more complex copper interconnect
`structures efficiently and with high yield, engineers must
`consider many different combinations of complexities not
`before addressed. Specifically, lithographic and etch pro-
`cessing of dual inlaid copper structures must contend with
`one or more of: (1) adverse chemical interactions related to
`copper; (2) more complicated optical issues associated with
`the dielectric interfaces in the copper dielectric stack (e.g.,
`light reflection, destructive interference,
`light distortion,
`etc); (3) disadvantageous electrical properties associated
`with dielectric materials and etch stop layers within the
`copper dielectric stack; (4) complications in etch chemistries
`and etch processing; and
`the more complicated mechani-
`cal integrity of the inlaid structure. While one of these five
`factors may have been faced by aluminum on occasion,
`never has a combination of two or more of these issues been
`a serious concern for aluminum—based ICs.
`
`15
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`
`In addition to the collective weight of several of the five
`factors enumerated above, many copper-based designs
`require that different copper layers over the same integrated
`circuit have different
`trench depths and thicknesses. For
`example, the dual inlaid via height within inlaid structures
`may be designed to vary from layer to layer on the same IC,
`and different trench interconnect depths within the dual
`inlaid structures may also vary between the first metal layer
`and the Nth metal layer within a single integrated circuit (N
`being up to or greater than eight in current IC devices).
`With respect to the first of the five factors enumerated
`above,
`integrated circuit engineers are concerned with
`adverse chemical interactions that are associated with cop-
`per based materials and processing. Copper will adversely
`react with ambient air and oxidize in a manner that could
`
`reduce integrated circuit yield and/or adversely increase the
`resistance of the electrical interconnects. In addition, all etch
`stops and/or capping layers in contact with the copper must
`
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`US 6,326,301 B1
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`3
`Aproblem is that any one of the above concerns may be
`addressed and optimized within an IC interconnect structure
`when ignoring all the other concerns. When two or three, not
`to mention all five, of the above discussed concerns are
`considered at once, it is difficult to make the proper trade-
`offs and decisions that result
`in the best possible inlaid
`structure for a certain set of conditions.
`
`Therefore, it should be evident to one of ordinary skill in
`the art that many complicated and sometimes conflicting
`concerns must be considered and balanced when engineer-
`ing a multi-layer dielectric stack for use in copper intercon-
`nected devices. A structure that considers two or more of
`
`these needs and creates an improved inlaid structure is
`needed in the art.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`10
`
`15
`
`FIGS. 1—5 illustrate, in cross sectional diagrams, a first
`method for forming a copper interconnect structure.
`FIGS. 6—9 illustrate, in cross sectional diagram, a second ,
`method that is used for forming dual inlaid copper intercon-
`nects on an integrated circuit (IC).
`It will be appreciated that for simplicity and clarity of
`illustration, elements illustrated in the drawings have not
`necessarily been drawn to scale. For example, the dimen-
`sions of some of the elements are exaggerated relative to
`other elements for clarity. Further, where considered
`appropriate, reference numerals have been repeated among
`the drawings to indicate corresponding or analogous ele-
`ments.
`
`DESCRIPTION OF A PREFERRED
`EMBODIMENT
`
`Generally each of the two embodiments taught in FIGS.
`1—9 herein teach a copper dual inlaid interconnect process
`and structure that is formed through a dielectric stack. The
`dielectric stack is specifically engineered based upon the
`results of significant experimentation and testing. The mate-
`rials used for the etch stop/ARC layers and dielectric layers
`within the dielectric stack, as well as their physical place-
`ment within this structure and geometry, were designed to
`optimize or make acceptable trade-offs between two or more
`of: (1) optimal chemical protection of copper interconnects;
`(2) improved optical properties within the dielectric stack;
`(3)
`improved electrical properties of the structure;
`(4)
`reduced etch processing complexity; and (5)
`improved
`mechanical integrity of the copper interconnect. In addition,
`the interconnect structure processing taught herein are flex—
`ible for different environments (different materials, different
`lithographic wavelengths etc.). Further,
`the processing
`taught herein allows integrated circuits (ICs) to be manu-
`factured with multiple layers of metal interconnects wherein
`each layer of metal may have difi'erent trench interconnect
`opening aspect ratios and different via connection opening
`aspect ratios.
`The materials primarily considered for use as etch stop
`layers and ARCs herein were chemical vapor deposited
`(CVD) silicon nitride (SiNx), plasma enhanced silicon
`nitride (PEN), silicon oxynitride (SiOXNy), and silicon rich
`silicon oxynitride nitride (Si—SiOxNv). It was found that
`CVD silicon nitride films resulted in very good line-to-line
`current leakage performance, but that CVD silicon nitride
`must be deposited at a temperature that is too high for use
`with copper. Also, fear of copper cross-contamination gen-
`erally prevents manufacturing facilities from putting wafers
`with copper already on them into a CVD furnace.
`In
`addition,
`the higher dielectric constant of most silicon
`
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`nitride films (e.g., Er=7.0—8.0) when compared to silicon
`oxide (roughly Er=4.0) resulted in unacceptable high fre-
`quency performance of copper interconnects as well as
`unacceptable cross-talk in some test structures. Therefore,
`while CVD silicon nitride may be used as an etch stop or
`ARC layer within any portion of the dielectric stack taught
`herein,
`it was generally determined that a better set of
`trade-offs could be obtained by avoiding any use of con-
`ventional CVD silicon nitride films within the inlaid dielec-
`tric stacks taught herein.
`In addition to CVD silicon nitride, stoichiometric silicon
`oxynitride (SiON) was also studied in various positions and
`geometries within the dielectric stack. Stoichiometric silicon
`oxynitride with an index of refraction of n=1.6 and an
`extension coefficient of k=0.0 showed very low line-to-line
`leakage as did CVD silicon nitride. However, stoichiometric
`SiON also acted as a poor anti—reflective coating (ARC) and
`a poor via etch stop layer within dielectric stacks. Therefore,
`while stoichiometric silicon oxynitride may be used in the
`embodiments taught herein, it was generally found that other
`materials would likely produce a more acceptable dielectric
`stack for copper dual inlaid use.
`In addition to CVD silicon nitride and stoichiometric
`
`SiON, silicon-rich SiON films were researched as capping
`layers and as etch stop layers in a copper dual
`inlaid
`dielectric stack. Many compositions of silicon-rich SiON
`films were found to be excellent anti-reflective coatings
`(ARCs) and/or excellent etch stop layers within the dielec-
`tric stack, however, their use as a copper capping layer was
`not practical. SiON was less attractive as a copper capping
`layer since this material had a greater likelihood of chemi-
`cally reacting with the copper at the Cu—SiON interface.
`This reaction produced interfacial films which were shown
`to occasionally increase leakage current between adjacent
`copper interconnects and increase sheet resistance within
`individual interconnects. Therefore, when considering sev-
`eral of the five areas of concern enumerated above when
`
`searching for an improved etch stop, capping, and ARC
`layer combination, it was found that a silicon—rich silicon
`oxynitride films were best put to use as an intermediate etch
`stop layer near a central portion of the inlaid dielectric stack.
`However, Si-rich SiON material can be engineered to be
`generally used in any etch stop, ARC layer, or capping
`function within the devices taught herein, sometimes to less,
`but potentially acceptable, effect.
`The final of the four layers researched for use in the
`dielectric stack was plasma enhanced silicon nitride (PEN).
`It was found that plasma enhanced silicon nitride was an
`optimal capping layer to place in direct contact with copper
`since experimental results indicated either no degradation in
`sheet resistance or an acceptable interconnect resistance. In
`addition, PEN resulted in a reduction in leakage current
`while the containment and protection of the copper over
`time was within accepted tolerances.
`In addition to determining the optimal material composi-
`tion of various etch stop layers, ARC layers, and capping
`layers within the dielectric stack, the embodiments taught
`herein specifically engineer the various thicknesses, geo-
`metric properties, and physical positions of layers within the
`inlaid dielectric stack in order to improve or maintain the
`optical integrity of the interconnect structure during manu-
`facturing. Therefore,
`the selection of materials discussed
`above has typically improved the chemical stability of the
`copper interconnect, improved the electrical properties of
`the interconnect structures, and provided adequate mechani-
`cal stability to the integrated circuit while at the same time
`being engineered to provide adequate or improved optical
`
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`

`US 6,326,301 B1
`
`5
`properties over and above that available in prior art inlaid
`structures. In addition to obtaining these benefits, the etch
`processing taught herein is not significantly complicated
`compared to conventional copper processing. In addition,
`the resulting cross-sectional geometries (i.e., aspect ratio) of
`the trench interconnect opening in the via interconnect
`opening are also optimized in the structures herein to allow
`for formation of copper interconnects with reduced voiding
`and keyholes so that
`integrated circuit
`(IC) yield is
`enhanced.
`
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`6
`tric stack 13 that contains four layers 16, 18, 20, and 22. The
`layers 16, 18, 20, and 22 are subsequently used to form dual
`inlaid copper interconnect structures across an IC.
`As previously discussed, the capping layer 16 must be
`physically positioned, geometrically designed, and com-
`posed of a material that provides certain acceptable proper-
`ties and/or functions. Generally, the layer 16 should be an
`acceptable protective layer for the interconnects 14a and
`14b, especially if these layers may be adversely affected by
`exposure to an environment. For example, if layers 14a and
`14b are a copper-based interconnects, layer 16 should pro-
`vide adequate containment and protection of copper to
`prevent or
`reduce copper oxidation or contamination.
`Furthermore, layer 16 should function as an adequate barrier
`layer that prevents any copper contaminants or like con-
`taminants from diffusing from regions 14a and 14b into
`adjacent dielectric layers such as layers 12 and 18. The
`thickness and position of the layer 16 as well as its index of
`refraction (N) and its extinction coefficient
`should serve
`to improve the optical integrity of the dielectric stack 13
`(i.e., reduce distortion, reduce destructive interference, etc.).
`Proper engineering of this layer will result
`in reduced
`destructive interference upon light reflection, diminish any
`intensity of reflected light, and reduced distortion of litho-
`graphic critical dimensions (CD’s) upon reflection.
`In
`addition, layer 16 should be chosen to provide acceptable
`levels of leakage current between the layers 14a and 14b
`while providing for high frequency performance having
`reduced cross talk between layers 14a and 14b.
`As previously discussed, it has been determined that a
`plasma enhanced silicon nitride (PEN) layer is an optimal
`layer for use as layer 16 in FIG. 1 in order to reasonably
`obtain the above objectives. While it was found that plasma
`enhanced nitride (PEN) is a most appropriate choice for the
`material used for layer 16, other materials such as silicon
`oxynitride, silicon rich silicon nitride, silicon rich silicon
`oxynitride, CVD silicon nitride, or composites of these
`materials with or without PEN may be used as the capping
`layer 16 in FIG. 1. It was found that a thickness of the layer
`16 of roughly 500 angstroms worked well when using
`lithographic exposures of roughly 365 nm (i.e., I-line).
`However, other thicknesses may be used for I line, and other
`thicknesses are used for different wavelengths of exposure in
`order to optimally change the dimensions X and W in the
`figures do different lithographic characteristics. Other thick—
`nesses may be easily derived for other commonly used
`lithographic wavelengths, such as 248 nm (deep UV). In
`essence, the thickness of this film as well as its placement
`within the stack is also largely a function of the wavelength
`used for lithographic operations as is the engineered index of
`refraction and extension coefficient of this film. In addition,
`the reflective properties of the interface 16b and 16a is also
`largely a function of the composition and physical dimen-
`sions of the layers 18 and 12. Therefore, while an optimal
`layer 16 is roughly a 500 angstrom PEN layer when using
`I-line in the environment discussed herein, other reasonable
`thicknesses and other materials may be used for layer 16
`under different circumstances.
`
`A dielectric layer 18 is formed within the dielectric stack
`13 overlying the capping layer 16. In a preferred form, for
`improved electrical properties, adequate mechanical
`properties, and adequate optical properties, the layer 18 was
`selected as a CVD TEOS layer. However, the layer 18 may
`be any other dielectric layer taught herein or may be any
`composite thereof. Generally,
`the thickness of the layer
`(X-Y) is selected to be roughly 8000 angstroms in thickness.
`This thickness is selected to improve the optical properties
`
`Specific details of the various embodiments may be
`understood with specific references FIGS. 179.
`Specifically, FIGS. 1—5 illustrate a first embodiment that
`may be used to form a dual inlaid copper interconnect
`structure within an integrated circuit (IC).
`FIG. 1 illustrates a few beginning process steps that are
`used to start
`the formation of an integrated circuit 10.
`Integrated circuit 10 is to contain one or more layers of
`inlaid copper interconnect structures.
`In FIG. 1, all
`the ,
`shown elements are formed over a substrate surface, printed
`circuit board (PCB) or like substrate. While not specifically
`illustrated in FIG. 1, the substrate material which is com-
`monly used for integrated circuit formation is one of silicon,
`silicon germanium, germanium, gallium arsenide, other
`III-V compounds, a silicon carbide, epitaxial regions, silicon
`on insulator (SOI) substrates, or like starting material. Over
`this substrate is formed any number of passive devices such
`as resistors, capacitors, inductors, diodes, and the like. In
`addition, the substrate may support up to millions of inte-
`grated active devices, such as NMOS transistors, PMOS
`transistors, bipolar transistors, JFETs,
`thyristors, SCRs,
`memory cells, logic gates, and/or like electrical circuitry.
`Furthermore, micromachined and/or electromechanical
`devices such as pressure transducers, gears, engines,
`detectors, and/or the like may be formed on the integrated
`circuit (IC) substrate.
`The various devices that are formed on top of the substrate
`may be interconnected by one or more metallic layers. A
`single metallic layer may be used to form many segmented
`interconnects across the integrated circuit (IC). FIG. 1
`specifically illustrates that a first metallic layer is used to
`form at least two such interconnects 14a and 14b. FIG. 1
`illustrates that a dielectric layer 12 is generally used to
`electrically isolate one interconnect 14a from another inter-
`connect 14b within one metallic layer. Any one interconnect
`layer of an integrated circuit may contain millions of indi-
`viduals and segmented interconnects similar to 14a and 14b,
`and an integrated circuit may contain up to 8 or more stacked
`layers of interconnect metallurgy over
`the top of one
`another. In FIG. 1, interconnects such as 14a and 14b are
`generally formed as one of either tungsten
`plugs,
`tungsten local interconnects, aluminum wiring, inlaid cop-
`per interconnects, polysilicon regions, dual inlaid copper
`interconnects, composite metallic contacts, and/or like inte—
`grated circuit conductive members. In addition, various
`dielectric layers taught herein, such as dielectric layer 12,
`are usually one or more of tetraethelorthosilicate (TEOS),
`fluorine doped TEOS (f—TEOS), low k dielectrics, borophos-
`phosilicate glass (BPSG), phosphosilicate glass (PSG), spin
`on glasses (SOG), silicon nitride layers, metal oxides, air
`gaps, composites thereof, and/or like dielectric regions.
`FIG. 1 illustrates that a dielectric stack 13 is formed over
`
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`
`a top of the interconnects 14a and 14b and a top of the
`dielectric layer 12. Generally, a dielectric stack is any
`vertically stacked combination of two or more different
`dielectric materials. Specifically, FIG. 1 illustrates a dielec-
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`US 6,326,301 B1
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`10
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`7
`of the structure when using lithographic wavelengths of 365
`nanometers (I-line)
`for photoresist processing over the
`dielectric stack 13. It should be understood that different
`thicknesses will result when different lithographic wave-
`lengths are used, different material compositions are
`selected, different thicknesses of material are deposited,
`diiferent interfaces are created, different chemical composi-
`tions are formed, and/or the like.
`After formation of the layer 18, an etch stop layer 20 is
`deposited over the layer 18 and the dielectric stack 13.
`Generally, the layer 20 is chosen as any layer that can be an
`etch stop for
`the overlying layer 22. In addition,
`it
`is
`advantageous if the layer 20 prevents copper leakage.
`Further, the thickness and material composition of layer 20
`should be engineered to improve the optical properties of the
`overall structure 13. Since the layer 20 will generally be
`adjacent or in close proximity to the trench interconnect
`regions and since these trench interconnect regions are more
`closely spaced to each other via dimension C (see FIG. 5),
`the layer 20 of FIG. 1 needs to be electrically robust enough r
`to ensure low levels of leakage current. Further, an improved
`device is formed if the layer 20 has a dielectric constant and
`capacitive geometry that is conducive to higher frequencies
`of operation without adversely high parasitic capacitors
`and/or excessive cross talk.
`Amaterial that was found to provide a good trade off and
`balance among the above considerations was silicon-rich
`silicon oxynitride (Si—SiON). A silicon rich silicon oxyni-
`tride film provides an excellent antireflective coating (ARC)
`for improved optical properties and was also found to be an
`excellent etch stop layer for the overlying layer 22. In
`addition, the minimal surface area contacted the layer 20 to
`any subsequent metallurgy ensured that any reactions that
`could occur therebetween were of little impact to the overall
`performance of the device. It was found that the SiON layer
`
`8
`20 and the barrier materials of the copper interconnect, if
`they reacted with each other, did not result in unacceptable
`degradation in sheet resistance or unacceptable increase in
`line-to-line leakage current.
`Generally, a thickness of the silicon-rich SiON layer 20
`(Y-Z) is on the order of 600 angstroms for I-line lithographic
`processing. It is important to note that different thicknesses
`of layer 20 may be used and that different materials or
`composites of materials other than silicon-rich silicon oxyni-
`tride may be used for layer 20. For example, a thicker layer
`of stoichiometric silicon oxynitride may replace the silicon
`rich silicon oxynitride layer 20, but such a layer would likely
`need to be at least 1000 angstroms in thickness whereby etch
`throughput, leakage, etc. may be altered. Other composite
`materials and/or different thicknesses may be optimal in
`other circumstances where different materials are used for
`layers 18 and 22, different lithographic wavelengths are
`used, or different conditions apply. However, for the mate-
`rials discussed so far and for I-line lithography of 365
`nanometers, the 600 Angstroms silicon rich SiON layer is
`optimal with the above discussed layers 18 and 20.
`After formation of layer 20, a top layer 22 is formed as a
`top portion of the dielectric stack 13. Layer 22 is generally
`analogous to the layer 18 in term of material composition.
`However, the layer 22 is generally deposited to a thickness
`that is less than the layer 18. As shown in FIG. 1, various
`surfaces 16a, 16b, 20a and 20b must be adequately posi-
`tioned within the trench and subject to properly engineered
`indices of refraction in extinction coefficient values in order
`
`to improve the optical characteristics of the overall inter-
`connect structure. For this purpose, the layer 22 is generally
`a CVD TEOS layer that is roughly 4000—5000 angstroms in
`thickness.
`
`In summary of FIG. 1, an acceptable dielectric stack was
`found to be:
`
`Wavelength of Layer ID and
`Lithiography
`Material
`
`Thickness of Layer
`(range and target)
`
`I—line
`365 nm
`
`bottom etch
`stop 16
`(PEN layer)
`
`300—800
`Angstroms,
`500 Angstrom
`target
`
`6,000—10,000
`bottom
`dielectric layer Angstroms,
`18
`8,000 Angstrom
`(TEOS layer)
`target
`top etch stop
`300‘800
`layer 20
`Angstroms,
`(Si rich SiON)
`600 Angstrom
`target
`
`top dielectric
`layer
`(TEOS layer)
`
`bottom etch
`stop 16
`(PEN layer)
`
`3,000—6,000
`Angstroms,
`4,500 Angstrom
`target
`300—800
`Angstroms,
`500 Angstrom
`target
`
`6,000—10,000
`bottom
`dielectric layer Angstroms,
`18
`8,000 Angstrom
`(TEOS layer)
`target
`top etch stop
`300—800
`
`Deep UV
`248 nm
`
`TABLE 1
`
`Useful Process
`Information
`
`use a parallel plate
`RF reactor by
`Applied Materials,
`flow both SiH4 and
`NH4 at
`3700 C. to 4100 C.
`
`use a parallel plate
`RF reactor by
`Applied Materials,
`flow all of SiH4,
`N20, and NH4, at
`370° C. to 410° C.
`
`use a parallel plate
`RF reactor by
`Applied Materials,
`flow both SiH4 and
`NH4 at
`370° C. to 410° C.
`
`Refractive Index (N)
`
`Extinction
`Coefficient (K)
`
`1.5—3.0 with roughly
`2.3 being a target
`
`0.0 to 0.4 with
`0.027 being a target
`
`2074.0 with one of
`either 2.8 or 3.5
`being a target
`
`0.1 to 1.0 with one
`of either 0.3 or 0.7
`being a target
`
`1.0—3.0 with roughly
`2.1 being a target
`
`0.0 to 0.4 with 0.0
`being a target
`
`use a parallel plate
`
`2.0—4.0 with 2.5
`
`0.1 to 1.5 with 0.9
`
`

`

`US 6,326,301 B1
`
`10
`
`\Vavelength of Layer ID and
`Lithiography
`Material
`
`Thickness of Layer Useful Process
`(range and target)
`Information
`
`Refractive Index (N)
`
`Extinction
`Coefficient
`
`TABLE 1-continned
`
`being a target
`
`being a target
`
`layer 20
`(Si rich SiON)
`
`Angstroms,
`600 Angstrom
`target
`
`top dielectnc
`layer
`(TEOS layer)
`
`3,000—6,000
`Angstroms,
`4,500 Angstrom
`target
`
`RF reactor by
`Applied Materials,
`flow all of SiH4,
`N20, and NH4, at
`3700 C. to 4100 C.
`
`15
`
`In addition, stoichiometric SION may be used in place of
`the silicon-rich SiON if formed to thicknesses above 1000
`Angstroms with an N value of roughly 1.6 and a K value of
`roughly 0.0 at I-line (365 nm) lithographic exposure. Sto-
`ichiometric SiON when exposed with Deep UV was similar ,
`except that N was roughly 1.7 and K was roughly 0.03.
`FIG. 2 illustrates that a photoresist layer 24 is spin coated
`or deposited over a top of the layer 22. A lithography mask
`is then placed between a light source or energy source and
`the photoresist 24. Energy or light is then passed selectively
`through the mask or altered by the mask to selectively
`expose portions of the photoresist 24. Generally, this expo-
`sure is I-line exposure at 365 nanometers. However, other
`lithographic processes such as deep UV at 248 nanometers,
`phase shift lithography, x—ray, SCALPEL, or other litho—
`graphic wavelengths or processing may be used.
`As previously stated, changes in the lithography process
`may require changes in the thicknesses, materials,
`placement, or processing of the dielectric stack 13 to further
`optimize the stack 1