`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
`Petitioner
`
`v.
`
`GODO KAISHA IP BRIDGE 1
`Patent Owner.
`
`Case IPR2017-01843
`
`DECLARATION OF STANLEY R. SHANFIELD, PH.D.
`REGARDING U.S. PATENT NO. 7,893,501
`CLAIMS 1, 4-5, 7, 9-11, 15-18, and 23-25 (Petition #3)
`
`TSMC 1202
`
`
`
`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`TABLE OF CONTENTS
`
`Page
`BACKGROUND ............................................................................................... 1
`I.
`II. LEGAL PRINCIPLES ...................................................................................... 7
`III. PERSON OF ORDINARY SKILL IN THE ART .......................................... 10
`IV. TECHNOLOGY BACKGROUND ................................................................ 11
`V. OVERVIEW OF THE ’501 PATENT ............................................................ 19
`A.
`Priority Date of the ’501 Patent........................................................... 28
`B.
`Summary of the Prosecution History .................................................. 28
`VI. CLAIM CONSTRUCTION ............................................................................ 30
`VII. GROUNDS FOR FINDING THE CHALLENGED CLAIMS INVALID ..... 30
`A. Ground 1: Claims 1, 4-5, 7, 9-11, 15-18, and 23-25 are rendered
`obvious by Misra in view of Tsai ........................................................ 30
`1.
`Independent Claim 1 ................................................................. 31
`2.
`Dependent Claim 4 ................................................................... 56
`3.
`Dependent Claim 5 ................................................................... 58
`4.
`Dependent Claim 7 ................................................................... 63
`5.
`Dependent Claim 9 ................................................................... 65
`6.
`Dependent Claim 10 ................................................................. 67
`7.
`Dependent Claim 11 ................................................................. 69
`8.
`Dependent Claim 15 ................................................................. 71
`9.
`Dependent Claim 16 ................................................................. 71
`10. Dependent Claim 17 ................................................................. 73
`11. Dependent Claim 18 ................................................................. 75
`12. Dependent Claim 23 ................................................................. 77
`13. Dependent Claim 24 ................................................................. 78
`14. Dependent Claim 25 ................................................................. 82
`VIII. AVAILABILITY FOR CROSS-EXAMINATION ........................................ 84
`IX. RIGHT TO SUPPLEMENT ............................................................................ 84
`X.
`JURAT ............................................................................................................. 85
`
`i
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`I, Stanley R. Shanfield, Ph.D., declare as follows:
`
`1. My name is Stanley R. Shanfield.
`
`I.
`
`BACKGROUND
`2.
`I am a Distinguished Member of Technical Staff and Technical
`
`Director in Advanced Hardware Development at the Charles Stark Draper
`
`Laboratory (“Draper Laboratory”) in Cambridge, Massachusetts.
`
`3.
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`I received a B.S. in Physics from the University of California, Irvine
`
`in 1977, Phi Beta Kappa. In 1975, I received the University of California Regents
`
`Award for Outstanding Research Project for my experimental and theoretical work
`
`on rotating relativistic electron beams. Under full Energy Research and
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`Development Administration (DOE) scholarship, I received a Ph.D. in Physics
`
`from the Massachusetts Institute of Technology in 1981.
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`4.
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`After receiving my doctorate degree, I worked at Spire Corporation in
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`Bedford, Massachusetts from 1981-1984, where I served as a Staff Scientist, and
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`later, a Senior Staff Scientist. At Spire, I developed a new method of plasma-
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`assisted CVD epitaxial silicon for low temperature semiconductor processing. In
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`addition, I built, operated, and characterized an ion-assisted deposition system for
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`making semiconductor coatings.
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`5.
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`From 1985-1999, I worked at Raytheon Corporation. In my early
`
`years at Raytheon, I was a staff member, then Section Manager for
`
`1
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`Semiconductors and Integrated Circuits. My work focused primarily on designs,
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`layout and fabrication technology for CMOS silicon and MISFET GaAs integrated
`
`circuits. I developed thin film, dry etch and photolithographic processes for
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`fabricating high frequency multi-function integrated circuits. In one major design
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`and fabrication program, I combined high performance CMOS digital and analog
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`devices in a family of integrated circuits designs for a phased array radar system. I
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`was responsible for developing a power MOSFET process sequence later used in a
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`variety of Raytheon products. From 1992-1996, I served as a Research Laboratory
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`Manager at Raytheon, and became responsible for semiconductor materials, wafer
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`fab, testing, and some of the IC design and layout center. I led a 90 employee
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`organization in work related to high-performance semiconductor devices and
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`integrated circuits, advanced measurement and modeling, and state-of-the-art
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`CMOS wafer fabrication. I led a team that invented and implemented a major
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`revenue-generating technology ($100 million) based on a novel semiconductor
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`device, specifically, a pseudomorphic high electron mobility transistor.
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`6.
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`In 1996, I became the Manager of Semiconductor Operations at
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`Raytheon Commercial Electronics. As Manager, I built and led a 300 employee,
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`$60 million revenue-generating semiconductor development, commercial circuit
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`design, and electronic module manufacturing operation. My group developed the
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`first Iridium handset electronic modules, designed and built chips and supplied
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`2
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`circuit board assemblies for AT&T wireless base stations. I was heavily involved
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`as a decision-maker in Raytheon’s acquisition of a design and wafer fab group at
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`Texas Instruments, providing significant expert opinion on semiconductor, printed
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`circuit board assembly and design facilities. I was involved in setting up
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`packaging, assembly and test operations in South Korea, and was directly involved
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`in electronics package design and characterization.
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`7.
`
`From 1999-2001, I worked at AXSUN Technologies as part of the
`
`founding team, first as the Director of Manufacturing & Wafer Fab Technology,
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`and later, as the Vice President of Operations. As Director of Manufacturing &
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`Wafer Fab Technology, I led device and module manufacturing, creating a wafer
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`fab and circuit board assembly infrastructure; my responsibilities included hiring
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`over 70 individuals and leading production design efforts. In my role as Vice
`
`President of Operations, I designed, fabricated, and productized AXSUN’s
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`microelectromechanical (MEM) Fabry-Perot optical filter, and managed a new
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`generation of electronics module design. In addition, I established a process and
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`fabrication facility in Belfast, Northern Ireland for producing thick oxide silicon-
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`on-insulator devices. As a result of my work at AXSUN, I was awarded patents on
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`semiconductor processing and control electronics. This company was eventually
`
`sold.
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`3
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`I have served since 2003 at the Draper Laboratory, ultimately
`
`8.
`
`becoming a Distinguished Member of Technical Staff and Technical Director in
`
`Advanced Hardware Development. I led the Advanced Hardware Development
`
`Division (approximately 80 staff) in their work on the laboratory’s multi-chip
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`integrated circuit and module facility. I have been the technical leader for
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`numerous micro-electronics-related programs, typically involving integrated circuit
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`processing technology, circuit design and layout, circuit modeling, wafer
`
`fabrication (foundry and in-house), packaging and test. For example, I developed a
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`new concept for miniature, extremely stable frequency source chip set and led the
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`successful design, layout, and testing efforts. I was responsible for the design,
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`fabrication and testing of an experimental direct digital receiver system using time-
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`of-flight telemetry. I led a study evaluating state-of-the-art memory design and
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`fabrication technology, focusing on reduced operating power.
`
`9.
`
`I have received awards and recognition for my work, including the
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`Draper 2010 Distinguished Performance Award and the 2010 Best Patent Award
`
`for “Systems and Methods for High Density Multi-Component Electronic
`
`Modules.”
`
`10.
`
`I have authored more than 25 journal and conference papers; my
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`publications include numerous papers on topics relating to semiconductor
`
`processing, advanced semiconductor devices, electronic circuit design and
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`4
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`packaging. I have been invited to give professional talks at various conferences. In
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`1997, I gave an invited talk on “IC Technologies for Wireless Applications Beyond
`
`2000,” and received an Author’s award for work in that area.
`
`11.
`
`I am a co-inventor of seven U.S. Patents, including U.S. Patent No. 5,
`
`223,458, entitled “Method of Manufacturing a III-V Semiconductor Device Using
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`a Self-Biased Substrate and a Plasma Containing an Electronegative Species”
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`(issued June 29, 1993), and U.S. Patent No. 5,880,483, entitled “Semiconductor
`
`Devices” (issued March 9, 1999).
`
`12. A copy of my curriculum vitae is attached as Appendix A.
`
`13.
`
`I have reviewed the specification and claims of U.S. Patent No.
`
`7,893,501 (the “’501 patent”; Ex-1201). I have been informed that the ’501 patent
`
`claims priority to Application No. 11/730,988, filed on April 5, 2007, now U.S.
`
`Patent No. 7,417,289, which is a continuation of Application No. 10/859,219, filed
`
`on June 3, 2004, now U.S. Patent No. 7,205,615.
`
`14.
`
`I have also reviewed the following references, all of which I
`
`understand to be prior art to the ’501 patent:
`
` U.S. 5,960,270 (“Misra,” Ex-1204).
`
` U.S. 6,444,566 (“Tsai,” Ex-1215).
`15.
`I have been informed that Misra is prior art under 35 U.S.C. § 102(b)
`
`because it issued on September 28, 1999, which is more than a year before the
`
`5
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`earliest claimed U.S. filing date of the ’501 patent, which is June 3, 2004. I have
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`also been informed that Misra is also prior art under §102(a) and §102(e) because
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`it has a U.S. filing date August 11, 1997 and issued on September 28, 1999, which
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`are before the earliest claimed priority date of the ’501 patent, which is June 16,
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`2003 based on JP 2003-1700335.
`
`16.
`
`I have been informed that Tsai is prior art under 35 U.S.C. §102(b),
`
`because it issued on September 3, 2002, which is more than a year before the
`
`earliest claimed U.S. filing date of the ’501 patent, which is June 3, 2004. I have
`
`also been informed that Tsai is also prior art under §102(a) and §102(e) because it
`
`has a U.S. filing date of April 30, 2001, and issued on September 3, 2002, which
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`are before the earliest claimed priority date of the ’501 patent, which is June 16,
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`2003 based on JP 2003-1700335.
`
`17.
`
`I have been informed that Oda is prior art under 35 U.S.C. §102(b)
`
`because it issued on December 5, 1995, which is more than a year before the
`
`earliest claimed U.S. filing date of the ’501 patent, which is June 3, 2004. I have
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`also been informed that Oda is also prior art under 35 U.S.C. §102(a) and §102(e)
`
`because it has a U.S. filing date of April 26, 1995 and issued on December 5, 1995,
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`both of which are before the earliest claimed priority date of the ’501 patent, which
`
`is June 16, 2003 based on JP 2003-1700335.
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`6
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`I have been informed that Hokazono is prior art under 35 U.S.C.
`
`18.
`
`§102(b) because it published on January 3, 2002, which is more than a year before
`
`the earliest claimed U.S. filing date of the ’501 patent, which is June 3, 2004.
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`Hokazono is also prior art under 35 U.S.C. §102(a) and §102(e) because it has a
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`U.S. filing date of June 28, 2001 and was published on January 3, 2002, which are
`
`before the earliest claimed priority date of the ’501, which is June 16, 2003 based
`
`on JP 2003-1700335.
`
`19.
`
`In addition to the documents listed above, I have also reviewed the
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`file history of the ’501 patent and all of the documents listed in Petitioner’s List of
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`Exhibits in the accompanying petition.
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`20.
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`I am being compensated at my normal consulting rate for my work.
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`21. My compensation is not dependent on and in no way affects the
`
`substance of my statements in this Declaration.
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`22.
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`I have no financial interest in the Petitioner. I similarly have no
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`financial interest in the ’501 patent.
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`II. LEGAL PRINCIPLES
`23.
`I am not an attorney. For the purposes of this declaration, I have been
`
`informed about certain aspects of the law that are relevant to my opinions. My
`
`understanding of the law was provided to me by Petitioner’s attorneys.
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`7
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`I understand that prior art to the ’501 patent includes patents and
`
`24.
`
`printed publications in the relevant art that predate the priority date of the alleged
`
`invention recited in the ’501 patent. I have applied the date of June 16, 2003, the
`
`filing date of the foreign application to which the ’501 patent claims priority, as the
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`priority date, although the ’501 patent may actually not be entitled to such an early
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`priority date.
`
`25.
`
`I understand that a claim is unpatentable if it would have been obvious
`
`to a person of ordinary skill in the art at the time the alleged invention was made. I
`
`understand that a claim could have been obvious from a single prior art reference
`
`or from a combination of two or more prior art references.
`
`26.
`
`I understand that an obviousness analysis requires an understanding of
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`the scope and content of the prior art, any differences between the alleged
`
`invention and the prior art, and the level of ordinary skill in evaluating the
`
`pertinent art.
`
`27.
`
`I further understand that certain factors may support or rebut the
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`obviousness of a claim. I understand that such secondary considerations include,
`
`among other things, commercial success of the patented invention, skepticism of
`
`those having ordinary skill in the art at the time of invention, unexpected results of
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`the invention, any long-felt but unsolved need in the art that was satisfied by the
`
`alleged invention, the failure of others to make the alleged invention, praise of the
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`8
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`alleged invention by those having ordinary skill in the art, and copying of the
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`alleged invention by others in the field. I understand that there must be a nexus,
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`that is, a connection, between any such secondary considerations and the alleged
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`invention. I also understand that contemporaneous and independent invention by
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`others is a secondary consideration tending to show obviousness.
`
`28.
`
`I further understand that a claim would have been obvious if it unites
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`old elements with no change to their respective functions, or alters prior art by
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`mere substitution of one element for another known in the field, and that
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`combination yields predictable results. Also, I understand that obviousness does
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`not require physical combination/bodily incorporation, but rather consideration of
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`what the combined teachings would have suggested to persons of ordinary skill in
`
`the art at the time of the alleged invention.
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`29. While it may be helpful to identify a reason for this combination, I
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`understand that there is no rigid requirement of finding an express teaching,
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`suggestion, or motivation to combine within the references. When a product is
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`available, design incentives and other market forces can prompt variations of it,
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`either in the same field or a different one. If a person of ordinary skill in the art
`
`can implement a predictable variation, obviousness likely bars its patentability. For
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`the same reason, if a technique has been used to improve one device and a person
`
`of ordinary skill in the art would recognize that it would improve similar devices in
`
`9
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`the same way, using the technique would have been obvious. I understand that a
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`claim would have been obvious if a person of ordinary skill in the art would have
`
`had reason to combine multiple prior art references or add missing features to
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`reproduce the alleged invention recited in the claims.
`
`30.
`
`I am not aware of any allegations by the named inventors of the ’501
`
`patent or any assignee of the ’501 patent that any secondary considerations tend to
`
`rebut the obviousness of any claim of the ’501 patent discussed in this declaration.
`
`31.
`
`I understand that in considering obviousness, it is important not to
`
`determine obviousness using the benefit of hindsight derived from the patent being
`
`considered.
`
`32.
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`I understand that other challenges to the validity of a patent, including
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`patent ineligibility, enablement, written description, and definiteness, cannot be
`
`raised in IPR proceedings before the Board to challenge the validity of the ’501
`
`patent. Accordingly, I did not consider those other challenges.
`
`33. The analysis in this declaration is in accordance with the above-stated
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`legal principles.
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`III. PERSON OF ORDINARY SKILL IN THE ART
`34.
`I understand that the level of ordinary skill may be reflected by the
`
`prior art of record, and that a person of ordinary skill in the art to which the
`
`claimed subject matter pertains would have the capability of understanding the
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`10
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`scientific and engineering principles applicable to the pertinent art. I understand
`
`that one of ordinary skill in the art has ordinary creativity, and is not a robot.
`
`35.
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`I understand there are multiple factors relevant to determining the
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`level of ordinary skill in the art, including (1) the levels of education and
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`experience of persons working in the field at the time of the invention, (2) the
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`sophistication of the technology, (3) the types of problems encountered in the field;
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`and (4) the prior art solutions to those problems. There are likely a wide range of
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`educational backgrounds in the technology fields pertinent to the ’501 patent.
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`36. A technology field pertinent to the ’501 patent is semiconductor
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`manufacturing of integrated circuits. A person of ordinary skill in the art
`
`(“POSITA”) at the time of the alleged invention of the ’501 patent would have had
`
`the equivalent of a Master’s degree in electrical engineering, physics, chemistry,
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`materials science, or equivalent training, and two years of work experience in field
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`of semiconductor manufacturing. Additional graduate education could substitute
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`for work experience, and additional work experience/training could substitute for
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`formal education. As described in more detail above, I would have been a person
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`with at least ordinary skill in the art of the ’501 patent as of the time of its alleged
`
`invention.
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`IV. TECHNOLOGY BACKGROUND
`
`11
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`37. The challenged claims relate to semiconductor devices, which existed
`
`long before the filing of the application that became the ’501 patent. The claims
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`recite features that were standard to many, if not all, MISFET transistors, such as
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`an active region made of a semiconductor substrate, a gate insulating film, a gate
`
`electrode, source/drain regions, and a silicon nitride film.
`
`38. Metal-insulator-semiconductor field effect transistors (MISFETs) with
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`standard features claimed in the ’501 patent, were first developed long before the
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`’501 patent. The small size of MISFETs as compared with prior vacuum tube
`
`technologies helped enable much of the modern computer and electronics industry
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`that developed from the 1970s and 1980s through the present.
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`39. MOS transistors are a type of MISFET where the insulating film is an
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`oxide, such as silicon dioxide or silicon oxynitride. MOS transistors are by far the
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`most common type of MISFET. The figure below shows an example of a
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`MISFET, and more particularly, a MOS transistor. Single crystal silicon is a
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`semiconductor, and can be “doped” to become a conductor with a preponderance
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`of negative charge carriers (n-type) or a preponderance of positive charge carriers
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`(p-type). The layers containing dopant materials such as arsenic or phosphorous
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`are sometimes described as “impurity diffusion layers.” This term refers to the
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`addition of the dopant (“impurity”) and subsequent high temperature diffusion of
`
`impurity atoms in the pure silicon crystal. One very useful three-electrode device
`
`12
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`is a Metal-Insulator-Semiconductor Field Effect Transistor, commonly known as a
`
`“MISFET,” which can be formed on the surface of a single crystal silicon substrate
`
`(see figure below). In a MISFET, current flowing between two electrodes in
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`electrical contact with a doped silicon layer (these contacts are called “source” and
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`“drain”) can be controlled by the voltage on a third electrode called a “gate”
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`electrode. The gate electrode is separated by a thin insulating layer from the
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`current-carrying layer of silicon. The gate electrode draws almost no current. At
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`the time the application that led to the ’501 patent was filed, the most commonly
`
`used insulator separating the gate electrode from doped semiconductor was silicon
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`dioxide (SiO2). The SiO2 was typically grown directly on silicon by oxidizing the
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`surface at high temperature in the presence of water vapor.
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`13
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`Fig. 1. Cross-sectional view of NMOS and PMOS devices1
`40. This type of SiO2 is called thermally-grown oxide, or simply “thermal
`
`oxide,” to distinguish it from the same material deposited by chemical vapor
`
`deposition, sputtering, or some other method. Devices using a silicon dioxide gate
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`insulator are called Metal-Oxide-Semiconductor-Field-Effect-Transistors,
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`“MOSFETs” or “MOS” transistors. MOSFETs are a type of MISFET. The region
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`between the source and drain electrodes where current flows is called the channel
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`region (also shown in Fig. 1 above), and a process that combines MOSFETs with
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`p-doped channels and MOSFETs with n-doped channels is referred to as a
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`Complementary-Metal-Oxide-Semiconductor Process or CMOS process. CMOS
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`circuits have advantages over circuits using just one doping type MOSFET (i.e.
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`only n-type MOSFETs or only p-type MOSFETs). The most important advantages
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`of using CMOS in circuit designs are reduced power consumption, and reduced
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`electrical noise.
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`41. Fig. 1 (above) shows a cross section of a MISFET, and more
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`particularly, a well-known n-channel MOSFET (NMOS) and an adjacent p-
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`channel MOSFET (PMOS) device, with labels highlighting all important regions in
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`1 Fig. 1 was taken from Plummer et al., Silicon VLSI Technology: Fundamentals,
`
`Practice and Modeling, at 86 (1st ed. 2000) (Ex-1209). Color and labels were
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`added to facilitate the description.
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`14
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`these devices. To reduce clutter in the diagram, some labels shown on just the
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`NMOS or just the PMOS device in Fig. 1 also apply to the complementary device.
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`MISFETs include active regions made of a semiconductor substrate. The active
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`regions of each device are found between the “shallow trench isolation” (STI),
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`shown as grey regions in Fig. 1. (See J. Rabaey et al., Digital Integrated Circuits,
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`at 42-43 (2d ed. 2003) (“Rabaey”) (Ex-1211).) The active regions are where the
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`transistors are formed and are present in every transistor. (Id. at 42.) The source
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`and drain regions (green), the channel (area between the source and drain regions),
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`and the well (“N Well” and “P Well”) are formed in regions of the active regions.
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`Active areas in transistors are so well-known that they are usually not labeled in
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`transistor drawings. The gate electrode (orange) is formed above the channel.
`
`42. The STI are formed using the trench method. Prior to the adoption of
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`shallow trench isolation (STI), Local Oxidation of Silicon or “LOCOS” was the
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`most common method of electrically isolating individual devices in silicon
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`semiconductor chips. Although effective in creating electrical isolation, the
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`LOCOS method used a significant fraction of the integrated circuit area, and the
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`process could not be easily scaled to smaller dimensions. Manufacturers
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`eventually found that shallow trench isolation geometry could be easily scaled to
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`smaller area along with shrinking device dimensions without compromising
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`electrical isolation. Since smaller isolation regions allowed higher device density
`
`15
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`circuits, STI was rapidly adopted by semiconductor chip manufacturers in the early
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`1990s. The STI process surrounds each electrically active device with narrow
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`trenches cut into the silicon substrate. After formation, the trench surfaces are
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`briefly exposed to high temperature and oxygen, creating a thin silicon dioxide
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`layer which partially fills the trench. The remaining space in the trenches is filled
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`with deposited silicon dioxide. Although narrow, the trenches surround each
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`electrically active device on the chip, providing isolation in preventing the flow of
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`electrical current between devices.
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`43. Returning to the annotated figure above, the gate electrode (orange) is
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`separated from the channel by an insulating film (red). The doped regions of the
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`source and drain regions (green) are formed by doping the substrate with
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`impurities. It was common and conventional for source and drain regions (green)
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`to have a lightly-doped region, a heavily doped region, and a silicide film, as
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`shown in Fig. 1 above. The lightly-doped and heavily doped regions are
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`sometimes referred to as LDD (lightly-doped drain) and HDD (heavily-doped
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`drain), although it is understood that both the source and drain are lightly and
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`heavily doped.
`
`44. The source and drain contacts are formed with a metal silicide, which
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`is an electrically conductive metal-silicon compound. The silicide source and
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`drain layers are in electrical contact with a shallow, heavily doped (highly
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`conductive) semiconductor region, connected to a lightly doped region near the
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`gate. This two level doping structure is called a “lightly doped drain” (LDD)
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`structure, although LDD also implies a symmetric, lightly doped source layer. The
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`LDD structure allowed the NMOS and PMOS devices to be dramatically reduced
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`in size while minimizing “short channel effects” that occur as dimensions are
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`reduced. One important such short channel effect, called “hot electron injection,”
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`results in unstable MOSFET electrical characteristics, and is caused by an increase
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`in the number of very energetic electrons (hot electrons) generated as device size is
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`reduced. The LDD doping structure is most easily fabricated using a gate spacer,
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`shown as the labelled dark blue region immediately surrounding each gate in Fig.
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`1—first the LDD doping, second the formation of the gate spacer, and third the
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`HDD doping using the gate spacer as a mask. The spacer dimensions help control
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`the doping level introduced by ion implantation (high energy implantation) of
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`dopant atoms near each gate. The use of a gate with a gate spacer to align the
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`source and drain implants and contact metal is sometimes called “self-aligned
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`contacts” or “SAC.” The term “self-aligned” is used because the process aligns the
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`gate, the contact metal, and the contact implants to each other.
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`45. The gate electrodes (orange) shown in Fig. 1 consist of two layers,
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`and this layered structure was typical of state-of-the-art MOSFETs at the time the
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`initial ’501 patent application was filed. The topmost layer of the gate is a metal
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`silicide, usually of the same composition as the silicide used to form the source and
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`drain contacts. The lower layer of the gate electrode can be made of materials such
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`as a highly doped polysilicon (i.e., polycrystalline silicon) or a metal. The top
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`layer of metal silicide is considerably more electrically conductive than the
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`underlying polysilicon, and this characteristic is a key benefit in reducing the
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`overall gate electrode resistance. 2 The gate insulator (red) can be made of
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`materials such as thermally-grown silicon dioxide (SiO2) or silicon oxynitride
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`(SiOxNy). The polysilicon (underneath the metal silicide) was advantageous in the
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`gate structure because it forms an electrically favorable interface with the top side
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`of the gate insulator. However, polysilicon is more resistive than metal, and
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`polysilicon forms a depletion region that effectively increases the gate insulator
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`thickness. Since thinner gate insulator was required for further reduction in
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`MOSFET size, the depletion region was an undesirable feature of the polysilicon.
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`46. Silicon dioxide (SiO2), grown thermally forms a nearly ideal (stable,
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`almost charge-free) interface with the underlying doped silicon layer carrying
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`current between the source and the drain. Silicon dioxide was well established as
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`an extremely reliable gate insulating layer, and nearly all MISFETs produced at the
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`time used thermally grown SiO2 as the gate insulator. However, gate insulating
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`2 For historical reasons, the term “MOSFET” refers to both devices with
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`polysilicon/silicide gates and devices with metal gates.
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`materials with a higher dielectric constant, called “high-k” dielectrics, were known
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`at the time to be needed for MISFETs with extremely small gate dimensions (tens
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`of nm). At the time, those skilled in the art were aware that an all-metal gate
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`would work more advantageously than a silicide/polysilicon gate with a high-k
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`dielectric gate insulator.
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`47. Silicon nitride films were commonly included over the source and
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`drain regions (green) in MISFET devices, with the gate electrode (orange)
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`protruding above the silicon nitride film long before the alleged invention of the
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`’501 patent. (E.g., Igarashi at [0117-0118], Fig. 12 (Ex-1207); Misra at 5:52-55;
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`6:67-7:15 (describing formation of protruding gate illustrated in Fig. 7), Fig. 7 (Ex-
`
`1204).) Silicon nitride films were commonly used for applications like etch stops.
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`(E.g., Igarashi at [0047] (etch stop) (Ex-1207); Misra at 5:24-27 (etch stop) (Ex-
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`1204).) Etch stops are included to control the etching process during
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`manufacturing. The use of silicon nitride films in MISFET devices and design
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`choices about what portions of the device to cover and how to locate the height of
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`the gate relative to the nitride film were well understood before the alleged
`
`invention of the ’501 patent.
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`V. OVERVIEW OF THE ’501 PATENT
`48. The challenged claims are directed to a transistor with the standard
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`structures of conventional MISFETs at the time. As depicted in Figure 1 of the
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`’501 patent, reproduced below, the claimed device of the ’501 patent includes: (1)
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`an active region 1a made of a