US007893501B2
`
`(12) United States Patent
`Tsutsui et al.
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 7,893,501 B2
`*Feb. 22, 2011
`
`(54)
`
`(75)
`
`SEMICONDUCTOR DEVICE INCLUDING
`MISFET HAVING INTERNAL STRESS FILM
`
`(56)
`
`Inventors: Masafumi Tsutsui, Osaka (JP);
`Hiroyuki Umimoto, Hyogo (JP); Kaori
`Akamatsu, Osaka (JP)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,023,676 A
`
`6/1991 Tatsuta
`
`(73)
`
`Assignee: Panasonic Corporation, Osaka (JP)
`
`(*)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`This patent is subject to a terminal dis
`claimer.
`
`(21)
`
`(22)
`
`(65)
`
`(63)
`
`Appl. No.: 12/170,191
`
`Filed:
`
`Jul. 9, 2008
`
`Prior Publication Data
`
`US 2009/0050981 A1
`
`Feb. 26, 2009
`
`Related US. Application Data
`
`Continuation of application No. 11/730,988, ?led on
`Apr. 5, 2007, noW Pat. No. 7,417,289, Which is a con
`tinuation of application No. 10/859,219, ?led on Jun.
`3, 2004, noW Pat. No. 7,205,615.
`
`(Continued)
`FOREIGN PATENT DOCUMENTS
`
`JP
`
`52-120776
`
`10/1977
`
`(Continued)
`OTHER PUBLICATIONS
`
`ShimiZu, A., et 31., “Local Mechanical-Stress Comtrol (LMC): A
`New Technique for CMOSfPerformance Enhancement”, 2001,
`IEDM 01, p. 19.41-19.44.
`
`(Continued)
`Primary ExamineriHoWard Weiss
`(74) Attorney, Agent, or FirmiMcDermott Will & Emery
`LLP
`
`(57)
`
`ABSTRACT
`
`(30)
`Jun.
`
`Foreign Application Priority Data
`
`16, 2003
`
`(JP)
`
`........................... .. 2003-170335
`
`(51)
`
`(52)
`(58)
`
`Int. Cl.
`(2006.01)
`H01L 29/76
`(2006.01)
`H01L 29/94
`(2006.01)
`H01L 31/062
`(2006.01)
`H01L 31/113
`(2006.01)
`H01L 31/119
`US. Cl. .................................................... .. 257/369
`
`Field of Classi?cation Search ................ .. 257/369
`See application ?le for complete search history.
`
`A semiconductor device includes a ?rst-type internal stress
`?lm formed of a silicon oxide ?lm over source/drain regions
`of an nMISFET and a second-type internal stress ?lm formed
`of a TEOS ?lm over source/drain regions of a pMISFET. In a
`channel region of the nMISFET, a tensile stress is generated
`in the direction of movement of electrons due to the ?rst-type
`internal stress ?lm, so that the mobility of electrons is
`increased. In a channel region of the pMISFET, a compressive
`stress is generated in the direction of movement of holes due
`to the second-type internal stress ?lm, so that the mobility of
`holes is increased.
`
`25 Claims, 9 Drawing Sheets
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`

`US 7,893,501 B2
`Page 2
`
`US. PATENT DOCUMENTS
`
`6,437,404 B1* 8/2002
`6,573,172 B1
`6/2003
`6,870,230 B2* 3/2005
`6,977,194 B2 12/2005
`6,982,465 B2
`1/2006
`7,022,561 B2
`4/2006
`7,205,615 B2* 4/2007
`7,417,289 B2* 8/2008
`2003/0040158 A1
`2/2003
`2004/0075148 A1
`4/2004
`
`Xiang et al. .............. .. 257/347
`En et a1.
`
`Matsuda et al. ........... .. 257/365
`Belyansky et a1.
`Kumagai et al.
`Huang et al.
`
`Tsutsui et a1. ............. .. 257/369
`
`Tsutsui et a1. ............. .. 257/369
`Saitoh
`Kumagai et al.
`
`JP
`JP
`JP
`JP
`
`9/2005 Chan et a1.
`2005/0194596 A1
`FOREIGN PATENT DOCUMENTS
`60-236209
`11/1985
`01-042840 A
`2/1989
`2003-086708
`3/2003
`2004-193166
`7/2004
`OTHER PUBLICATIONS
`Japanese Of?ce Action, With English translation, issued in Japanese
`Patent Application No. 2003-170335, mailed Dec. 22, 2009.
`Japanese Of?ce Action, With English translation, issued in Japanese
`Patent Application No. 2003-170335, mailed Mar. 23, 2010.
`* cited by examiner
`
`

`

`US. Patent
`U.S. Patent
`
`Feb. 22, 2011
`Feb. 22, 2011
`
`Sheet 1 019
`Sheet 1 019
`
`US 7,893,501 B2
`US 7,893,501 B2
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`US. Patent
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`Feb. 22, 2011
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`Sheet 2 of9
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`US 7,893,501 B2
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`US. Patent
`
`Feb. 22, 2011
`
`Sheet 3 of9
`
`US 7,893,501 B2
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`FIG. 3A
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`U.S. Patent
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`Feb. 22, 2011
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`US 7,893,501 B2
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`US. Patent
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`Feb. 22, 2011
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`Sheet 5 of9
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`US 7,893,501 B2
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`US. Patent
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`Feb. 22, 2011
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`US. Patent
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`Feb. 22, 2011
`
`Sheet 8 0f 9
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`US 7,893,501 B2
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`US. Patent
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`Feb. 22, 2011
`
`Sheet 9 of9
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`US 7,893,501 B2
`
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`

`

`US 7,893,501 B2
`
`1
`SEMICONDUCTOR DEVICE INCLUDING
`MISFET HAVING INTERNAL STRESS FILM
`
`RELATED APPLICATIONS
`
`This application is a Continuation of US. application Ser.
`No. 11/730,988, ?ledApr. 5, 2007, now US. Pat. No. 7,417,
`289, Which is a Continuation of US. application Ser. No.
`10/859,219, ?led Jun. 3, 2004, now US. Pat. No. 7,205,615,
`and claiming priority of Japanese Application No. 2003
`170335, ?led Jun. 16, 2003, the entire contents of each of
`Which are hereby incorporated by reference.
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to a semiconductor device
`including an MISFET and a method for fabricating the same,
`and more particularly relates to a measure for increasing the
`mobility of carriers.
`When a stress is generated in a semiconductor crystal layer,
`a crystal-lattice constant varies and a band structure is
`changed, so that the mobility of carriers is changed. This
`phenomenon has been knoWn as the “pieZo resistivity effect”.
`Whether the carrier mobility is increased or reduced differs
`depending on the plane direction of a substrate, the direction
`in Which carriers move, and Whether the stress is a tensile
`stress or a compressive stress. For example, in an Si (100)
`substrate, i.e., a silicon substrate of Which the principal sur
`face is the {100} plane, assume that carriers move in the [01 1]
`direction. When carriers are electrons, With a tensile stress
`generated in the direction in Which electrons in a channel
`region move, the mobility of the carriers is increased. On the
`other hand, When carriers are holes, With a compressive stress
`generated in the direction in Which holes in a channel region
`move, the mobility of the carriers is increased. The increase
`rate of carrier mobility is proportional to the siZe of a stress.
`In this connection, conventionally, there have been propos
`als for increasing carrier mobility by applying a stress to a
`semiconductor crystal layer to increase the operation speed of
`transistors and the like. For example, in Reference 1 , an entire
`semiconductor substrate is bent using an external device,
`thereby generating a stress in an active region of a transistor.
`
`SUMMARY OF THE INVENTION
`
`HoWever, in the above-described knoWn structure, an
`external device is needed in addition to a semiconductor
`substrate and a stress can be generated only in the same
`direction in an entire region of the semiconductor substrate in
`Which active regions of a transistor and the like are provided
`and Which is located in the principal surface side. For
`example, When an Si (100) substrate is used, neither the
`mobility of electrons nor the mobility of holes can be
`increased.
`It is therefore an object of the present invention to provide,
`by generating a stress Which increases the mobility of carriers
`in a semiconductor layer Without using an external device, a
`semiconductor device including a pMISFET and an nMIS
`FET of Which respective operation speeds are increased and a
`method for fabricating the same.
`A semiconductor device according to the present invention
`includes an internal stress ?lm for generating a stress in a gate
`length direction in a channel region of an active region in
`Which a MISFET is formed.
`Thus, the mobility of carriers in the MISFET can be
`increased by using the pieZo resistivity effect.
`
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`The internal stress ?lm is capable of covering one or both
`of source/drain regions. In an nMISFET, the internal stress
`?lm generates a tensile stress substantially in the parallel
`direction to a gate length direction in a channel region (i.e.,
`the direction of movement of electrons). In a pMISFET, the
`internal stress ?lm generates a compressive stress substan
`tially in the parallel direction to a gate length direction in a
`channel region (i.e., the direction of movement of holes).
`Covering both side surfaces or both side and upper surfaces
`of a gate electrode, the internal stress ?lm can generate a
`stress in the longitudinal direction of the channel region
`through the gate electrode, thereby increasing the mobility of
`carriers.
`Moreover, covering a side surface of the gate electrode and
`an upper surface of the semiconductor substrate in tWo
`regions of the substrate sandWiching part of the gate elec
`trode, Whether the MISFET is an nMISFET or a pMISFET,
`the internal stress ?lm can generate a tensile stress substan
`tially in the parallel direction to the gate Width direction of the
`MISFET, thereby increasing the mobility of carriers.
`A ?rst method for fabricating a semiconductor device
`according to the present invention is a method in Which an
`nMISFET and a pMISFET are formed in ?rst and second
`active regions of a semiconductor substrate, respectively, and
`then ?rst and second internal stress ?lms Which cover source/
`drain regions of the nMISFET and source/ drain regions of the
`pMISFET, respectively, and generate a tensile stress and a
`compressive stress, respectively, substantially in the parallel
`directions to respective gate length directions of the channel
`regions are formed.
`According to this method, a CMOS device of Which the
`operation speed is increased can be obtained.
`A second method for fabricating a semiconductor device
`according to the present invention is a method in Which an
`internal stress ?lm is formed ?rst, a groove is formed in the
`internal stress ?lm, a gate insulating ?lm and a buried gate
`electrode are formed in the groove, and then the internal stress
`?lm is removed.
`According to this method, a stress Which increases the
`mobility of carriers in the channel region can be generated
`using a remaining stress in the gate insulating ?lm.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a cross-sectional vieW illustrating a semiconduc
`tor device according to a ?rst embodiment of the present
`invention.
`FIG. 2A through 2C are cross-sectional vieWs illustrating
`?rst half of respective steps for fabricating the semiconductor
`device of the ?rst embodiment.
`FIG. 3A through 3C are cross-sectional vieWs illustrating
`latter half of respective steps for fabricating the semiconduc
`tor device of the ?rst embodiment.
`FIGS. 4A through 4C are cross-sectional vieWs illustrating
`?rst, second and third modi?ed examples of the ?rst embodi
`ment.
`FIGS. 5A through 5D are cross-sectional vieWs illustrating
`respective steps for fabricating a semiconductor device
`according to the ?rst modi?ed example of the ?rst embodi
`ment.
`FIGS. 6A through 6C are cross-sectional vieWs illustrating
`respective steps for fabricating a semiconductor device
`according to the third modi?ed example of the ?rst embodi
`ment.
`
`

`

`US 7,893,501 B2
`
`3
`FIGS. 7A through 7D are cross-sectional vieWs illustrating
`?rst half of respective steps for fabricating a semiconductor
`device according to a second embodiment of the present
`invention.
`FIGS. 8A through 8D are cross-sectional vieWs illustrating
`latter half of respective steps for fabricating the semiconduc
`tor device of the second embodiment.
`FIGS. 9A and 9B are a plane vieW of an MISFET of a
`semiconductor device according to a third embodiment of the
`present invention and a cross-sectional vieW illustrating a
`cross-sectional structure taken along the line IX-IX (a cross
`section in the gate Width direction), respectively.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`First Embodiment
`
`FIG. 1 is a cross-sectional vieW illustrating a semiconduc
`tor device according to a ?rst embodiment of the present
`invention. As shoWn in FIG. 1, a surface region of a semicon
`ductor substrate 1, i.e., an Si (100) substrate is divided into a
`plurality of active regions 1a and 1b by an isolation region 2.
`The semiconductor device includes an nMISFET formation
`region Rn Which includes the active region 111 and in Which an
`nMISFET is to be formed and a pMISFET formation region
`Rp Which includes the active region 1b and in Which a pMIS
`PET is to be formed.
`The nMISFET includes n-type source/drain regions 3a and
`411 each of Which includes an n-type lightly doped impurity
`region, an n-type heavily doped impurity region and a silicide
`layer such as a CoSi2 layer, a gate insulating ?lm 5 formed on
`the active region 111 and made of a silicon oxide ?lm, a silicon
`oxynitride ?lm or the like, a gate electrode 611 formed on the
`gate insulating ?lm 5 and made of polysilicon, aluminum or
`the like, and a sideWall 7 covering a side surface of the gate
`electrode 611 and made of an insulating ?lm. Part of the active
`region 111 located under the gate electrode 611 is a channel
`region 1x in Which electrons move (travel) When the nMIS
`FET is in an operation state.
`The pMISFET includes p-type source/drain regions 3b and
`4b each of Which includes a p-type lightly doped impurity
`region, a p-type heavily doped impurity region and a silicide
`layer such as a CoSi2 layer, a gate insulating ?lm 5 formed on
`the active region 1b and made of a silicon oxide ?lm, a silicon
`oxynitride ?lm or the like, a gate electrode 6b formed on the
`gate insulating ?lm 5 and made of polysilicon, aluminum or
`the like, and a sideWall 7 covering a side surface of the gate
`electrode 6b and made of an insulating ?lm. Part of the active
`region 1b located under the gate electrode 6b is a channel
`region ly in Which holes move (travel) When the pMISFET is
`in an operation state.
`Moreover, provided are a ?rst-type internal stress ?lm 811
`formed on the source/drain regions 3a and 4a of the nMIS
`FET, made of a silicon nitride ?lm or the like, and having a
`thickness of about 20 nm, a second-type internal stress ?lm 8b
`formed on the source/drain regions 3b and 4b of the pMIS
`FET, made of a TEOS ?lm or the like, and having a thickness
`of about 20 nm, an interlevel insulating ?lm 9 covering the
`nMISFET and pMISFET and having a surface ?attened, a
`lead electrode 10 formed on the interlevel insulating ?lm 9,
`and a contact 11 connecting each of the source/drain regions
`3a, 3b, 4a and 4b With the lead electrode 10 through the
`interlevel insulating ?lm 9.
`Herein, an “internal stress ?lm” is a ?lm characterized in
`that Where the internal stress ?lm is directly in contact With
`some other member or faces some other member With a thin
`
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`?lm interposed therebetWeen, a stress is generated in the ?lm
`itself. As for stress, there are tensile stress and compressive
`stress. In this embodiment and other embodiments, an inter
`nal stress ?lm in Which a tensile stress is generated substan
`tially in the parallel direction to the direction in Which carriers
`move (i.e., the gate length direction) in a channel region of an
`MISFET is referred to as a “?rst-type internal stress ?lm” and
`an internal stress ?lm in Which a compressive stress is gen
`erated substantially in the parallel direction to the direction in
`Which carriers move (the gate length direction) in a channel
`region of an MISFET is referred to as a “second-type internal
`stress ?lm”.
`Herein, the semiconductor substrate 1 is an Si substrate of
`Which the principal surface is the {100} plane and is referred
`to as an Si (100) substrate for convenience. HoWever, the
`{100} plane is a general name for the (1100) plane, the (0110)
`plane and the (0011) plane, and therefore, even a plane Which
`is not exactly the {100} plane and is tilted from the {100}
`plane by a less angle than 10 degree is considered to be
`substantially the {100} plane. Moreover, in this embodiment,
`the direction in Which electrons move in the nMISFET and
`the direction in Which holes move in the pMISFET (i.e., the
`gate length direction of each MISFET) is the [01 1] direction.
`HoWever, in this embodiment, the “[011] direction on the
`principal surface of an Si (100) substrate” includes equivalent
`directions to the [01 1] direction, such as the [01-1] direction,
`the [0-1 1] direction, and the [0-1-1] direction, i.e., directions
`Within the range of the <011> direction. That is, even a
`direction Which is not exactly the [011] direction and tilted
`from the <011> direction by a less angle than 10 degree is
`considered to be substantially the [011] direction.
`According to this embodiment, the following effects can be
`obtained.
`In the nMISFET, When the ?rst-type internal stress ?lm 8a
`is brought into a direct contact With a semiconductor layer or
`made to face a semiconductor layer With a thin ?lm interposed
`therebetWeen, a stress for compressing the ?rst-type internal
`stress ?lm itself, i.e., a compressive stress is generated in the
`?rst-type internal stress ?lm 8a. As a result, by the ?rst-type
`internal stress ?lm 8a, the semiconductor layer adjacent to the
`?rst-type internal stress ?lm 811 can be stretched in the vertical
`direction to a boundary surface. Speci?cally, the ?rst-type
`internal stress ?lm 8a applies a compressive stress to the
`source region 311 and the drain region 411 in the active region
`111 of the nMISFET in the parallel direction to the principal
`surface. As a result, a tensile stress is applied to a region of the
`substrate located betWeen the source region 311 and the drain
`region 4a, i.e., the channel region be in the gate length direc
`tion (the direction in Which electrons move When the nMIS
`PET is in an operation state). Then, With this tensile stress,
`electrons are in?uenced by the pieZo resistivity effect, so that
`the mobility of electrons is increased. Herein, “substantially
`in the parallel direction” also means in a direction tilted by an
`angle of less than 10 degree from the direction in Which
`electrons move.
`For example, assume that the substrate 1 is an Si (100)
`substrate and the direction in Which electrons move is the
`[011] direction. When the internal stress of the ?rst-type
`internal stress ?lm 8a adjacent to the semiconductor layer is
`a general level for a silicon nitride ?lm, i.e., 1.5 GPa, the
`thickness of the ?rst-type internal stress ?lm 8a is 20 nm, a
`space betWeen respective parts of the source and drain regions
`3a and 411 being in contact With the ?rst-type internal stress
`?lm 8a, i.e., the length of the channel region 1x, is 0.2 pm, a
`tensile stress in the gate length direction generated at a depth
`of 10 nm from the surface of the substrate is 0.3 GPa (J . Appl.
`Phys., vol. 38-7, p. 2913, 1967) and the improvement rate of
`
`

`

`US 7,893,501 B2
`
`5
`the mobility of electrons is +10% (Phys. Rev., vol. 94, p. 42,
`1954). To obtain a larger change in the mobility than this, the
`tensile stress of a semiconductor can be increased. Thus, a
`?lm having a large internal stress can be used as the ?rst-type
`internal stress ?lm 8a, the thickness of the ?rst-type internal
`stress ?lm 811 can be increased, or the space betWeen the parts
`of the source and drain regions 3a and 411 being in contact With
`the ?rst-type internal stress ?lm 8a, i.e., the length of the
`channel region 1x, can be reduced for a larger change in the
`mobility. For example, When the thickness of the ?rst-type
`internal stress ?lm 8a is doubled, the space betWeen the parts
`of the source and drain regions 3a and 411 being in contact With
`the ?rst-type internal stress ?lm 8a, i.e., the length of the
`channel region be is reduced to half, the improvement rate of
`the mobility of electrons is +40%. As another Way to obtain a
`large mobility, the direction in Which electrons move is
`changed from the [011] direction to the [010] direction to
`change the improvement rate of the mobility of electrons With
`respect to a tensile stress. As a result, With the same tensile
`stress, the improvement rate of the mobility becomes about
`3 .5 times large. Although the source and drain regions 3a and
`4a receive compressive stresses by the ?rst-type internal
`stress ?lm 8a, in?uence of the pieZo resistivity effect is small
`because a loW-resistant heavily doped semiconductor device
`and a silicide ?lm are used. Moreover, in?uence of the inter
`nal stress of the interlevel insulating ?lm 9 on the channel
`region can be neglected. This is because With the substrate
`covered by the interlevel insulating ?lm 9, internal stresses in
`the interlevel insulating ?lm 9 are cancelled off With each
`other, so that the function of applying stress to the active
`regions 1a and 1b is small.
`In the pMISFET, When the second-type internal stress ?lm
`8b is brought into a direct contact With the semiconductor
`layer or made to face a semiconductor layer With a thin ?lm
`interposed therebetWeen, a stress for stretching the second
`type internal stress ?lm itself, i.e., a tensile stress is generated
`in the second-type internal stress ?lm 8b. As a result, by the
`second-type internal stress ?lm 8b, the semiconductor layer
`adjacent to the second-type internal stress ?lm 8b is com
`pressed in the vertical direction to a boundary surface. Spe
`ci?cally, the second-type internal stress ?lm 8b applies a
`tensile stress to the source region 3b and the drain region 4b in
`the active region 1b of the pMISFET in the parallel direction
`to the principal surface. As a result, a compressive stress is
`applied to a region of the substrate located betWeen the source
`region 3b and the drain region 4b, i.e., the channel region 1y
`substantially in the parallel direction to the gate length direc
`tion (the direction in Which holes move When the pMI SFET is
`in an operation state). Then, With this compressive stress,
`holes are in?uenced by the pieZo resistivity effect, so that the
`mobility of holes is increased. Herein, “substantially in the
`parallel direction” also means in a direction tilted by an angle
`of less than 10 degree from the direction in Which electrons
`move.
`Note that, instead of the internal stress ?lms 8a and 8b, the
`semiconductor ?lm itself in Which the source and drain
`regions 3a, 4a, 3b and 4b are formed may be a ?lm having an
`internal stress, for example, an uppermost semiconductor
`layer in an SOI substrate.
`Furthermore, each of the internal stress ?lms 8a and 8b
`does not have to be a single layer but may include multiple
`layers, as long as each of the internal stress ?lms 8a and 8b
`can apply a stress to the substrate as a Whole.
`Moreover, in this embodiment, an Si (100) substrate is
`used. HoWever, even if an Si (11 1) substrate is used, With the
`direction in Which electrons move set to be the [001] direc
`tion, the mobility of electrons is increased by a tensile stress.
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`In general, in any substrate plane directions, there is a direc
`tion of movement of electrons or holes, Which alloWs increase
`in the mobility of electrons or holes according to the direction
`of a stress.
`In this embodiment, the internal stress ?lms 8a and 8b exist
`on the source/drain regions 3a and 4a and the source/drain
`regions 3b and 4b, respectively. HoWever, even When the
`internal stress ?lm 8a exists only on one of the source/drain
`regions 3a and 4a and the internal stress ?lm 8b exists only on
`one of the source/ drain regions 3b and 4b, the effect of
`increasing the mobility of carriers can be obtained. In this
`case, the improvement rate of the mobility is reduced to half.
`In each of the folloWing embodiments, When an internal stress
`?lm exits only on one of source/drain regions, the improve
`ment rate of the mobility is reduced to half, compared to the
`case Where internal stress ?lms exist on source/drain regions,
`but the mobility is increased.
`FIGS. 2A through 2C and FIGS. 3A through 3C are cross
`sectional vieWs illustrating respective steps for fabricating a
`semiconductor device according to the ?rst embodiment of
`the present invention.
`First, in the process step of FIG. 2A, a trench and a buried
`oxide ?lm are formed in part of a semiconductor substrate 1,
`i.e., an Si (100) substrate, thereby forming an isolation region
`2 for dividing the substrate into active regions 1a, 1b and so
`on. Thereafter, after a gate insulating ?lm 5 has been formed
`by thermal oxidation of respective surfaces of the active
`regions 1a and 1b and a polysilicon ?lm for forming gate
`electrodes has been deposited, the polysilicon ?lm and the
`gate insulating ?lm 5 are etched by patterning using lithog
`raphy and anisotropic dry etching, thereby forming gate elec
`trodes 6a and 6b. The gate length direction of each of the gate
`electrodes 6a and 6b is the [011] direction. Next, using the
`gate electrode 611 of the nMISFET as a mask, ion implantation
`of an n-type impurity (e. g., arsenic) at a loW concentration is
`performed to an nMISFET formation region Rn at an injec
`tion energy of 1 0 keV and a dose of 1 x 1 013/cm2, andusing the
`gate electrode 6b of the pMISFET as a mask, ion implantation
`of a p-type impurity (e.g., boron) at a loW concentration is
`performed to a pMISFET formation region Rp at an injection
`energy of 2 keV and a dose of 1><1015/cm2. Thereafter, an
`insulating ?lm Which is for forming a sideWall and has a
`thickness of about 50 nm is deposited on the substrate and
`then a sideWall 7 is formed on side surfaces of the gate
`electrodes 6a and 6b by etch back. Next, using the gate
`electrode 611 of the nMISFET and the sideWall 7 as masks, ion
`implantation of an n-type impurity (e.g., arsenic) at a high
`concentration is performed to the nMI SFET formation region
`Rn at an injection energy of20 keV and a dose of 1 ><1014/cm2,
`and ion implantation of a p-type impurity (e.g., boron) at a
`high concentration is performed to the pMISFET formation
`region Rp at an injection energy of 5 keV and a dose of
`1><1016/cm2. Thereafter, thermal treatment (RTA) for activat
`ing impurities is performed. By the above-described process
`ing, source/drain regions 3a and 411 including an n-type
`lightly doped impurity region and an n-type heavily doped
`impurity region are formed in the nMISFET formation region
`Rn and source/drain regions 3b and 4b including a p-type
`lightly doped impurity region and a p-type heavily doped
`impurity region are formed in the pMISFET formation region
`Rp.
`Next, in the process step of FIG. 2B, a silicon nitride ?lm 8x
`is formed on the substrate so that the silicon nitride ?lm 8x has
`a relatively large thickness and a surface thereof is ?atted. At
`this point of time, the silicon nitride ?lm 8x covers respective
`upper surfaces of the gate electrodes 6a and 6b of the MIS
`FETs. Thereafter, a resist ?lm 12 is formed on the silicon
`
`

`

`US 7,893,501 B2
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`7
`nitride ?lm 8x by lithography and the silicon nitride ?lm 8x is
`patterned using the resist ?lm 12 as a mask so that the silicon
`nitride ?lm 8x is left only on the nMISFET formation region
`Rn.
`Next, in the process step of FIG. 2C, after the resist ?lm 12
`has been removed, the silicon nitride ?lm 8x is etched back,
`part of the silicon nitride ?lm 8x located on the gate electrode
`611 is removed and the thickness of the silicon nitride ?lm 8x
`is further reduced. Thus, a ?rst-type internal stress ?lm 8a is
`formed. That is, the ?rst-type internal stress ?lm 811 does not
`exist on the gate electrode 611 of the nMISFET but exits only
`on the source/drain regions 3a and 411.
`Next, in the process step of FIG. 3A, a TEOS ?lm 8y is
`formed on the substrate so that the TEOS ?lm 8y has a
`relatively large thickness and a surface thereof is ?atted. At
`this point of time, the TEOS ?lm 8y covers respective upper
`surfaces of the gate electrodes 6a and 6b of the MISFETs.
`Thereafter, a resist ?lm (not shoWn) is formed on the TEOS
`?lm 8y by lithography and the TEOS ?lm 8y is patterned
`using the resist ?lm as a mask so that the TEOS ?lm 8y is left
`only on the pMISFET formation region Rp.
`Next, in the process step of FIG. 3B, after the resist ?lm has
`been removed, the TEOS ?lm 8y is etched back, parts of the
`TEOS ?lm 8y located on the gate electrodes 6a and 6b are
`removed and the thickness of the TEOS ?lm 8y is further
`reduced. Thus, a second-type internal stress ?lm 8b having
`substantially the same thickness as that of the ?rst-type inter
`nal stress ?lm 8a is formed. That is, the second-type internal
`stress ?lm 8b does not exist on the gate electrode 6b of the
`pMISFET and the ?rst-type internal stress ?lm 811 but exists
`only on the source/ drain regions 3b and 4b.
`By the above-described process steps, the internal stress
`?lms 8a and 8b for applying stresses in opposite directions to
`each other are formed on the source/drain regions 3a and 4a
`of the nMISFET and the source/drain regions 3b and 4b of the
`pMISFET, respectively.
`Next, in the process step of FIG. 3C, on the substrate, an
`interlevel insulating ?lm 9 is formed and then contact holes
`are formed so as to pass through the interlevel insulating ?lm
`9 and reach the source/drain regions 3a and 4a of the nMIS
`FET by lithography and dry etching, the source/ drain regions
`3b and 4b, and the gate electrodes 6a and 6b, respectively.
`Thereafter, each of the contact holes is ?lled With metal (e.g.,
`tungsten), thereby forming contact plugs 11. Furthermore, a
`metal ?lm such as an aluminum alloy ?lm is deposited on the
`interlevel insulating ?lm 9 and then the metal ?lm is pat
`terned, thereby forming a lead electrode 10 connected to each
`of the contact plugs 11. Thus, the respective source/drain
`regions 3a, 4a, 3b and 4b of the MISFETs and the gate
`electrodes 6a and 6b are made to be electrically connectable
`from the outside.
`In the fabrication method of this embodiment, either one of
`the tWo types of internal stress ?lms 8a and 8b may be formed
`?rst. And the internal stress ?lms 8a and 8b may overlap With
`each other over the isolation region 2 and the source/drain
`regions 3a, 4a, 3b and 4b.
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`First Modi?ed Example of First Embodiment
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`FIGS. 4A through 4C are cross-sectional vieWs illustrating
`?rst through third modi?ed examples of the ?rst embodiment.
`A semiconductor device according to a ?rst modi?ed
`example shoWn in FIG. 4A has a structure in Which the
`sideWall 7 of the ?rst embodiment is omitted. Moreover, each
`of the source/drain regions 3a, 4a, 3b and 4b does not include
`a lightly doped impurity region and includes only a heavily
`doped impurity region. Other part has the same structure as
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`that of the semiconductor device of the ?rst embodiment. In
`this modi?ed example, no sideWall exists in forming an inter
`nal stress ?lm, so that a space betWeen respective parts of the
`source/drain regions 3a and 411 being in contact With the
`?rst-type internal stress ?lm 8a is small. Thus, a stress applied
`to each of the channel regions 1x and 1y is increased, so that
`the effect of improving the carrier mobility becomes larger
`than that of the ?rst embodiment.
`A semiconductor device according to a second modi?ed
`example shoWn in FIG. 4B has a structure in Which instead of
`the sideWall 7 of the ?rst embodiment, Which is made of a
`silicon oxide ?lm, the ?rst-type internal stress ?lm 811 made of
`a silicon nitride ?lm covers a side surface of the gate electrode
`611 of the nMISFET and the second-type internal stress ?lm 8b
`made of a TEOS ?lm covers a side surface of the gate elec
`trode 6b of the pMISFET. Moreover, each of the source/drain
`regions 3a, 4a, 3b and 4b does not include a lightly doped
`impurity region and includes only a heavily doped impurity
`region. Other part has the same structure as that of the semi
`conductor device of the ?rst embodiment.
`In this modi?ed example, in addition to the effect of the
`?rst modi?ed example, the folloWing effect can be obtained.
`In the nMISFET, the ?rst-ty