`INTEGRATED
`CIRCUITS
`
`A DESIGN PERSPECTIVE
`
`SECOND EDITION
`
`JAN M. RABAEY
`ANANTHA CHANDRAKASAN
`BORIVOJE NIKOLIC
`
`PRENTICE HALL ELECTRONICS AND VLSI SERIES
`CHARLES G. SODINI, SERIES EDITOR
`
`evaset)
`Education
`ee
`
`Pearson Education, Inc.
`Upper Saddle River, New Jersey 07458
`
`TSMC 1110
`TSMC 1110
`
`
`
`Library of Congress Cataloging-in-Publication Dataonfile.
`
`Vice President and Editorial Director, ECS: Marcia J. Horton
`Publisher: Tom Robbins
`
`Editorial Assistant: Eric Van Ostenbridge
`Vice President and Director of Production and Manufacturing, ESM: David W. Riccardi
`Executive Managing Editor: Vince O’Brien
`Managing Editor: David A. George
`Production Editor: Daniel Sandin
`
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`Creative Director: Carole Anson
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`Art Editor: Greg Dulles
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`Manufacturing Buyer: Lisa McDowell
`Marketing Manager: Holly Stark
`
`About the Cover: Detail of "Wet Orange," by Joan Mitchell (American, 1925-1992). Oil on canvas, 112 x 245in.
`(284.5 X 622.3 cm). Carnegie Museum of Art, Pittsburgh, PA. Gift of Kaufmann'’s Department Store and the
`National Endowmentfor the Arts, 74.11. Photograph by Peter Harholdt, 1995.
`
`iestines wan
`
`© 2003, 1996 by Pearson Education,Inc.
`Pearson Education, Inc.
`filme
`Pm@@mmes Upper Saddle River, NJ 07458
`
`The author and publisher of this book have used their best efforts in preparing this book. These efforts include the devel-
`opment, research, and testing of the theories and programs to determine their effectiveness. The author and publisher
`shall not be liable in any event for incidental and consequential damages in connection with, or arising out of, the fur-
`nishing, performance,or use of these programs.
`
`All rights reserved. No part of this book may be reproduced, in any form or by any means,
`without permission in writing from the publisher.
`
`Printed in the United States of America
`
`109 8 765 43 2
`
`41
`
`ISBN 0-13-597444-5
`
`Pearson Education Ltd., London
`Pearson Education Australia Pty, Ltd., Sydney
`Pearson Education Singapore, Pte. Ltd.
`Pearson Education North Asia Ltd., Hong Kong
`Pearson Education Canada Inc., Toronto
`Pearson Educacion de Mexico, S.A. de C.V.
`Pearson Education—Japan, Tokyo
`Pearson Education Malaysia, Pte. Ltd.
`Pearson Education Inc., Upper Saddle River, New Jersey
`
`
`
`
`
`Contents
`
`Preface
`
`Vii
`
`renegeneeARLA
`
`Part I
`
`The Fabrics
`
`1 3 4 6
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`15
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`16
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`18
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`27
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`30
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`31
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`31
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`32
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`33
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`35
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`36
`36
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`37
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`37
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`41
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`42
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`47
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`51
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`52
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`53
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`59
`61
`61
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`63
`64
`
`Chapter 1
`
`Chapter 2
`
`1.2
`
`1.3
`
`Introduction
`A Historical Perspective
`1.1
`Issues in Digital Integrated Circuit Design
`Quality Metrics of a Digital Design
`1.3.1 Cost of an Integrated Circuit
`1.3.2 Functionality and Robustness
`1.3.3. Performance
`1.3.4 Power and Energy Consumption
`Summary
`To Probe Further
`Reference Books
`References
`
`1.4
`
`1.5
`
`2.2
`
`2.3
`
`2.4
`
`The Manufacturing Process
`Introduction
`2.1
`Manufacturing CMOSIntegrated Circuits
`2.2.1 The Silicon Wafer
`2.2.2 Photolithography
`2.2.3.
`Some Recurring Process Steps
`2.2.4 Simplified CMOS Process Flow
`Design Rules—The Contract between Designer
`and Process Engineer
`Packaging Integrated Circuits
`2.4.1
`Package Materials
`2.4.2
`Interconnect Levels
`2.4.3 Thermal Considerations in Packaging
`Perspective—Trends in Process Technology
`2.5.1
`Short-Term Developments
`2.5.2
`Inthe Longer Term
`Summary
`
`2.5
`
`2.6
`
`XV
`
`
`
`
`
`xvi
`
`Contents
`
`2.7
`
`To Probe Further
`References
`
`Design Methodology Insert A IC LAYOUT
`Al
`To Probe Further
`References
`
`3.2
`
`Chapter 3 The Devices
`3.1
`Introduction
`The Diode
`3.2.1 A First Glance at the Diode—The Depletion Region
`3.2.2 Static Behavior
`3.2.3 Dynamic, or Transient, Behavior
`3.2.4 The Actual Diode—Secondary Effects
`3.2.5 The SPICE Diode Model
`The MOS(FET)Transistor
`3.3.1 A First Glance at the Device
`3.3.2 The MOSTransistor under Static Conditions
`3.3.3. The Actual MOS Transistor—Some Secondary Effects
`3.3.4 SPICE Models for the MOSTransistor
`A Word on Process Variations
`Perspective—Technology Scaling
`Summary
`To Probe Further
`References
`
`3.3
`
`3.4
`
`3.5
`
`3.6
`
`3.7
`
`Design Methodology Insert B_ Circuit Simulation
`References
`
`4.2
`
`4.3
`
`Chapter4 The Wire
`4.1
`Introduction
`A First Glance
`Interconnect Parameters—Capacitance, Resistance,
`and Inductance
`4.3.1 Capacitance
`4.3.2 Resistance
`4.3.3
`Inductance
`Electrical Wire Models
`4.4.1 The Ideal Wire
`4.4.2 The Lumped Model
`4.4.3 The Lumped RC Model
`444 The Distributed rc Line
`44.5 The Transmission Line
`
`4.4
`
`64
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`64
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`67
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`71
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`71
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`73
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`74
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`74
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`75
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`77
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`80
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`84
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`85
`87
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`87
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`88
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`114
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`117
`120
`122
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`128
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`129
`130
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`131
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`134
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`135
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`136
`136
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`138
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`138
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`144
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`148
`150
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`151
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`151
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`152
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`156
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`159
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`
`
`
`
`
`Contents
`
`4.5
`
`4.6
`4.7
`
`SPICE Wire Models
`4.5.1 Distributed rc Lines in SPICE
`4.5.2 Transmission Line Models in SPICE
`4.5.3 Perspective: A Look into the Future
`Summary
`To Probe Further
`References
`
`Part 2
`
`A Circuit Perspective
`
`Chapter 5
`
`The CMOSInverter
`
`5.1.
`5.2.
`5.3
`
`5.4
`
`5.5
`
`5.6
`
`5.7
`5.8
`
`Introduction
`The Static CMOS Inverter—AnIntuitive Perspective
`Evaluating the Robustness of the CMOSInverter:
`The Static Behavior
`5.3.1
`Switching Threshold -
`5.3.2 Noise Margins
`5.3.3 Robustness Revisited
`Performance of CMOSInverter: The Dynamic Behavior
`5.4.1 Computing the Capacitances
`5.4.2 Propagation Delay: First-Order Analysis
`5.4.3 Propagation Delay from a Design Perspective
`Power, Energy, and Energy Delay
`5.5.1 Dynamic Power Consumption
`5.5.2
`Static Consumption
`5.5.3 Putting It All Together
`5.5.4 Analyzing Power Consumption Using SPICE
`Perspective: Technology Scaling and its Impact
`on the Inverter Metrics
`.
`Summary
`To Probe Further
`
`References
`
`Chapter 6
`
`Designing Combinational Logic Gates in CMOS
`6.1
`Introduction
`6.2
`Static CMOS Design
`6.2.1 Complementary CMOS
`6.2.2 Ratioed Logic
`6.2.3 Pass-Transistor Logic
`Dynamic CMOSDesign
`6.3.1 Dynamic Logic: Basic Principles
`6.3.2 Speed and Power Dissipation of Dynamic Logic
`
`6.3.
`
`xvii
`
`170
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`170
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`170
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`171
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`174
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`174
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`174
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`177
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`179
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`180
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`180
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`184
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`185
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`188
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`191
`193
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`194
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`199
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`213
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`214
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`223
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`225
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`229
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`232
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`235
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`236
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`236
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`237
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`263
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`269
`284
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`284
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`287
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`
`
`
`
`xviii
`
`Contents
`
`Signal Integrity Issues in Dynamic Design
`6.3.3.
`6.3.4 Cascading Dynamic Gates
`Perspectives
`6.4.1 How to Choose a Logic Style?
`6.4.2 Designing Logic for Reduced Supply Voltages
`Summary
`To Probe Further
`References
`
`6.4
`
`6.5
`
`6.6
`
`290
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`295
`303
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`303
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`303
`306
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`307
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`308
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`309
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`310
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`310
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`315
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`317
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`319
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`325
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`326
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`327
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`328
`330
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`330
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`332
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`333
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`339
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`34]
`344
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`344
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`346
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`350
`354
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`354
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`356
`358
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`360
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`361
`364
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`364
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`367
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`368
`370
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`37]
`
`'
`
`Design Methodology Insert C How to Simulate Complex
`Logic Circuits
`Representing Digital Data as a Continuous Entity
`C.1
`Representing Data as a Discrete Entity
`C.2
`C.3 Using Higher-Level Data Models
`References
`Design Methodology Insert D Layout Techniques for Complex Gates
`Chapter7 Designing Sequential Logic Circuits
`7.1
`Introduction
`7.1.1 Timing Metrics for Sequential Circuits
`7.1.2 Classification of Memory Elements
`Static Latches and Registers
`7.2.1 The Bistability Principle
`7.2.2 Multiplexer-Based Latches
`7.2.3. Master-Slave Edge-Triggered Register
`7.2.4 Low-Voltage Static Latches
`7.2.5.
`Static SR Flip-Flops—Writing Data by Pure Force
`Dynamic Latches and Registers
`7.3.1 Dynamic Transmission-Gate Edge-triggered Registers
`7.3.2 C7MOS—A Clock-Skew Insensitive Approach
`7.3.3 True Single-Phase Clocked Register (TSPCR)
`Alternative Register Styles”
`7.4.1
`Pulse Registers
`74.2 Sense-Amplifier-Based Registers
`Pipelining: An Approach to Optimize Sequential Circuits
`7.5.1 Latch- versus Register-Based Pipelines
`7.5.2 NORA-CMOS—ALogicStyle for Pipelined Structures
`Nonbistable Sequential Circuits
`7.6.1 The Schmitt Trigger
`7.6.2 Monostable Sequential Circuits
`7.6.3 Astable Circuits
`Perspective: Choosing a Clocking Strategy
`Summary
`
`7.2
`
`7.3
`
`74
`
`7.5
`
`7.6
`
`7.7
`
`7.8
`
`
`
`
`
`Contents
`
`7.9
`
`To Probe Further
`References
`
`xix
`
`372
`
`372
`
`i P
`
`art 3
`
`A System Perspective
`
`375
`
`Chapter 8
`
`8.2
`
`8.3
`
`8.4
`
`Implementation Strategies for Digital ICS
`Introduction
`8.1
`From Custom to Semicustom and Structured-Array
`Design Approaches
`Custom Circuit Design
`Cell-Based Design Methodology
`8.4.1
`Standard Cell
`8.4.2 Compiled Cells
`8.4.3 Macrocells, Megacells and Intellectual Property
`8.44 Semicustom Design Flow
`Array-Based Implementation Approaches
`8.5.1
`Prediffused (or Mask-Programmable) Arrays
`8.5.2 Prewired Arrays
`Perspective—The Implementation Platform of the Future
`Summary
`To Probe Further
`References
`Design Methodology Insert E Characterizing Logic
`and Sequential Cells
`References
`Design Methodology Insert F Design Synthesis
`References
`
`8.5
`
`8.6
`
`8.7
`
`8.8
`
`9.2
`
`9.3
`
`Chapter 9 Coping with Interconnect
`Introduction
`9.1
`Capacitive Parasitics
`9.2.1 Capacitance and Reliability—Cross Talk
`9.2.2 Capacitance and Performance in CMOS
`Resistive Parasitics
`9.3.1 Resistance and Reliability—Ohmic Voltage Drop
`9.3.2 Electromigration
`9.3.3. Resistance and Performance—RC Delay
`Inductive Parasitics
`9.4.1
`Inductance and Reliability— Voltage Drop
`9.4.2
`Inductance and Performance—Transmission-line Effects
`AdvancedInterconnect Techniques
`
`9.4
`
`9.5
`
`377
`
`378
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`382
`
`383
`384
`385
`
`390
`392
`396
`399
`
`399
`
`404
`420
`
`423
`423
`424
`
`427
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`434
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`435
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`443
`
`445
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`446
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`446
`446
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`449
`460
`460
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`462
`
`464
`469
`469
`475
`
`480
`
`
`
`XX
`
`
`
`Contents
`
`9.5.1 Reduced-Swing Circuits
`9.5.2 Current-Mode Transmission Techniques
`Perspective: Networks-on-a-Chip
`Summary
`To Probe Further
`
`9.6
`9.7
`
`9.8
`
`References
`
`Chapter 10 TimingIssues in Digital Circuits
`10.1
`Introduction
`Timing Classification of Digital Systems
`10.2.1 SynchronousInterconnect
`10.2.2 Mesochronous interconnect
`
`10.2
`
`10.2.3 Plesiochronous Interconnect
`10.2.4 Asynchronous Interconnect
`Synchronous Design—AnIn-depth Perspective
`10.3.1 Synchronous Timing Basics
`10.3.2 Sources of Skew and Jitter
`10.3.3. Clock-Distribution Techniques
`10.3.4 Latch-Based Clocking”
`Self-Timed Circuit Design™
`10.4.1 Self-Timed Logic—An Asynchronous Technique
`10.4.2 Completion-Signal Generation
`10.4.3 Self-Timed Signaling
`10.4.4 Practical Examples of Self-Timed Logic
`Synchronizers and Arbiters™
`10.5.1 Synchronizers—Concept and Implementation
`10.5.2 Arbiters
`Clock Synthesis and Synchronization Using
`a Phase-Locked Loop"
`10.6.1 Basic Concept
`10.6.2 Building Blocks of a PLL
`Future Directions and Perspectives
`10.7.1 Distributed Clocking Using DLLs
`10.7.2 Optical Clock Distribution
`10.7.3 Synchronous versus Asynchronous Design
`Summary
`To Probe Further
`References
`
`10.3
`
`10.4
`
`10.5
`
`10.6
`
`10.7
`
`10.8
`10.9
`
`Design Methodology InsertG Design Verification
`References
`
`480
`
`486
`487
`
`488
`
`489
`
`489
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`491
`
`492
`
`492
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`492
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`493
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`493
`
`494
`495
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`495
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`502
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`508
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`516
`519
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`519
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`522
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`526
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`531
`534
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`534
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`538
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`539
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`540
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`542
`546
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`546
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`548
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`549
`550
`
`551
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`551
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`553
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`557
`
`
`
`
`
`Contents
`
`Chapter
`
`11.1
`
`11.2
`
`11.3
`
`11.4
`
`1111 Designing Arithmetic Building Blocks
`Introduction
`Datapaths in Digital Processor Architectures
`The Adder
`11.3.1 The Binary Adder: Definitions
`11.3.2 The Full Adder: Circuit Design Considerations
`11.3.3 The Binary Adder: Logic Design Considerations
`The Multiplier
`11.4.1 The Multiplier: Definitions
`11.4.2 Partial-Product Generation
`11.4.3 Partial-Product Accumulation
`11.4.4 Final Addition
`11.4.5 Multiplier Summary
`The Shifter
`11.5.1 Barrel Shifter
`11.5.2 Logarithmic Shifter
`Other Arithmetic Operators
`Power and Speed Trade-offs in Datapath Structures”
`11.7.1 Design Time Power-Reduction Techniques
`11.7.2 Run-Time Power Management
`11.7.3 Reducing the Powerin Standby (or Sleep) Mode
`Perspective: Design as a Trade-off
`11.8
`Summary
`11.9
`11.10 To Probe Further
`References
`
`11.5
`
`11.6
`
`11.7
`
`12.2
`
`Chapter 12 Designing Memory and Array Structures
`Introduction
`12.1
`12.1.1 Memory Classification
`12.1.2 Memory Architectures and BuildingBlocks
`The Memory Core
`12.2.1 Read-Only Memories
`12.2.2 Nonvolatile Read-Write Memories
`12.2.3 Read-Write Memories (RAM)
`12.2.4 Contents-Addressable or Associative Memory (CAM)
`Memory Peripheral Circuitry”
`12.3.1 The Address Decoders
`12.3.2 Sense Amplifiers
`12.3.3 Voltage References
`12.3.4 Drivers/Buffers
`12.3.5 Timing and Control
`
`12.3
`
`xxi
`
`559
`
`560
`560
`561
`
`561
`
`564
`
`571
`586
`
`586
`
`587
`
`589
`
`593
`
`594
`594
`595
`
`596
`596
`600
`601
`
`611
`
`617
`618
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`619
`
`620
`
`621
`
`623
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`624
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`625
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`627
`634
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`634
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`647
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`657
`
`670
`672
`
`672
`
`679
`
`686
`
`689
`
`689
`
`
`
`
`
`xxii
`
`Contents
`
`12.4 Memory Reliability and Yield”
`12.4.1 Signal-to-Noise Ratio
`12.4.2 Memory Yield
`12.5 Power Dissipation in Memories”
`12.5.1 Sources of Power Dissipation in Memories
`12.5.2 Partitioning of the Memory
`12.5.3 Addressing the Active Power Dissipation
`12.5.4 Data-Retention Dissipation
`12.5.5 Summary
`12.6 Case Studies in Memory Design
`12.6.1 The Programmable Logic Array (PLA)
`12.6.2 A 4-Mbit SRAM
`12.6.3 A 1-Gbit NAND Flash Memory
`12.7 Perspective: Semiconductor Memory Trends and Evolutions
`12.8 Summary
`12.9 To Probe Further
`References
`
`Design Methodology Insert H Validation and Test
`of Manufactured Circuits
`
`~
`
`Introduction
`H.1
`Test Procedure
`H.2
`H.3 Design for Testability
`H.3.1 Issues in Design for Testability
`H.3.2 Ad Hoc Testing
`H.3.3 Scan-Based Test
`H.3.4 Boundary-Scan Design
`H.3.5 Built-in Self-Test (BIST)
` Test-Pattern Generation
`H.4.1 Fault Models
`H.4.2 Automatic Test-Pattern Generation (ATPG)
`H.4.3 Fault Simulation
`To Probe Further
`References
`
`H.4
`
`H.5
`
`Problem Solutions
`
`Index
`
`693
`693
`698
`701
`701
`702
`702
`704
`707
`707
`707
`710
`712
`714
`716
`717
`718
`
`721
`
`721
`722
`723
`723
`725
`726
`729
`730
`734
`734
`736
`737
`737
`737
`
`739
`
`745
`
`
`
`
`
`
`CHAPTER
`
`The Manufacturing Process
`
`
`
`Overview of manufacturing process
`
`- Design rules
`
`ICpackaging
`Future Trends in Integrated Circuit Technology
`
`
`
`2.1
`
`2.2
`
`2.3
`
`2.4
`
`2.5
`
`2.6
`
`2.7
`
`Introduction
`Manufacturing CMOSIntegrated Circuits
`2.2.1
`The Silicon Wafer
`2.2.2
`Photolithography
`2.2.3
`Some Recurring Process Steps
`2.2.4
`Simplified CMOS Process Flow
`Design Rules—Between the Designer and the Process Engineer
`Packaging Integrated Circuits
`2.4.1
`Package Materials
`2.4.2
`Interconnect Levels
`2.4.3
`Thermal Considerations in Packaging
`Perspective—Trends in Process Technology
`2.5.1.
`Short-Term Developments
`2.5.2
`Inthe Longer Term
`Summary
`To Probe Further
`
`35
`
`
`
`
`
`36
`
`Chapter 2 ¢ The Manufacturing Process
`
`2.1.
`
`Introduction
`
`Most digital designers will never be confronted with the details of the manufacturing process
`that lay at the core of the semiconductor revolution. Still, some insight into the steps that lead to
`an operational silicon chip comes in quite handy in understanding the physical constraints
`imposed on a designer of an integrated circuit, as well as the impact of the fabrication process on
`issues such as cost.
`In this chapter, we briefly describe the steps and techniques used in a modern integrated
`circuit manufacturing process. It is not our aim to present a detailed description of the fabrica-
`tion technology, which easily deserves a complete course [Plummer00]. Rather, we aim at pre-
`senting the general outline of the flow and the interaction between the various steps. We learn
`that a set of optical masks formsthe central interface betweenthe intrinsics of the manufacturing
`process and the design that the user wants to see transferred to the silicon fabric. The masks
`define the patterns that, when transcribed onto the different layers of the semiconductor material,
`form the elements of the electronic devices and the interconnecting wires. As such, these pat-
`terns have to adhere to some constraints, in terms of minimum width and separation, if the
`resulting circuit is to be fully functional. This collection of constraints is called the design rule
`Set, and acts as the contract between the circuit designer and the process engineer. If the designer
`adheres to these rules, he gets a guarantee that his circuit will be manufacturable. An overview
`of the commondesign rules encountered in modern CMOSprocessesis given, as well as a per-
`spective on the IC packaging options. The package forms the interface between the circuit
`implemented onthe silicon die and the outside world, and as such has a major impact on the per-
`formance,reliability, longevity, and cost of the integrated circuit.
`
`2.2 Manufacturing CMOSIntegrated Circuits
`A simplified cross section of a typical CMOS inverter is shown in Figure 2-1. The CMOSpro-
`cess requires that both n-channel (NMOS) and p-channel (PMOS) transistors be built in the
`same silicon material. To accommodate both types of devices, special regions called wells must
`be created in which the semiconductor material is opposite to the type of the channel. A PMOS
`transistor has to be created in either an n-type substrate or an n-well, while an NMOSdevice
`resides in either a p-type substrate or a p-well. The cross section shown in Figure 2-1 features an
`
`Polysilicon
`
`SiO,
`
`Al
`
`Figure 2-1 Cross section of an n-well CMOSprocess.
`
`p-substrate
`
`
`
`
`
`
`
`
`
`
`
`
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`2.2 Manufacturing CMOSIntegrated Circuits
`
`37
`
`gateoxide
`
`Tungsten
`N
`
`TiSiy
`
`
`Lo
`
`
`
`Figure 2-2 Cross section of modern dual-well CMOSprocess.
`
`n-well CMOSprocess, where the NMOStransistors are implemented in the p-doped substrate,
`and the PMOS devices are located in the n-well. Modern processes are increasingly using a
`dual-well approach that uses both n- and p-wells, grown on top of an epitaxial layer, as shown in
`Figure 2-2.
`The CMOSprocessrequires a large number of steps, each of which consists of a sequence
`of basic operations. A numberof these steps and/or operations are executed very repetitively in
`the course of the manufacturing process. Rather than immediately delving into a description of
`the overall process flow, wefirst discuss the starting material followed by a detailed perspective
`on someof the most frequently recurring operations.
`
`2.2.1.
`
`The Silicon Wafer
`
`The base material for the manufacturing process comes in the form of a single-crystalline,
`lightly doped wafer. These wafers have typical diameters between 4 and 12 inches (10 and
`30 cm, respectively) and a thickness of, at most 1 mm. They are obtained by cutting a single-
`crystal ingot into thin slices (see Figure 2-3). A starting wafer of the p-type might be doped
`around the levels of 2 x 107! impurities/m°. Often, the surface of the wafer is doped more
`heavily, and a single crystal epitaxial layer of the opposite type is grownoverthe surface before
`the wafers are handed to the processing company. One important metric is the defect density of
`the base material. High defect densities lead to a larger fraction of nonfunctional circuits, and
`consequently an increase in costof the final product.
`
`Photolithography
`2.2.2
`In each processingstep, a certain area on the chip is masked out using the appropriate optical
`mask so that a desired processing step can beselectively applied to the remaining regions. The
`processing step can be any of a wide range of tasks, including oxidation, etching, metal and
`polysilicon deposition, and ion implantation. The technique to accomplish this selective mask-
`ing, called photolithography, is applied throughout the manufacturing process. Figure 2-4 gives
`
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`
`
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`38
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`Chapter 2 * The Manufacturing Process
`
`
`
`Figure 2-3 Single-crystal ingot and sliced wafers (from [Fullman99}).
`
`
`
`
`optical
`mask
`
`
`
`oxidation
`
`
`photoresist coating
`
`
`photoresist
`stepper exposure
`
`removal (ashing)
`
`
` photoresist
`development
`
`process
`step
`
`acid etch
`
`
`spin, rinse, dry
`
`
`
`Figure 2-4 Typical operations in a single photolithographic cycle (from [Fullman99]).
`
`
`
`
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`2.2 Manufacturing CMOSIntegrated Circuits
`
`39
`
`a graphical overview of the different operations involved in a typical photolithographic process.
`The following steps can be identified:
`
`1. Oxidation layering—this optional step deposits a thin layer of SiO, over the complete
`wafer by exposing it to a mixture of high-purity oxygen and hydrogen at approximately
`1000°C. The oxide is used as an insulation layer and also formstransistor gates.
`2. Photoresist coating—a light-sensitive polymer (similar to latex) is evenly applied to a
`thickness of approximately 1 um by spinning the wafer. This material is originally soluble
`in an organic solvent, but has the property that the polymers cross-link when exposed to
`light, making the affected regions insoluble. A photoresistof this type is called negative. A
`positive photoresist has the opposite properties; originally insoluble, but soluble after
`exposure. By using both positive and negative resists, a single mask can sometimes be
`used for two steps, making complementary regions available for processing. Since the cost
`of a mask is increasing quite rapidly with the scaling of technology, reducing the number
`of masks surely is a high priority.
`3. Stepper exposure—a glass mask(orreticle) containing the patterns that we want to trans-
`fer to the silicon is brought in close proximity to the wafer. The mask is opaque in the
`regions that we wantto process, and transparentin the others (assuming a negative photo-
`resist). The glass mask can be thoughtof as the negative of one layer of the microcircuit.
`The combination of mask and wafer is now exposed to ultraviolet light. Where the mask is
`transparent, the photoresist becomesinsoluble.
`4, Photoresist development and bake—the wafers are developedin either an acid or base
`solution to remove the nonexposedareas of photoresist. Once the exposed photoresist is
`removed, the wafer is “soft baked” at a low temperature to harden the remaining
`photoresist.
`5. Acid etching—material is selectively removed from areas ofthe wafer that are not covered
`by photoresist. This is accomplished through the use of many different types of acid, base
`and caustic solutions as a function of the material that is to be removed. Muchof the work
`with chemicals takes place at large wet benches where special solutions are prepared for
`specific tasks. Because of the dangerous nature of someof these solvents, safety and envi-
`ronmental impact is a primary concern.
`6. Spin, rinse, and dry—aspecial tool (called SRD) cleans the wafer with deionized water
`anddries it with nitrogen. The microscopic scale of modern semiconductor devices means
`that even the smallest particle of dust or dirt can destroy the circuitry. To prevent this from
`happening, the processing steps are performed in ultraclean rooms where the number of
`dust particles per cubic footof air ranges between | and 10. Automatic wafer handling and
`robotics are used wheneverpossible. This explains why the cost ofa state-of-the-art
`fabrication facility easily reaches multiple billions of dollars. Even then, the wafers must
`be constantly cleaned to avoid contamination and to removethe leftover of the previous
`processsteps.
`
`i | i ii|
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`40
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`Chapter 2 * The Manufacturing Process
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`7. Various process steps—the exposed area can now be subjected to a wide range of process
`steps, such as ion implantation, plasma etching, or metal deposition. These are the subjects
`of the subsequent section.
`8. Photoresist removal (or ashing)}—a high-temperature plasmais used to selectively remove
`the remaining photoresist without damaging device layers.
`
`In Figure 2-5, we illustrate the use of the photolithographic process for one specific exam-
`ple, the patterning of a layer of SiOQ,. The sequence of process steps shownin the figure patterns
`exactly one layer of the semiconductor material and may seem very complex. Yet, the reader has
`to bear in mind that the same sequence patterns the layer of the complete surface of the wafer.
`Hence,it is a very parallel process, transferring hundreds of millions of patterns to the semicon-
`ductor surface simultaneously. The concurrent and scalable nature of the optolithographical pro-
`cess is what makes the cheap manufacturing of complex semiconductor circuits possible, and
`lies at the core of the economic success of the semiconductor industry.
`The continued scaling of the minimum feature sizes in integrated circuits puts an enormous
`burden on the developer of semiconductor manufacturing equipment. This is especially true for
`the optolithographical process. The dimensions of the features to be transcribed surpass the
`wavelengths ofthe optical light sources, so that achieving the necessary resolution and accuracy
`
`Si substrate
`
`(a) Silicon base material
`
`Chemical or plasma
`etch
`
`Hardened resist
`
`S10,
`
`Si substrate
`
`Si substrate
`
`(d) After development and etching ofresist,
`chemical or plasma etch of SiO,
`
` Hardenedresist
`
`SiO, (b) After oxidation and deposition
`
`of negative photoresist
`
`
`
`
`
`
`
`:i:
`
`Si substrate
`WYdY EEE Td ce
`
`Patterned
`:
`| Coptical mask
`(e) After etching
`| | |
`\ | {
`Exposedresist r_\
`
`
`
`[| SiO>
`
`
`Si substrate
`
`(c) Stepper exposure
`
`Figure 2-5
`
`Processsteps for patterning of SiO.
`
`(f) Final result after removalof resist
`
`Si substrate
`
`
`
`teERRymngpet
`1RERSESTERNAORERERESee
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`
`
`
`
`rotSEREDRORAIRMEN
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`2.2 Manufacturing CMOSIntegrated Circuits
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`41
`
`becomes more and more difficult. So far, electrical engineering has extendedthe lifetime ofthis
`processatleast until the 100 nm (or 0.1 Um) process generation. Techniques such as optical mask
`correction (OPC) prewarp the drawn patterns to accountfor the diffraction phenomena, encoun-
`tered when printing close to the wavelength of the available optical source. This adds substan-
`tially to the cost of mask making. In the foreseeable future, other solutions that offer a finer
`resolution, such as extreme ultraviolet (EUV), X ray, or electron beam, may be needed. These
`techniques, while fully functional, are currently less attractive from an economic viewpoint.
`
`2.2.3
`
`Some Recurring Process Steps
`
`Diffusion and Ion Implantation
`Manysteps of the integrated circuit manufacturing process require a change in the dopant con-
`centration of some parts of the material. Examples include the creation of the source and drain
`regions, well and substrate contacts, the doping of the polysilicon, and the adjustments of the
`device threshold. Two approaches exist for introducing these dopants—diffusion and ion
`implantation. In both techniques, the area to be doped is exposed, while the rest of the wafer is
`coated with a layer of buffer material, typically SiO).
`In diffusion implantation, the wafers are placed in a quartz tube embeddedin a heated fur-
`nace. A gas containing the dopant is introduced in the tube. The high temperatures of the fur-
`nace, typically 900 to 1100 °C, cause the dopants to diffuse into the exposed surface both
`vertically and horizontally. The final dopant concentration is the greatest at the surface and
`decreases in a gaussian profile deeper in the material.
`In ion implantation, dopants are introduced as ions into the material. The ion implantation
`system directs and sweeps a beam ofpurified ions over the semiconductor surface. The accelera-
`tion of the ions determines how deep they will penetrate the material, while the beam current
`and the exposure time determine the dosage. The ion implantation method allows for an inde-
`pendent control of depth and dosage. This is the reason that ion implantation has largely dis-
`placed diffusion in modern semiconductor manufacturing.
`Ion implantation has some unfortunate side effects, however, the most important one being
`lattice damage. Nuclear collisions during the high energy implantation cause the displacement
`of substrate atoms, leading to material defects. This problem is largely resolved by applying a
`subsequent annealing step, in which the wafer is heated to around 1000°C for 15 to 30 minutes,
`and then allowed to cool slowly. The heating step thermally vibrates the atoms, which allows the
`bondsto reform.
`
`Deposition
`Any CMOSprocess requires the repetitive deposition of layers of a material over the complete
`wafer, to either act as buffers for a processing step, or as insulating or conducting layers. We
`have already discussed the oxidation process, which allows a layer of SiO, to be grown. Other
`materials require different techniques. For instance, silicon nitride (Si,N,) is used as a sacrificial
`buffer material during the formation of the field oxide and the introduction of the stopper
`
`
`
`
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`42
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`Chapter 2 « The Manufacturing Process
`
`implants. This silicon nitride is deposited everywhere using a process called chemical vapor
`deposition or CVD.This process is based on a gas-phase reaction, with energy supplied by heat
`at around 850°C.
`Polysilicon, on the other hand, is deposited using a chemical deposition process, which
`flows silane gas over the heated wafer coated with SiO, at a temperature of approximately
`650°C. The resulting reaction produces a noncrystalline or amorphous material called polysili-
`con. To increase the conductivity of the material, the deposition has to be followed by an implan-
`tation step.
`The Aluminum interconnect layers typically are deployed using a process knownas sput-
`tering. The aluminum is evaporated in a vacuum, with the heat for the evaporation delivered by
`electron-beam or ion-beam bombarding. Other metallic interconnect materials such as Copper
`require different deposition techniques.
`
`Etching
`Once a material has been deposited, etching is used selectively to form patterns such as wires
`and contact holes. We already discussed the wet etching process, which makes use of acid or
`basic solutions. Hydrofluoric acid buffered with ammonium fluoride typically is used to etch
`S10,, for example.
`In recent years, dry or plasma etching has advanced substantially. A wafer is placed into
`the etch tool's processing chamberand given a negative electrical charge. The chamber is heated
`to 100°C and brought to a vacuum level of 7.5 Pa, then filled with a positively charged plasma
`(usually a mix of nitrogen, chlorine, and boron trichloride). The opposing electrical charges
`cause the rapidly moving plasma molecules to align themselves in a vertical direction, forming a
`microscopic chemical and physical “sandblasting” action which removes the exposed material.
`Plasma etching has the advantage of offering a well-defined directionality to the etching action,
`creating patterns with sharp vertical contours.
`
`Planarization
`To reliably deposit a layer of material onto the semiconductor surface, it is essential that the sur-
`face be approximately flat. If special steps were not taken, this would definitely present prob-
`lems in modern CMOS processes, where multiple patterned metal interconnect layers are
`superimposed onto each other. Therefore, a chemical-mechanical planarization (CMP) step is
`included before the deposition of an extra metal layer on top of the insulating SiO, layer. This
`process uses a slurry compound—aliquid carrier with a suspended abrasive componentsuch as
`aluminum oxide or silica—to microscopically plane a device layer and to reduce the step
`heights.
`
`Simplified CMOS Process Flow
`2.2.4
`The gross outline of a potential CMOSprocessflow is given in Figure 2-6. The processstarts
`with the definition of the active regions—these are the regions where transistors will be con-
`structed. All other areas of the die will be covered with a thick layer of silicon dioxide (SiO,)
`
`
`
`
`
`
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`2.2 Manufacturing CMOSintegrated Circuits
`
`43
`
`
`
`
`
`
`Define active areas
`Etch andfill trenches
`
`
`
`}
`
`Implant weil regions
`
`
`
`
`y
`
`Deposit and pattern
`polysilicon layer
`
`|
`
`Implant source and drain
`regions and substrate contacts
`}
`
`Create contact and via windows
`Deposit and pattern metal layers
`
`Figure 2-6 Simplified process sequence for the manufacturing of a n-dual-well CMOScircuit.
`
`called the field oxide. This oxide acts as the insulator between neighboring devices, andit is
`either grown (as in the process of Figure 2-1) or deposited in etched trenches (Figure 2-2)—
`hence, the name trench insulation. Further insulation is provided by the addition of a reverse-
`biased np-diode, formed by adding an extra p* region called the channel-stop implant(orfield
`implant) underneath the field oxide. Next, lightly doped p- and n-wells are formed through ion
`implantation. To construct an NMOStransistor in a p-well, heavily doped n-type source and
`drain regions are implanted (or diffused) into the lightly doped p-type substrate. A thin layer of
`SiO, called the gate oxide separates the region between the source and drain, andis itself cov-
`ered by conductive polycrystalline silicon (or polysilicon, for short). The conductive material
`forms the gate of the transistor. PMOStransistors are constructed in an n-well in a similar fash-
`ion (just reverse n’s and p’s). Multiple insulated layers of metallic (most often Aluminum) wires
`are deposited on top of these devices to provide for the necessary interconnections between the
`transistors.
`A more detailed breakdown of the flow into individual process steps and their impact on
`the semiconductor material is shown graphically in Figure 2-7. While most of the operations
`should be self-explanatory in light of the previous descriptions, some comments on individual
`operations are worthwhile. The processstarts with a p