JOURNAL OF APPLIED PHYSICS
`
`VOLUME 89, NUMBER 10
`
`15 MAY 2001
`
`APPLIED PHYSICS REVIEW
`
`High-␬gate dielectrics: Current status and materials properties
`considerations
`G. D. Wilka)
`Agere Systems, Electronic Device Research Laboratory, Murray Hill, New Jersey 07974
`R. M. Wallaceb)
`University of North Texas, Department of Materials Science, Denton, Texas 76203
`J. M. Anthony
`University of South Florida, Center for Microelectronics Research, Tampa, Florida 33620
`共Received 9 November 2000; accepted for publication 19 January 2001兲
`Many materials systems are currently under consideration as potential replacements for SiO2 as the
`gate dielectric material for sub-0.1 ␮m complementary metal–oxide–semiconductor 共CMOS兲
`technology. A systematic consideration of the required properties of gate dielectrics indicates that
`the key guidelines for selecting an alternative gate dielectric are 共a兲 permittivity, band gap, and band
`alignment to silicon, 共b兲 thermodynamic stability, 共c兲 film morphology, 共d兲 interface quality, 共e兲
`compatibility with the current or expected materials to be used in processing for CMOS devices, 共f兲
`process compatibility, and 共g兲 reliability. Many dielectrics appear favorable in some of these areas,
`but very few materials are promising with respect to all of these guidelines. A review of current
`work and literature in the area of alternate gate dielectrics is given. Based on reported results and
`fundamental considerations, the pseudobinary materials systems offer large flexibility and show the
`most promise toward successful integration into the expected processing conditions for future
`CMOS technologies, especially due to their tendency to form at interfaces with Si 共e.g. silicates兲.
`These pseudobinary systems also thereby enable the use of other high-␬materials by serving as an
`interfacial high-␬layer. While work is ongoing, much research is still required, as it is clear that any
`material which is to replace SiO2 as the gate dielectric faces a formidable challenge. The
`requirements for process integration compatibility are remarkably demanding, and any serious
`candidates will emerge only through continued, intensive investigation. © 2001 American Institute
`关DOI: 10.1063/1.1361065兴
`of Physics.
`
`I. INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5243
`II. SCALING AND IMPROVED
`PERFORMANCE. . . . . . . . . . . . . . . . . . . . . . . . . . . 5244
`III. METAL-INSULATOR-SEMICONDUCTOR
`共MIS兲 GATE STACK STRUCTURES. . . . . . . . . . 5245
`IV. SCALING LIMITS FOR CURRENT GATE
`DIELECTRICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5247
`A. Ultrathin SiO2 properties. . . . . . . . . . . . . . . . . . . 5247
`B. Ultrathin SiO2 reliability. . . . . . . . . . . . . . . . . . . 5248
`C. Boron penetration and surface preparation. . . . . 5249
`D. SiOxNy and Si–N/SiO2 dielectrics. . . . . . . . . . . . 5249
`E. Fundamental limitations. . . . . . . . . . . . . . . . . . . . 5249
`F. Device structures. . . . . . . . . . . . . . . . . . . . . . . . . 5250
`V. ALTERNATIVE HIGH-␬GATE DIELECTRICS.. 5250
`A. High-␬candidates from memory applications. . 5251
`B. Issues for interface engineering. . . . . . . . . . . . . . 5252
`C. Recent high-␬results. . . . . . . . . . . . . . . . . . . . . . 5253
`
`a兲G. D. Wilk is formerly of Bell Laboratories, Lucent Technologies; elec-
`tronic mail: gwilk@agere.com
`b兲Electronic mail: rwallace@unt.edu
`
`1. Group IIIA and IIIB metal oxides. . . . . . . . . 5254
`2. Group IVB metal oxides. . . . . . . . . . . . . . . . 5256
`3. Pseudobinary alloys. . . . . . . . . . . . . . . . . . . . 5262
`4. High-␬device modeling and transport. . . . . 5265
`VI. MATERIALS PROPERTIES
`CONSIDERATIONS. . . . . . . . . . . . . . . . . . . . . . . . 5266
`A. Permittivity and barrier height. . . . . . . . . . . . . . . 5266
`B. Thermodynamic stability on Si. . . . . . . . . . . . . . 5268
`C. Interface quality. . . . . . . . . . . . . . . . . . . . . . . . . . 5269
`D. Film morphology. . . . . . . . . . . . . . . . . . . . . . . . . 5270
`E. Gate compatibility. . . . . . . . . . . . . . . . . . . . . . . . 5271
`F. Process compatibility. . . . . . . . . . . . . . . . . . . . . . 5272
`G. Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5272
`VII. CONCLUSIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . 5273
`
`I. INTRODUCTION
`The rapid progress of complementary metal–oxide–
`semiconductor 共CMOS兲 integrated circuit technology since
`the late 1980’s has enabled the Si-based microelectronics
`industry to simultaneously meet several technological re-
`quirements to fuel market expansion. These requirements in-
`
`0021-8979/2001/89(10)/5243/33/$18.00
`
`5243
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`© 2001 American Institute of Physics
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`Downloaded 11 Apr 2003 to 171.64.106.216. Redistribution subject to AIP license or copyright, see http://ojps.aip.org/japo/japcr.jsp
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`5244
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`J. Appl. Phys., Vol. 89, No. 10, 15 May 2001
`
`Appl. Phys. Rev.: Wilk, Wallace, and Anthony
`
`(VD /L) along the channel direction. Initially, ID increases
`linearly with VD and then eventually saturates to a maximum
`when VD,sat⫽VG⫺VT to yield
`共VG⫺VT兲2
`2
`The term (VG⫺VT) is limited in range due to reliability
`and room temperature operation constraints, since too large a
`VG would create an undesirable, high electric field across the
`oxide. Furthermore, VT cannot easily be reduced below
`about 200 mV, because kT⬃25 mV at room temperature.
`Typical specification temperatures 共⭐100 °C兲 could there-
`fore cause statistical fluctuations in thermal energy, which
`would adversely affect the desired the VT value. Thus, even
`in this simplified approximation, a reduction in the channel
`length or an increase in the gate dielectric capacitance will
`result in an increased ID,sat .
`In the case of increasing the gate capacitance, consider a
`parallel plate capacitor 共ignoring quantum mechanical and
`depletion effects from a Si substrate and gate兲6
`␬⑀0A
`t
`where ␬ is the dielectric constant 共also referred to as the
`relative permittivity in this article兲 of the material,7 ⑀0 is the
`permittivity of free space (⫽8.85⫻10⫺3 fF/␮m), A is the
`area of the capacitor, and t is the thickness of the dielectric.
`This expression for C can be rewritten in terms of teq 共i.e.,
`equivalent oxide thickness兲 and ␬ox 共⫽3.9, dielectric con-
`stant of SiO2兲 of the capacitor. The term teq represents the
`thickness of SiO2 that would be required to
`theoretical
`achieve the same capacitance density as the dielectric 共ignor-
`ing issues such as leakage current and reliability兲. For ex-
`ample, if the capacitor dielectric is SiO2, teq⫽3.9⑀0(A/C),
`and a capacitance density of C/A⫽34.5 fF/␮m2 corresponds
`to teq⫽10 Å. Thus, the physical thickness of an alternative
`dielectric employed to achieve the equivalent capacitance
`density of teq⫽10 Å can be obtained from the expression
`thigh⫺␬
`teq
`␬ox
`␬high⫺␬
`
`⫽
`
`or simply,
`
`thigh⫺␬⫽
`
`teq⫽
`
`teq .
`
`共4兲
`
`␬high⫺␬
`␬high⫺␬
`3.9
`␬ox
`A dielectric with a relative permittivity of 16 therefore af-
`fords a physical thickness of ⬃40 Å to obtain teq⫽10 Å. 共As
`noted above, actual performance of a CMOS gate stack does
`not scale directly with the dielectric due to possible quantum
`mechanical and depletion effects.兲6
`From a CMOS circuit performance point of view, a per-
`formance metric considers the dynamic response 共i.e., charg-
`ing and discharging兲 of the transistors, associated with a spe-
`cific circuit element, and the supply voltage provided to the
`element at a representative 共clock兲 frequency. A common
`element employed to examine such switching time effects is
`a CMOS inverter.1 This circuit element is shown in Fig. 1
`where the input signal is attached to the gates and the output
`signal is connected to both the n-type MOS 共nMOS兲 and
`p-type MOS 共pMOS兲 transistors associated with the CMOS
`
`.
`
`共2兲
`
`␮Cinv
`
`WL
`
`ID,sat⫽
`
`C⫽
`
`,
`
`共3兲
`
`clude performance 共speed兲, low static 共off-state兲 power, and
`a wide range of power supply and output voltages.1 This has
`been accomplished by developing the ability to perform a
`calculated reduction of the dimensions of the fundamental
`active device in the circuit:
`the field effect
`transistor
`共FET兲—a practice termed ‘‘scaling.’’2–4 The result has been
`a dramatic expansion in technology and communications
`markets
`including the market
`associated with high-
`performance microprocessors as well as low static-power ap-
`plications, such as wireless systems.5
`It can be argued that the key element enabling the scal-
`ing of the Si-based metal–oxide–semiconductor field effect
`transistor 共MOSFET兲 is the materials 共and resultant electri-
`cal兲 properties associated with the dielectric employed to iso-
`late the transistor gate from the Si channel in CMOS devices
`for decades: silicon dioxide. The use of amorphous, ther-
`mally grown SiO2 as a gate dielectric offers several key ad-
`vantages in CMOS processing including a stable 共thermody-
`namically and electrically兲, high-quality Si–SiO2 interface as
`well as superior electrical isolation properties. In modern
`CMOS processing, defect charge densities are on the order of
`1010/cm2, midgap interface state densities are ⬃1010/
`cm2 eV, and hard breakdown fields of 15 MV/cm are rou-
`tinely obtained and are therefore expected regardless of the
`device dimensions. These outstanding electrical properties
`clearly present a significant challenge for any alternative gate
`dielectric candidate.
`
`II. SCALING AND IMPROVED PERFORMANCE
`
`The industry’s demand for greater integrated circuit
`functionality and performance at lower cost requires an in-
`creased circuit density, which has translated into a higher
`density of transistors on a wafer.3 This rapid shrinking of the
`transistor feature size has forced the channel length and gate
`dielectric thickness to also decrease rapidly. As will be dis-
`cussed in the next few sections, the current CMOS gate di-
`electric SiO2 thickness can scale to at least 13 Å, but there
`are several critical device parameters that must be balanced
`during this process.
`The improved performance associated with the scaling
`of logic device dimensions can be seen by considering a
`simple model for the drive current associated with a FET.1
`The drive current can be written 共using the gradual channel
`approximation兲 as
`
`␮Cinv冉 VG⫺VT⫺
`
`冊 VD ,
`
`VD
`2
`
`WL
`
`ID⫽
`
`共1兲
`
`where W is the width of the transistor channel, L is the chan-
`nel length, ␮is the channel carrier mobility 共assumed con-
`stant here兲, Cinv is the capacitance density associated with
`the gate dielectric when the underlying channel is in the in-
`verted state, VG and VD are the voltages applied to the tran-
`sistor gate and drain, respectively, and the threshold voltage
`is given by VT . It can be seen that in this approximation the
`drain current is proportional to the average charge across the
`channel 共with a potential VD/2兲 and the average electric field
`
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`

`

`J. Appl. Phys., Vol. 89, No. 10, 15 May 2001
`
`Appl. Phys. Rev.: Wilk, Wallace, and Anthony
`
`5245
`
`FIG. 1. Components used to test a CMOS FET technology. VDD and VS
`serve as the source and drain voltages, respectively, and are common to the
`NAND gates shown. Each NAND gate is connected to three others resulting
`in a fanout of 3.
`
`stage. The switching time is limited by both the fall time
`required to discharge the load capacitance by the n-FET
`drive current and the rise time required to charge the load
`capacitance by the p-FET drive current. That is, the switch-
`ing response times are given by1
`CLOADVDD
`ID
`
`␶⫽
`
`, where CLOAD⫽FCGATE⫹C j⫹Ci ,
`共5兲
`and C j and Ci are parasitic junction and local interconnec-
`tion capacitances, respectively. The ‘‘fan out’’ for intercon-
`nected devices is given by the factor ‘‘F.’’ Ignoring delay in
`gate electrode response, as ␶GATEⰆ␶n,p , the average switch-
`ing time is therefore
`␶p⫹␶n
`
`2 ⫽CLOADVDD再
`
`␶¯⫽
`
`p冎 .
`
`共6兲
`
`FIG. 2. FOM as a function of equivalent oxide thickness, teq . Parasitic
`capacitances and resistances result in transistor design tradeoffs to optimize
`performance.
`
`dielectric capacitance. This can be seen in Fig. 2 where vari-
`ous FOM calculations are plotted as a function of an
`‘‘equivalent oxide thickness,’’ teq , as described earlier.
`Each FOM calculation shown in Fig. 2 corresponds to
`specific assumptions on the values of parasitic capacitance
`and gate sheet resistance, as indicated 共gate length is kept
`constant in this analysis兲. Important aspects such as gate in-
`duced drain leakage and reliability are ignored in this simple
`model.1 Nevertheless,
`the result of the FOM calculation
`shown in Fig. 1 indicates that tradeoffs on all aspects of the
`transistor design and scaling, including parasitics, must be
`carefully considered in order
`to increase the circuit
`performance.8
`III. METAL–INSULATOR–SEMICONDUCTOR „MIS…
`GATE STACK STRUCTURES
`Figure 3 provides the reader a schematic overview of the
`various regions associated with the gate stack of a CMOS
`FET 共regions are separated simply to clarify the following
`discussion兲. The gate dielectric insulates the gate electrode
`共gate兲 from the Si substrate. Gate electrodes in modern
`CMOS technology are composed of polycrystalline Si 共poly-
`Si兲 which can be highly doped 共e.g. by ion implantation兲 and
`subsequently annealed in order to substantially increase con-
`ductivity. The selection of the dopant species and concentra-
`
`FIG. 3. Schematic of important regions of a field effect transistor gate stack.
`
`1
`IDn ⫹ID
`
`The load capacitance in the case of a single CMOS inverter
`is simply the gate capacitance if one ignores parasitic contri-
`butions such as junction and interconnect capacitance.
`Hence, an increase in ID is desirable to reduce switching
`speeds. For more realistic estimates of microprocessor per-
`formance, the load capacitance is connected 共‘‘fanned out’’兲
`to other inverter elements in a predetermined fashion. When
`coupled with other NMOS/PMOS transistor pairs in the con-
`figuration shown in Fig. 1, one can create a logic ‘‘NAND’’
`gate which can be used to investigate the dynamic response
`of the transistors and thus examine their performance under
`such configurations. For example, in microprocessor esti-
`mates, a fan out of F⫽3 is often employed, as shown in
`Fig. 1.1
`One can then characterize the performance of a circuit
`共based on a particular transistor structure兲 through this
`switching time. To do this, various ‘‘figures of merit’’
`共FOM兲 have been proposed which incorporate parasitic ca-
`pacitance as well as the influence of gate sheet resistance on
`the switching time.8 For example, a common FOM employed
`is related to Eq. 共6兲 simply by
`2
`FOM⬵ 1
`⫽
`␶¯
`␶p⫹␶n
`In the case where parasitics are ignored, it is easily seen
`then that an increase in the device drive current ID results in
`a decrease in the switching time and an increase in the FOM
`value 共performance兲. Even in this simple model, however,
`the incorporation of parasitic effects, results in the ‘‘clamp-
`ing’’ of FOM improvement, despite an increase in the gate
`
`.
`
`共7兲
`
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`

`

`5246
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`J. Appl. Phys., Vol. 89, No. 10, 15 May 2001
`
`Appl. Phys. Rev.: Wilk, Wallace, and Anthony
`
`FIG. 4. Energy-band diagrams and associated high-
`frequency C – V curves for ideal MIS diodes for 共a兲
`n-type and 共b兲 p-type semiconductor substrates. For
`these ideal diodes, V⫽0 corresponds to a flatband con-
`dition. For dielectrics with positive (⫹Q f) or negative
`(⫺Q f) fixed charge, an applied voltage (VFB) is re-
`quired to obtain a flatband condition and the corre-
`sponding C – V curve shifts in proportion to the fixed
`charge. 共after Refs. 9 and 10兲.
`
`tion permits the adjustment of the poly-Si Fermi level for
`either nMOS or pMOS FETs. Metals can also be used as the
`gate electrode, and, in fact, are commonly used for evalua-
`tion of capacitor structures. Work is underway to find suit-
`able metal gates for CMOS 共see Sec. VI E兲.
`The interfaces with either the gate or the Si channel re-
`gion are particularly important in regard to device perfor-
`mance. These regions, ⬃5 Å thick, serve as a transition be-
`tween the atoms associated with the materials in the gate
`electrode, gate dielectric and Si channel. As will be dis-
`cussed, these interface regions can alter the overall capaci-
`tance of the gate stack, particularly if they have a thickness
`which is substantial relative to the gate dielectric. Addition-
`ally, these interfacial regions can be exploited to obtain de-
`sirable properties. The upper interface, for example, can be
`engineered in order to block boron outdiffusion from the p ⫹
`poly-Si gate. The lower interface, which is in direct contact
`with the CMOS channel region, must be engineered to per-
`mit low interface trap densities 共e.g. dangling bonds兲 and
`minimize carrier scattering 共maximize mobility兲 in order to
`obtain reliable, high performance.
`It is instructive to consider the band diagrams for the
`MIS structures discussed in this review. Figure 4 shows the
`energy-band diagrams for ideal MIS diode structures using
`共a兲 n-type and 共b兲 p-type semiconductor substrates.9,10 For
`these ideal structures, at V⫽0 applied voltage on the metal
`gate, the work function difference between the metal and
`semiconductor, ⌽MS , is zero
`
`⌽MS⫽⌽M⫺冉 ␹⫹
`
`⫺⌿B冊 ⫽0;
`
`Eg
`2q
`
`n-type
`
`p-type,
`
`共8兲
`
`⌽MS⫽⌽M⫺冉 ␹⫹
`
`⫹⌿B冊 ⫽0;
`
`Eg
`2q
`where ⌽M is the metal work function, ␹is the semiconductor
`electron affinity, Eg is the semiconductor band gap, ⌽B is the
`potential barrier between the metal and dielectric, and ␺B is
`the potential difference between the Fermi level EF and the
`intrinsic Fermi level, EI . Under these conditions, the energy
`bands are flat across the structure as shown in Fig. 4 and V
`⫽VFB⫽0, where VFB is the flat band voltage 共i.e., the volt-
`age required to bring the Fermi levels into alignment兲. A
`more typical case is that the Fermi levels of the electrode and
`substrate are misaligned by an energy difference, and a volt-
`age (VFB⫽0) must be applied to bring the Fermi levels into
`alignment.
`Many dielectrics exhibit a fixed charge (Q f), however,
`resulting in a required applied voltage V⫽VFB⫽0 to achieve
`a flat band condition. The amount of fixed charge can be
`related to the measured VFB value by the expression9
`共9兲
`VFB⫽⌽MS⫾Q f /Cacc ,
`where Cacc is the measured capacitance in accumulation.
`Thus, a value for fixed charge density Q f can be determined
`from measured values of VFB , ⌽MS and Cacc . The sign of
`the fixed charge is also important, as negative fixed charge
`correlates with the plus sign in Eq. 共9兲, and positive fixed
`charge correlates with the minus sign. These expressions will
`be discussed further in Sec. V C 2.
`The source of such fixed charge, often though not always
`positive, is thought to originate from the detailed bonding of
`the atoms associated with the dielectric near the dielectric/
`
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`

`

`J. Appl. Phys., Vol. 89, No. 10, 15 May 2001
`
`Appl. Phys. Rev.: Wilk, Wallace, and Anthony
`
`5247
`
`semiconductor interface. Several proposed explanations for
`the cause of the observed fixed charge will be discussed in
`Sec. V C 2. Figure 4 shows that for positive Q f , a negative
`shift in the VFB from ideal conditions 共where V⫽0兲 is re-
`quired for both n-type and p-type MIS structures. Similarly,
`a positive VFB is required for negative Q f .
`Most of the alternate dielectric candidates examined to
`date appear to have a substantial amount of fixed charge,
`which could present significant issues for CMOS applica-
`tions. Given the scaling limitations on applied voltages due
`to power consumption, shifts in the VFB value are undesir-
`able and must be minimized. In some applications, biasing
`the substrate to compensate for the fixed charge has been
`proposed.5 Moreover, a reproducible VFB 共correspondingly
`VT for transistors兲 value is also required for stable, reliable
`transistor operation. Thus, hysteretic changes in the VFB from
`voltage cycling of less than 20 mV are often required.
`Some dielectrics which incorporate aluminum, however,
`thus far suggest that a negative fixed charge is present. It has
`been recently proposed to combine Al ions with some alter-
`nate dielectric candidates in order to compensate positive
`and negative fixed charges to achieve a neutral state or, at
`least, minimize such fixed charge effects.11 If fixed charge is
`determined to be large and difficult to minimize and control
`in high-␬dielectrics, it will be a significant issue for obtain-
`ing the desired device performance on both nMOS and
`pMOS transistors. The magnitude of measured VFB shifts for
`many alternate dielectrics will be discussed later.
`
`IV. SCALING LIMITS FOR CURRENT GATE
`DIELECTRICS
`
`The previous sections outlined the need to scale oxide
`thicknesses to improve performance. The next two sections
`describe the present understanding in the field regarding the
`limits of scaling current gate dielectric materials, SiO2 and
`Si-oxide-nitride variations, for CMOS. Issues include band
`offset, interfacial structure, boron penetration and reliability.
`Beyond this scaling limit, another material will be required
`as the gate dielectric to allow further CMOS scaling.
`A. Ultrathin SiO2 properties
`Experiments and modeling have been done on ultrathin
`SiO2 films on Si, as a way to determine how the SiO2 band
`gap or band offsets to Si change with decreasing film
`thickness.12–15 In the study by Muller et al.,12 electron en-
`ergy loss spectroscopy 共EELS兲 was carried out on 7–15 Å
`SiO2 layers on Si. It was found that the density of states 共as
`measured by the oxygen K-edge in EELS, with a probe reso-
`lution ⬍2 Å兲 transition from the substrate into the SiO2 layer
`indicated that the full band gap of SiO2 is obtained after only
`about two monolayers of SiO2. This indicates that within two
`monolayers of the Si channel interface, oxygen atoms do not
`have the full arrangement of oxygen neighbors and therefore
`cannot form the full band gap that exists within the ‘‘bulk’’
`of the SiO2 film.
`
`An earlier ab inito model by Tang et al.13 of extremely
`thin SiO2, which was modeled as a modified beta-
`cristoballite phase, showed an important result, in that the
`band gap of SiO2 did not begin to decrease until there were
`fewer than three monolayers of oxide. Moreover, estimates
`of the changes in the associated conduction and valance band
`offsets for these systems indicated that a minimum of 7 Å of
`SiO2 is required to obtain bulk properties. The recent first
`principles study by Neaton et al.14 determined that the local
`energy gap in SiO2 is directly related to the number of O
`second nearest neighbors, for a given O atom. The last row
`of O atoms 共next to the Si substrate兲 by definition cannot
`have the full six nearest neighbor O atoms. The second row
`of O atoms from the Si interface is thus the first layer of O
`atoms that have the required six second-nearest neighbor O
`atoms. The distance required to obtain the full band gap of
`SiO2 at each interface is therefore given by 1.6 Å 共the spac-
`ing of one Si–O bond length兲 ⫹2.4 Å 共the distance between
`neighboring O atoms is 2.7 Å, but this is variable because of
`Si–O bond bending. The distance is typically in the range
`⬃2 to 2.4 Å兲. The thickness at each interface required for the
`full SiO2 band gap is therefore ⬃3.5–4.0 Å. Counting both
`interfaces, the total thickness of 7–8 Å is required, in agree-
`ment with Tang et al.13 and with the experiment.12 These
`results set an absolute physical thickness limit of SiO2 of 7
`Å. Below this thickness, the Si-rich interfacial regions from
`the channel and polycrystalline Si gate interfaces used in
`MOSFETs overlap, causing an effective ‘‘short’’ through the
`dielectric, rendering it useless as an insulator.
`The agreement between the experiment and simulation
`in these cases indicates that the inherent band gap of SiO2
`remains intact, even down to only a few monolayers of ma-
`terial. Other important properties of SiO2 have been reported
`in the ultrathin, sub-20 Å regime, such as the conduction
`band offset ⌬EC to Si 关using x-ray photoelectron spectros-
`copy 共XPS兲兴,16 the tunneling electron effective mass m*
`共from tunneling I – V measurements兲,17 and the photoelectron
`attenuation length.18 These measurements have further dem-
`onstrated very little change in fundamental SiO2 properties
`between bulk and ultrathin sub-20 Å films.
`The apparent robust nature of SiO2, coupled with indus-
`try’s acquired knowledge of oxide process control, has
`helped the continued use of SiO2 for the past several decades
`in CMOS technology. As experimental evidence of the ex-
`cellent electrical properties of such ultrathin SiO2 films, it
`has been demonstrated that transistors with gate oxides as
`thin as 13–15 Å continue to operate satisfactorily.19–24 Al-
`though high leakage current densities of 1–10 A/cm2 共at
`VDD兲 are measured for such devices,25 transistors intended
`for high-performance microprocessor applications can sus-
`tain these currents. As first reported by Timp et al.20–22 scal-
`ing of CMOS structures with SiO2 gate oxides thinner than
`about 10–12 Å results in no further gains in transistor drive
`current. This result has been subsequently and independently
`reported by other groups, thus 10–12 Å could serve as a
`practical limit for reducing the SiO2 thickness.23,24,26
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`ing must be ‘‘accelerated’’ at higher voltages and tempera-
`tures than are actually experienced by typical devices. Mak-
`ing reliability projections
`from accelerated to actual
`conditions requires proper scaling for area 共from one device
`area to an entire chip area兲, voltage, temperature, and the
`failed fraction of devices.27,32 Recent results by Stathis
`et al.,31 Weir et al.,25 and Nicollian et al.33 show that ex-
`trapolations of reliability factors, such as the critical defect
`共trap兲 density, with voltage scaling changes dramatically at
`lower voltages, such as those used for testing oxides ⬍20 Å
`thick. This realization of the change in voltage scaling be-
`havior at low voltages is the largest factor contributing to the
`improved reliability projections described earlier. In addi-
`tion, improved macroscopic oxide uniformity across the wa-
`fer and wafer-to-wafer has also been shown to give more
`accurate reliability projections.25,34 This analysis should not
`be misinterpreted as meaning that the oxide reliability itself
`is improved. Rather, the reliability projection becomes more
`accurate 共regardless of whether the projection is for good or
`poor oxide reliability兲 with higher macroscopic oxide
`uniformity.35
`Improving microscopic oxide uniformity
`should further produce more accurate reliability projections,
`according to simulation.36 It has also been demonstrated that
`making reliability measurements on a large number of
`samples is important for obtaining better breakdown statis-
`tics and accurate projections.34
`A fundamental mechanism for oxide breakdown in this
`ultrathin SiO2
`regime was first
`reported by DeGraeve
`et al.37,38 as a percolation model. This model describes ultra-
`thin oxide breakdown as the buildup of many ‘‘defects’’
`within the SiO2 layer, where after a certain amount of stress
`共either constant voltage or constant current through the oxide
`at a given temperature兲, a complete path of defects form
`across the oxide thickness.37 This point defines breakdown or
`failure of the oxide. While there is general agreement on the
`percolation model for oxide breakdown, the defects which
`act as precursors to breakdown are not defined or specified.
`The mechanism which leads to the creation of these defects
`is under debate, and has been proposed as an anode hole
`injection model36,39 and a hydrogen release model.40,41
`It is also important to distinguish between previously
`reported leakage current projections by simulation for oxide
`thicknesses measured in accumulation, and the presently ac-
`cepted methods.25,31,33 Extrapolated leakage current versus
`gate oxide thickness data from three to five years ago was
`valuable at the time, when sufficient data for oxides ⬍16 Å
`was not available. Caution should be used, however, when
`referring to such extrapolations now,42 as data from more
`recent measurement methodology must be adopted for useful
`comparisons. Much of the understanding for ultrathin oxides
`have come about only in the past five years, despite decades
`of research on SiO2. This suggests that understanding the
`reliability and failure mechanisms in high-␬dielectrics will
`require significant effort, especially if any material is to re-
`place SiO2 within five years, as most roadmaps suggest.
`C. Boron penetration and surface preparation
`In addition to leakage current increasing with scaled ox-
`ide thickness, the issue of boron penetration through the ox-
`
`FIG. 5. Power consumption and gate leakage current density for a chip
`which has a 15 Å thick SiO2 gate dielectric compared to the potential re-
`duction in leakage current by an alternate dielectric exhibiting the same
`equivalent oxide thickness. Assumes at total gate area of 0.1 cm2.
`
`In contrast to the high performance microprocessor mar-
`ket, the rapidly growing market of low-power applications
`requires transistors with much lower (⬃10⫺3 A/cm2) leak-
`age currents.5 This is illustrated in Fig. 5, where the current
`density and standby power consumption are plotted as a
`function of gate voltage. The curve for 15 Å oxide is based
`on measured values,17 but the curve for a high-␬ film is
`meant to show the potential reduction in leakage current for
`a high-␬dielectric with the same teq value. Depending on the
`specific materials and conditions, leakage current reduction
`may be less than shown. It is clear that a gate dielectric with
`a permittivity higher than that of SiO2 is required to meet
`low-power application requirements.
`
`B. Ultrathin SiO2 reliability
`An equally important issue regarding ultrathin SiO2 gate
`oxides has been understanding and predicting oxide reliabil-
`ity. Considerable debate existed over whether SiO2 gate ox-
`ides ⬍22–27 Å thick would exhibit the stringent ten year
`reliability criteria,27 which is required for CMOS devices.
`The first report of a sub-20 Å SiO2 gate oxide to meet reli-
`ability requirements was given by Weir et al.,25 where a 16
`Å oxide was shown to have reliability projections at 1.6 V
`operation for greater than ten years. This is much thinner
`than projected even three to five years ago.28,29 The high
`reliability of ultrathin oxides suggests that there is no intrin-
`sic 共i.e., not limited by intrinsic defects or thickness varia-
`tions兲 reliability limitation to SiO2 layers at least down to
`thicknesses of about 16 Å. In fact, more recent projections
`indicate that oxides down to 14 Å 共as measured by ellipsom-
`etry兲 at 1.4 V operating voltage will meet ten year reliability
`requirements.30 Several independent groups have also re-
`cently reached similarly encouraging reliability projections
`for such thin SiO2 gate oxides.26,31 Other extrinsic reliability
`factors, however, such as particles or contaminants, could
`still yield an ultimately poorer oxide reliability.
`Part of the difficulty in making reliability projections
`arises from the difference between test conditions and oper-
`ating conditions. It is clearly not feasible to test individual
`devices for ten years prior to product incorporation, thus test-
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`Appl. Phys. Rev.: Wilk, Wallace, and Anthony
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`5249
`
`ide is a significant concern. The large boron concentration
`gradient between the heavily doped poly-Si gate electrode,
`the undoped oxide and lightly doped Si channel causes boron
`to diffuse rapidly through a sub-20 Å oxide upon thermal
`annealing, which results in a higher concentration of boron
`in the channel region. A change in channel doping then
`causes a shift in threshold voltage, which clearly alters the
`intended device properties in an unacceptable way.43 As will
`be discussed in the next section, incorporating nitrogen into
`the oxide can greatly reduce boron diffusion.
`Some approaches to enhance performance have also fo-
`cused on surface preparation as a way to provide a flatter,
`more uniform Si interface in attempts to minimize electron
`channel mobility degradation 共due to scattering at the inter-
`face兲 and gate leakage.44,45 Growing or depositing sub-15 Å
`oxides has also been investigated as a potential means for
`producing high-quality, re