`
`584
`
`IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 38, NO. 3. MARCH 199!
`
`Hot-Carrier Injection Suppression Due to the
`Nitride—Oxide LDD Spacer Structure
`Tomohisa Mizuno, Member, IEEE, Shizuo Sawada, Yoshikazu Saitoh, and Takeshi Tanaka
`
`Abstract—Hot carrier effects in silicon nitride LDD spacer MOS-
`FET’S have been investigated. It is found that the oxide thickness un-
`der the nitride film spacer afl'ects hot-carrier effects. The thinner the
`LDD spacer oxide becomes, the larger the initial drain current deg-
`radation becomes at dc stress test and,
`in addition, the smaller the
`stress time dependence becomes. Moreover, after the dc stress test,
`reduced drain current recovers at room temperature. These phenom-
`ena are due to the large hot-carrier injection into the LDD nitride
`spacer, because the nitride film barrier height is much less than the
`silicon oxide barrier height. Therefore, it is necessary to form the LDD
`spacer oxide, in order to suppress the large hot-carrier injection in the
`nitride film LDD spacer MOSFET. Furthermore, the drain current
`shift mechanism in the nitride LDD spacer MOSFET's is also dis-
`cussed, considering the lucky electron model.
`
`I.
`
`INTRODUCTION
`
`ENERALLY. CVD~SiO2 material has been used as the
`LDD spacer [1]. Recently, LDD MOSFET‘s with a silicon
`nitride spacer were studied [2], [3]. Howevcr, the nitride spacer
`is reported to cause large degradation in LDD MOSFET’s, the
`mechanism of which is not quite clear [2]. Moreover, while it
`is known that LDD MOSFET degradation is due to the hot-
`carricr injection into the LDD spacer [4], the LDD spacer ma—
`terial influence on hot-carrier eiiects has not been investigated
`in detail.
`It has been previously reported that the dielectric constant of
`LDD spacer affects LDD MOSFET perfonnancc [5]. In addi—
`tion, when the dielectric constant of LDD spacer increases, the
`gate—fringing field becomes large. Therefore, because of this
`large gate—fringing field, high reliability and high current driv—
`ability can he realized in high dielectric LDD spacer MOS-
`FET’s (HLDD). However, with increasing the dielectric con-
`stant for an insulator,
`its bandgap energy decreases [6]. As a
`result,
`the barrier height for the high dielectric insulator de—
`creases, which causes a large hot-carrier injection into its LDD
`spacer. Therefore, it is important to fomi the large barrier height
`insulator such as Si02 under the high dielectric LDD spacer.
`In this paper, the authors discuss the influence of the sidewall
`SiO2 thickness on the hot—carrier effects in Si3N4 or SiO2 LDD
`spacer structure [7], which can be explained by the luckey elec-
`tron model, and thc LDD spacer oxide thickness is believed to
`play an important role in the MOSFET reliability. Moreover,
`we show relaxation phenomena of the MOSFET degradation
`after dc stress test.
`
`Manuscript received May 23. 1990; revised September 18, 1990. The
`review of this paper was arranged by Associate Editor R. B. Fair.
`'1‘. MizunO, S. Sawada, and T. Tanaka are with tho Semiconductor De-
`vice Engineering Laboratory. Toshiba Corporation, 1, Komukai Toshiba»
`cho, Saiwai-ku, Kawasaki 210, Japan.
`Y. Saitoh is with Toshiba Microelectronics Corporation, 1, Komukai,
`Toshiba—Che, Saiwai-ku, Kawasaki 210, Japan.
`IEEE Log Number 9041427.
`
`
`
`Fig. 1. Schematic cross sections of three different LDD spacer structures.
`(a) Si; N4 on SiO2 LDD spacer structure (ONLDD). (b) Only SEN, film
`structure (NLDD). (c) Conventional SiOz LDD spacer (OLDD).
`
`II. EXPERIMENTAL PROCEDURE
`
`Three types of LDD spacer structures were fabricated as
`shown in Fig. 1: (a) an LPCVDeSi3N4 film on thcrmal oxide
`(which is called the sidewall oxide) spacer (ONLDD), (b) an
`LPCVD-Si3N4 film spacer (N-LDD), and (c) a conventional
`CVDeSi02 film on a thermal oxide spacer and an only CVD—
`SiO2 film spacer (O-LDD). An n—channel LDD MOSFET with
`the ONLDD structure was fabricated by reactive ion etching of
`0.2-um-thick deposited LPCVD—Si3N4 on the sidewall oxide.
`In both the nitride and the oxide film LDD spacer structures.
`the sidewall oxide was formed by dry 02 oxidation just after
`forming the gate electrode and LDD n’ region. Sidewall oxide
`thickness T0X conditions at the Si surface were changed by dry
`02 oxidation time and arc 0, 15, and 25 nm. The ONLDD hot—
`carrier effects were investigated, comparing to those of the
`NLDD structure (2.5~nm—thick native oxide) and the OLDD
`structure. LDD spacer width is about 0.2 pm. The gate poly-
`silicon length and the channel width are 0.8 and 10 um,
`re—
`spectively. The p—well region and the LLB n‘ region concen—
`tration are about 2 X 1017 cm’ 3 and 5 X 1018 cst,
`respectively. Gate oxide thickness Tg is 15 nm.
`
`0018-9383/91/0300-0584$01.00 @ 1991 IEEE
`
`TSMC 1127
`
`TSMC 1127
`
`

`

`585
`
`T'BOOK
`
`[Va -ev. vqssv STRESS]
`
` 0|
`
`10°
`
`103
`102
`IO'
`STRESS TIME (SEC)
`Fig. 2. Drain current degradation rate at dc stress test
`Vg = 3 V).
`
`to4
`
`(V,, = 6 V,
`
`
`—OD/
`V9 =3V, Vd =6V STRESS
`/O
`’.,-o-0
`
`OO
`
`NLDD
`
`10‘?
`10-2
`
`Lpoly=0.8 pm
`J
`|
`l
`1
`Io2
`IO'
`|O°
`I0"
`STRESS TIME (SEC)
`
`I03
`
`Fig. 3. Substrate current degradation rate at the same dc stress test as in
`Fig. 2.
`-
`
`
`lOO
`
`vg = 3v, vd = 6V STRESS
`
`10
`
`I
`
`SE
`T’
`
`I §4
`
`10°
`
`
`
`.
`l
`.
`103
`to2
`10‘
`STRESS TIME (SEC)
`
`to“
`
`Fig. 4. Threshold voltage shift versus Stress time at the same dc stress test
`as in Fig. 2.
`
`oxidation process and depend on the sidewall oxide as men-
`tioned above. This is considered to be due to the reason that the
`gate to n’
`region overlap length is longer than that of the gate
`bird’s beak [17].
`The band diagram at the LDD spacer is shown in Fig. 5. It
`shows the schematic energy band diagram across the electric
`field from the drain 11— region to the gate electrode in ONLDD
`or NLDD. The trap level in Si3N4 film is reported to be very
`shallow and be about 0.8 eV by Svensson er al. [9]. Therefore,
`the injected hot electron cannot be trapped in the nitride film or
`the trapped hot electron can be detrapped. Namely, the injected
`hot electron can be trapped only in the oxide. Since the hot
`carrier is mainly injected into the LDD sidewall region and is
`trapped only in the LDD sidewall oxide, the V”, shift is caused
`by the trapped charge in the LDD sidewall oxide. In addition,
`since the injected hot carrier is considered to be uniformly trap—
`ped in the LDD sidewall oxide, the Vm shift is condsidered to
`be proportional to the square of the LDD sidewall oxide thick—
`ness [10]. Therefore, V”, does not shift in the case of NLDD as
`shown in Fig. 4, because of its very thin sidewall oxide.
`2) Stress Time Dependence in the Nitride LDD Spacer
`Structure: Generally,
`Id degradation rate is experimentally
`
`MIZUNO El al.: HOT-CARRIER INJECTION SUPPRESSION
`
`Drain current characteristics of chD MOSFETS after dc
`stress test were measured at the drain and gate biases of 3.3 V
`in the reverse mode to the stress condition. The substrate bias
`is — 1.5 V, in order to improve the subthreshold characteristics.
`The ONLDD and the OLDD data are mainly those with 25—
`nmethick sidewall oxide.
`
`111. RESULTS AND DISCUSSION
`
`A. Drain-Current Degradation Phenomena
`
`1) DC Stress Test: Fig. 2 shows the drain—current degrada-
`tion rate AId/Id versus stress time t at dc stress test of Vd = 6
`V, Vg = 3 V. NLDD data show the large degradation of the
`drain current at very small stress time. As LDD spacer oxide
`thickness becomes thick, such as ONLDD and OLDD, the ini-
`tial drain current degradation becomes small. On the contrary,
`the stress time dependence of drain current degradation be-
`comes small when the LDD spacer oxide becomes thin, such as
`NLDD. Fig, 3 shows the substrate current reduction rate as a
`function of the stress time at the same dc stress conditions as in
`Fig. 2. The substrate current was measured at the same dc stress
`biases in the forward mode. It is also found that the stress time
`dependence of the substrate~current shift is affected by the LDD
`spacer oxide thickness, and the substrateecurrent shift depen—
`dence on stress time in NLDD is about two magnitudes faster
`than the ONLDD data. The substrate current shift in NLDD
`starts at about 10 ms.
`0n the other hand, in the case of an NLDD, when the LDD
`spacer oxide thickness is nearly equal to zero, V,h values are not
`changed at dc stress test, as shown in Fig. 4. However, Vth
`Shifts in the case of both ONLDD and OLDD. These phenom-
`ena can be explained by the following discussion.
`According to the discussion by Katto [8], trapped charges in
`the LDD spacer also cause the V,h shift even in an LDD MOS-
`FET. Therefore, NLDD data shown in Figs. 2 and 4 indicate
`that in NLDD the injected hot electron does not get trapped and
`can generate only the interface state in NLDD sidewall struc»
`ture. This generated interface state is considered to cause the
`transconductance degradation in NLDD, resulting in the drain
`current shift in NLDD shown in Fig. 2.
`We estimate the 1,, shift rate due to the only trapped charge.
`Since the drain current is proportional to (V8 — V,,,) in a short»
`channel MOSFET [14], the Id shift rate due to the trapped charge
`can be expressed as follows:
`
`AV“.
`it!
`S
`V _Vth
`Id
`
`(1)
`
`where A1,, and AV”, are the 1,, shift and Vm shift, respectively.
`According to the V,h shift data at 1 h shown in Fig. 4, the Id
`shift rate for NLDD, ONLDD, and OLDD can be calculated to
`be about 0%, 0.7%, and 0.7%, respectively. Since the 1,, shift
`for NLDD, ONLDD, and OLDD are about 4%, 3%, 1.5%,
`respectively, as shown in Fig. 2, the trapped charge causes less
`than one half of the total Id shift. Therefore, it is found that the
`1,, shift is mainly caused by the interface state generation.
`However, the OLDD data with 0 and 15-nm-thick sidewall
`oxide were almost the same as those at T,,X = 25 nm shown in
`Figs. 2 and 4. In the case of OLDD, sidewall oxide thickness
`did not affect the hot-carrier effects. Namely, the gate bird’s
`beak does not affect hot—carrier effects in OLDD. Therefore, it
`is found that hot-carrier eifects in both ONLDD and NLDD are
`not affected by the gate bird’s beak formed from the sidewall
`
`

`

`
`
`586
`
`IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 38. NO 3. MARCH l99|
`
`l 0.0
`
`(7o)
`
`1.0
`
`Aid/Id
`
`103
`
`SUBSTRATE CURRENT ( FA)
`Fig. 6. Drain current degradation, as a function of the initial substrate cur
`rent at the I—h dc stress test (Vg = 3 V, V,, = 6 V) in various gate
`lengths.
`
`2.0
`
`10
`E 0.6
`
`vq-av
`
`.
`°
`O’O/ Va 6V
`
`
`
`5 0'4 /e maTgx
`0'2
`0'1
`
`D E
`
`vd-ev STRESS
`
`l
`1
`lOO
`IO
`SIDE-WALL Si02 THICKNESS(nm)
`Fig. 7. Index m in (2) versus the LDD spacer oxide thickness at the dc
`stress test ( Vg = 3 V, Vd = 6 V). The solid lines show the Tox power law
`of index In.
`
`to
`0.8
`0.6
`
`04
`
`0.2
`0|
`
`E
`
`Lo
`08
`0.6
`
`“304
`
`x g
`
`E 02
`0|
`
`Va - 6V STRESS
`
`
`
`4
`2
`STRESS GATE BIAS (V)
`
`6
`
`0
`
`Fig. 8. Parameters [3 and mo in (3) versus stress gate bias. Closed and open
`circles show [3 and mo, respectively.
`
`NLDD, in order to reduce the substrate current dependence of
`the index m.
`Next, according to Fig. 2, parameters A and a in (2) are de-
`pendent on the LDD spacer oxide thickness under the nitride
`film spacer. Moreover, as the LDD spacer oxide becomes thin,
`the initial degradation parameter A becomes large. On the con—
`trary, the stress time coeflicient (1 becomes small. By fitting the
`1,, shift data at various stress gate bias values to (2), we have
`determined the LDD spacer oxide thickness dependence of pa-
`rameters A and 01.
`Fig. 9 shows the initial degradation parameterA as a function
`of T0,. According to Fig. 9, A is clearly proportional to the
`inverse of the power of T0,. That is.
`
`A : Aorgj
`
`(5)
`
`where A0 and 6 are parameters.
`
`TRAP STATE
`/'\
`
`GATE
`
`st
`\ INTERFACE
`STATE
`
`Si02
`
`
`
`SI02
`Fig. 5. Schematic band diagram of the Si; NA/SiO2 spacer structure across
`the electric field from the drain nT region to the gate electrode. Interface
`states exist at both the Si; N4/Si01, and the SiOZ/Si interfaces. Moreover.
`trap levels also exist in both the Si; N4 and the SiOZ films.
`
`given by the stress time power law as follows [I l]:
`
`—" = IZ'AI“
`
`(2)
`
`where 1,, is the substrate current and A, at, and m are parameters.
`Physical meaning of these parameters has not been clear, but
`these parameters are very important to predict the lifetime for
`the devices in the hot-carrier effects. Moreover, these parame
`ters are obtained by fitting (2) to the data as shown in Fig. 2.
`This section discusses the LDD spacer oxide thickness de—
`pendence of parameters in (2) at the fixed stress drain bias of6
`V. Moreover, it is shown that all parameters in (2) can be ex-
`pressed by a function of the sidewall oxide thickness. Since the
`LDD spacer oxide thickness is relatively small in this study and
`the dielectric constant for the nitride film is not large, the gate-
`fringing field in both NLDD and ONLDD [5] is not affected by
`the LDD spacer oxide thickness and is not large.
`Index m in (2) is determined by changing the gate length.
`Fig. 6 shows the drain current degradation rate for a l—h dc
`stress test versus the substrate current at various gate lengths.
`It is clear that the Id shift is proportional to the power of the
`substrate current. However,
`index m is changed by the LDD
`spacer oxide thickness. Fig. 7 shows index m versus LDD
`spacer oxide thickness. As shown in Fig. 7, m becomes small,
`when the LDD spacer oxide becomes thin. At Vg = 3 V, pa—
`rameter m of the thicker sidewall oxide devices is about 1 and
`is almost the same as that of Kinugawa et al. (~0.9) [ll]. In
`addition, index m is proportional to the power of the LDD spacer
`oxide thickness To, as follows:
`
`m 2 m0 Tgx
`
`(3)
`
`where m0 and (3 are parameters.
`If T0x becomes zero, the Id shift does not depend on the sub-
`strate current. Therefore,
`the 1,, shift in NLDD remains con-
`stant,
`in spite of an increase in the stress drain bias and the
`shrinking gate length.
`Fig. 8 shows the stress gate bias dependence for parameters
`m0 and B in (3). According to Fig. 8, since 6 is about 0.5 at Vg
`< 4 V, index m can be expressed as follows:
`
`m : mOTgtj.
`
`(4)
`
`Since, in the case of V8 > 4 V, mg is constant at 0.3 and 6
`decreases in V‘g > 4 V, T0X dependence of index m becomes
`small. This is due to the large hot-electron injection rate in large
`stress gate bias. As a result, at shorter channel length, it is im»
`portant
`to reduce the LDD spacer oxide thickness, such as
`
`

`

`MIZUNO at al.: HOTCARRIER INJECTION SUPPRESSION
`
`587
`
`
`Vd=6V STRESS
`
`|O°
`
`6O I
`4/
`° \ A¢T0;"
`
`A A
`\ Vq=6V
`
`lo-Z-
`
`
`
`INITIALDEGRADATIONPARAMETER.A IO" —
`
`
`IO-s—Lj_41__
`IO
`IOO
`SIDE‘WALL SiOz THICKNESS (rim)
`
`
`
`Fig. 9. Initial degradation parameterA versus the LDD spacer oxide thick,
`ness. Solid lines show the Tox power law of A.
`
`vd -ev STRESS
`
`INDEX,8O.0.0.—G)mo
`
`In.
`
`Dl\)
`
`0'0
`
`4
`2
`STRESS GATE BIAS (V)
`
`6
`
`I
`
`Fig. 10. Parameters 6 and A0 in (5) versus stress gate bias. Closed and
`open circles show 5 and A0, respectively,
`
`Fig. 10 shows parameters A0 and 6 as a function of stress gate
`bias. By fitting data to (5), 5 is about 2 in Vg < 4 V, resulting
`in A oc 1/rg,, as shown in Fig. 10. As a result, the initial deg—
`radation parameter A becomes large in decreasing TO“ by the
`1 /T(2,x law. Moreover, A0 and 5 suddenly decrease in VS > 4
`V.
`
`Consequently, in order to reduce the initial degradation, it is
`necessary to thicken the LDD spacer oxide, such as OLDD
`structure.
`
`Finally, Fig. 11 shows the stress time coeflicient oz versus the
`LDD spacer oxide thickness Tux. In thicker sidewall oxide de-
`vices, or is about 0.2 and is almost the same as that of Kinugawa
`et a1. ( ~02) [l 1]. It is obvious that or is proportional to the
`power of Tax. Therefore, a can be expressed as follows:
`
`a : c{Orb‘x
`
`where 010 and n are parameters.
`The stress time coefficient 01 becomes small with a decrease
`in Tox and becomes zero in the case of LDD structure without
`the oxide. This means that the Id shift of a no—oxide LDD spacer
`becomes constant, in spite of the increase of the stress time.
`By fitting data to (6),
`index n in (6) is shown by the open
`circles in Fig. 12. Index n is a constant unity in V1, < 4 V,
`resulting in a or T0,. However, n decreases varied from 1
`to
`0.2 in V5, > 4 V. On the other hand, (20 is almost constant at
`V3 < 3 V, but increases at Vg > 3 V.
`
`
`
`vd = ev STRESS
`
`INDEX,(1 5 IO'?
`
`102
`IO'
`I00
`SIDE-WALL SiOa THICKNESS (nm)
`
`Fig. ll, Stress time coefficient a versus Tm. Solid lines show the TM power
`law of or.
`
`
`
`STRESS GATE BIAS (V)
`
`Fig. 12. Parameters n and 010 in (6) versus stress gate bias. Closed and
`open circles show n and (10, respectively.
`
`Consequently, parameters m, A, and or in (2) strongly depend
`on LDD spacer oxide thickness. In addition, the initial degra~
`dation parameter dependence on the LDD spacer oxide thick—
`ness is opposite to the stress time coeflicient dependence.
`Therefore,
`it
`is important to optimize the LDD spacer oxide
`thickness in order to realize highly reliable LDD MOSFET’s.
`According to the above discussion, drain current shift equa4
`tion (I) can be expressed by the LDD spacer oxide thickness.
`in the case of the maximum substrate current dc stress test con-
`ditions, as follows:
`
`A_Id = IZIUVTOK 14—? ["070xv
`[d
`TEX
`
`On the other hand, it is clear that the dependence of all pa-
`rameters in (2) on T0x becomes smaller at a larger stress gate
`bias. This is probably due to the high hot—carrier injection rate
`at larger stress gate bias conditions. In the case of other drain
`stress bias conditions, parameters in (2) can be also obtained by
`fitting data to (2), but parameters in (2) are considered to be
`different from the values in (7) because of their different hot—
`carrier injection rate.
`3) Stress Drain Bias Dependence: Fig. 13 shows the stress
`drain bias dependence of the Id shift at the maximum substrate
`current dc stress test for 1 h. In the case of NLDD, the Id shift
`does not increase and remains constant,
`in spite of increasing
`stress drain bias at Vd > 5 V. This is caused by the weak sub
`strate current dependence and small stress time coefficient in
`NLDD as mentioned before.
`
`Moreover, the Id shift of NLDD is observed in a small stress
`drain bias region of NLDD, compared to ONLDD data. This
`indicates that the interface state in NLDD can be generated by
`low—energy hot carriers. On the other hand, no Id shift
`in
`
`

`

`
`
`588
`
`IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 38. NO. 3. MARCH 1991
`
`
`
`IO
`
`8
`6
`
`
`
`Aid/Id(7a) 4
`
`2
`0
`
`l
`
`‘
`
`vgsizvd I"-STRES$
`
`NLDD
`
`'
`
`Lp,.,=o.e,.m
`A/
`
`mom
`,
`
`
`I
`A
`
`./ I]! /O
`
`/ o ONLDD
`| 2/
`l
`6
`4
`2
`STRESS DRAlN V0! TAGF H11
`
`
`
`8
`
`AId/Id(%)
`
`4.50
`
`5.5 r——————_—
`Vq=Vd=Vsub =0V
`T“~~~~ ~~
`480 K
`5.0“"“ _’__i_ 36153::2 300 K
`
`
`
`RECOVERY TIME (XIO‘SEC)
`
`Fig. [4. Relaxation phenomena of the drain current shift rate to the initial
`current, after dc stress test (V8 = 3 V, Vd = 6 V) for 5 h, The relaxation
`bias conditions are all terminal grounded in MOSFET‘s.
`
`STRESS
`
`V; =-_;_-Vd
`
`4
`
`N
`
`‘2
`
`0
`
`mum \
`o-O‘§\° O
`o--———-f————?v-
`
`TIME (M04 SEC)
`Fig. 15. Drain current shift rate behavior, at and after dc stress test, as a
`parameter of stress drain bias. DC stress test at t < 0 stops at t z 0 and
`the relaxation lest is carried out in t > 0. By the way, the result of NLDD
`around I = 0 s is the data for I = — 10 s.
`
`Fig. 13. Drain current shift versus stress drain bias at the maximum sub-
`strate current dc stress test for l h.
`
`ONLDD is observed in small stress drain bias, which indicates
`that LDD spacer oxide suppresses the low-energy hot-carrier
`injection. However, stress drain bias dependence of the drain
`current shift becomes large in ON LDD and OLDD. Especially
`in OLDD, the drain current at 7 V stress drain bias becomes
`larger than that of NLDD, because of the farmer’s large stress
`time coefficient.
`Consequently, high reliability in the ONLDD structure can
`be realized by both the LDD spacer oxide suppression of hot-
`carrier injection and the gate—fringing field effects [5].
`
`B.
`
`Id-Shifi-Relaxan'on Phenomena in NLDD
`Generally, the 1,, shift in MOSFET does not recover after dc
`stress test. Here, Fig. 14 shows the reduced drain current re-
`laxation phenomena after 5-h dc stress test (Vg : 3 V, Vd : 6
`V), where all terminals biases for MOSFET’s are 0 V. In
`NLDD, reduced drain current is recovered at room temperature.
`Moreover, its relaxation time constant 1 at room temperature is
`nearly equal to that at high temperature (400 K). These results
`indicate that
`the activation energy for the interface state in
`NLDD is very small and is considered to be almost equal to the
`room temperature thermal energy. According to this small ac-
`tivation energy in NLDD, the interface state between SiJ N4 and
`the native oxide is considered to be generated by low—energy
`hot-carrier injection, which causes the large initial degradation
`parameter, shown in Fig. 9, and the Id shift in low stress drain
`bias, shown in Fig. 13.
`On the contrary, in the OLDD structure, reduced drain cur—
`rent does not recover, even at high temperature. According to
`these data, the time constant is very large in OLDD, which is
`considered to be due to high activation energy of the SiOz/Si
`interface. Therefore, high activation energy in OLDD sup-
`presses the initial dcgradation parameter, compared to that in
`NLDD.
`Moreover, new recovery data for the Id shift in NLDD are
`also shown in Fig. 15. which shows the Id shift phenomena as
`a parameter of dc stress drain bias, at and after the dc stress
`test. In Fig. 15. the dc stress test at t < 0 stops at t = O and a
`relaxation test is carried out at r > 0. It has been recently found
`that reduced drain current does not recover at all in low stress
`drain bias conditions. That is, at Vd = 4 V stress test reduced
`drain current does not recover at all, in spite of the same Id shift
`as that at Vd = 6 V dc stress test. Moreover. according to Figs.
`14 and 15, reduced drain current cannot completely recover and
`its relaxation rate (which is defined by the Id shift rate after
`relaxation test minus the maximum Id shift at the dc stress test)
`is about 1%.
`
`,2 , AFTER vil =—l2'Vd «STRESS
`(Lpoly=0.8;i.m) ./.—'
`LO.—
`
`
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`STRESS DRAIN VOLTAGE (V)
`
`O'IONLDD
`
`NLDD
`
`'
`
`o
`I’
`
`,’
`,0I
`
`Fig. 16. Relaxation rate 011,, shil‘t versus stress drain bias at the maximum
`substrate current dc stress test. Sidewall oxide thickness of ONLDD is 15
`nm in this figure. Relaxation rate is defined as the Id shift rate after the
`relaxation test minus the maximum 1,, shift at the dc stress test.
`
`Fig. 16 shows the [d shift relaxation rate as a function of do
`stress drain bias at the maximum substrate current dc stress test.
`The Id shift can recover, when the stress drain bias becomes
`larger than 5 V, and is not observed at a stress Vd < S V. In
`addition, the relaxation rate of the Id shift approaches a satu—
`rated value (about 1%) with increasing stress drain bias and
`
`

`

`
`
`MIZUNO or £11.: HOTeCARRIER INJECTION SUPPRESSION
`
`589
`
`AFTER DC STRESS
`
`RELAXATIONOFIdWu)
`
`IO'
`
`104
`1o3
`102
`RELAXATION TIME (SEC)
`
`105
`
`'
`
`/
`['mi-(réaaimii
`LP =O.8p.m
`
`Fig, 17. Recovery rate of 1,, shift versus relaxation time in NLDD.
`
`there is a turning point at around VJ = 5 V. On the other hand,
`even in the ONLDD structure, the 1,, shift is also recovered at
`stress Vd > 6 V in thinner LDD spacer SiOz (15 nm) structure.
`This rcsult indicates that the Si3 N4/Si0Z interface state is also
`generated by higher energy hot—electron injection even in
`ONLDD. However,
`in a thicker LDD spacer oxide structure
`(25 am), no Id shift relaxation was observed in this study.
`Next, the relationship between the Id shift relaxation rate and
`the relaxation time is shown. Fig. 17 shows the relaxation rate
`value versus the relaxation time. This relaxation rate R(t) can
`be expressed as the following function, by fitting the data:
`
`R(t) : rl(l — exp
`
`(8)
`
`where r] is a constant and r is the time constant.
`The time constant 7 in NLDD is not afiected by dc stress
`conditions and is about 3600 s (1 h). The physical meaning for
`this 7' value is not so clear, but it is probably considered to bc
`a dctrapping rate for the Si3 N4 / Si02 interface state.
`
`C. Hot—Carrier Injection Mechanism
`According to Section III-A1,
`the drain current shift at the
`peak substrate current conditions is considered to be mainly
`caused by interface generation. This section discusses the hot-
`carrier mechanism in both NLDD and ONLDD, considering the
`interface generation rate by using the lucky electron model [12],
`in order to explain the 1,, shift versus the stress drain bias shown
`in Fig, 13.
`According to the discussion in the previous sections, there
`are two interface state generation regions in the ONLDD struc-
`ture, such as the Si3N4/SiO2 and the SiOz/Si interfaces, as
`shown in Fig. 5.
`Generally, interface state generation rate P can be given as
`follows [12]:
`
`
`(9)
`P = C11,, exp <— m + (15')
`q)» Emax
`where Cl is a constant, 1,, is the substrate current, he is the elec-
`tron mean free path in the Si (7.5 nm) [14], Emax is the maxi—
`mum lateral drain field, (15b and <15,- are the barrier height and the
`generation energy for the interface state, respectively. In (9),
`experimental 1,, is used and E"m is calculated by the 2D device
`simulator MOSZC [16].
`In the case of the ONLDD, the injected hot-carrier rate from
`the Si into the Si3N4/8102 is reduced by the LDD spacer oxide,
`obeying the function exp ( *Tox/AO), where M, is the electron
`mean free path in the SiO2 film. Therefore. according to (9),
`the Si3N4/Si01 interface state generation rate P" can be ex-
`pressed as follows:
`
`_
`
`P” — C21, exp <
`
`_E
`
`_ Sbe + 45m
`
`> exp ( ——qume>
`
`(10)
`
`where C2 is constant, d)“, (3.2 eV) [12] and do," are the barrier
`height of the 8102/81 and the generation energy of the 813N4
`interface state, respectively. The barrier height of the Si3 N4 to
`the Si is 2.05 eV113J.
`Since,
`in the case of NLDD, the threshold voltage does not
`shift at the dc stress test, shown in Fig. 4 and the LDD spacer
`oxide (natural oxide) thickness is almost the same as the elec—
`tron mean free path in SiO2 ( 1.5 nm) [15], it is considered that
`
`10°
`
`|
`Vq -?Vd STRESS
`’ — =Si3N4/Si02
`_2 ———=Si02/Si
`IO r———=H0T-H0LE
`
`
`
`
`
`GENERATIONRATE(A.U.)
`
` O
`
`
`
`I0-4_
`
`lo-SL ONLDD
`.
`(TOX |5nm)
`
`
`
`l
`I
`‘\ I
`\\(
`
`
`6
`8
`4
`2
`STRESS DRAIN VOLTAGE (V)
`
`Fig. 18. Arbitrary interface state generation rate for Si; NA / $10; and
`5102 / Si interfaces. Solid lines and dotted and dashed lines show the cal—
`culated results of the Si3 Nx/SiO2 and the SiOz/Si interfaces by hot-elec-
`tron injection, respectively. Dashed line shows the calculated resnlts of the
`Si3 N4 /Si02 interface by the hot»hole injection.
`
`almost all hot-electrons can be injected into the Si3N4/Si02
`interface by the tunneling mechanism. Therefore, the term exp
`(~Tnx/h0) in (10) is nearly equal to unity in NLDD. More-
`over, according to the data in Fig. 14, (pl-n in (10) is about the
`thermal energy at room temperature and can be expressed as
`follows:
`
`(11)
`
`¢.,=kT=~.0.03ev
`where k is the Boltzmann constant.
`On the other hand, the activation energy for SiOZ/ Si inter-
`face state ¢i0 is considered to be much larger than (1),", according
`to OLDD data in Fig. 14. Therefore, in this siudy, (12,0 in (9) is
`adopted as the SiH bond energy 0.3 eV reported by Hu et a1.
`[12]. As a result, the SiOz / Si interface state generation energy
`is ten times as large as that of the Si3N4/Si02. Moreover, C,
`in (9) is assumed to be equal to C2 in (10).
`Using (9) and (10), Fig. 18 shows the calculated Si3 N4/Si02
`interface state generation rate P" in both NLDD and ONLDD
`with lS—nm—thick LDD spacer oxide. P" in ONLDD is reduced
`to about five magnitudes smaller than that in NLDD. Moreover,
`P,l in ONLDD with 25—nm-thick LDD spacer oxide is also cal—
`culated by (10) and is about eight magnitudes smaller than
`NLDD data, determined by the term exp ( ~T0x/X0). So P" in
`ONLDD with a 25-nm—thick LDD spacer oxide is considered to
`
`

`

`590
`
`1F.F.F TRANSACTIONS ON ELECTRON DEVICES. VOL. 38. N0. 3. MARCH 1991
`
`be negligibly small. Therefore. this low generation rate for the
`SigNa/SiO2 interface state suppresses the 1,, shift in ONLDD at
`low stress drain bias, shown in Fig. 13, and the initial degra~
`dation parameter, shown in Fig. 9. However, Fig. 18 indicates
`that. even in ONLDD, the Si3N4/Si02 interface state can be
`generated with increasing stress drain bias. In addition, P,,
`in
`NLDD is almost the same as that in ONLDD at about 4 V higher
`stress bias. This can be well explained by the 1,, shift recovery
`difference between NLDD and ONLDD, that is, why the relax—
`ation rate for ONLDD is almost the same as that for NLDD at
`about 3.5 V lower stress drain bias, as shown in Fig. 16. Cone
`sequently, the LDD spacer oxide suppresses the hot—carrier in-
`jection into the SigN4/Si02 interface
`The dashed line in Fig. 18 shows the calculated SiOz/Si in-
`terface state generation rate P0 for ONLDD, using (9). Com-
`pared to P0 in ONLDD, it is found that P,, in NLDD is much
`larger and is almost the same as P0 in ONLDD at about 2 V
`higher stress bias, which can explain the difierence between the
`Id shift dependence on the stress drain voltage for NLDD and
`ONLDD, as shown in Fig. 13. This high interface state gen—
`eration rate in NLDD causes the large 1,, shift in low bias stress
`test and a large initial degradation parameter, compared to the
`ONLDD structure.
`
`On the other hand, the barrier height of the hole injection is
`only 1.95 eV in NLDD [13] and is almost equal to that of the
`electron injection. Here, substituting the hole mean free path
`(5.5 nm) [14] into (9), P,, by hot~hole injection can be calcu—
`lated and is shown by the dotted and dashed line in Fig. 18. P,l
`by the hot—hole injection is about one tenth as large as P,, by the
`hoteelectron injection, because of smaller mean free path of the
`hole, but is two magnitudes larger than the interface state gen-
`eration rate in ONLDD. This high hot—hole injection in NLDD
`is not physically understood in detail now, but it is considered
`that high h0t~hole injections affects the large initial degradation
`parameter shown in Fig. 9, the large 1,, shift in low bias stress
`test shown in Fig. 13, and the 1,, shift relaxation phenomena
`shown in Fig. 14.
`
`IV. CONCLUSION
`
`It is found that LDD spacer structure influences hot—carrier
`elfects. In the Si3 N4 LDD spacer structure (NLDD), large hot—
`electron and hole injection into the nitride LDD spacer cause
`the large 1,, shift at low stress drain bias and a large initial deg—
`radation parameter, compared to both ONLDD and OLDD, be—
`cause of the small banier height in the Si3N4 film. Moreover,
`after dc stress test, reduced 1,, recovers at room temperature,
`which is due to small activation energy for the Si3 N4/Si02 in—
`terface state. On the contrary, in the Si3 N4/SiOz LDD spacer
`structure (ONLDD), Si02 film with large barrier height sup-
`presses the hot—earrier injection. Therefore. a highly reliable
`ONLDD is realized, compared to both NLDD and the conven-
`tional LDD structure.
`in addition,
`these results can be ex—
`plained by the simple hot—carrier model, considered the lucky
`electron model.
`Consequently, in a high dielectric LDD spacer structure with
`a small energy bandgap,
`it is important to suppress the hot-
`carrier injection from the Si surface. Therefore, it is necessary
`to form the thick Si02 film with the large barrier height under
`the high dielectric LDD spacer structure (high dielectric insu-
`lator/8102 complex film LDD spacer structure), in order to re-
`alize a highly reliable LDD MOSFET.
`
`ACKNOWLEDGMENT
`
`The authors would like to thank Dr. S. Shinozaki for his con»
`tinuous support. Thanks are also due to S. Sugiura for his useful
`discussion.
`
`REFERENCES
`
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`Trans. Electron Devices. vol. ED-27, p. 1359, 1980.
`[2] F.-C. Hsu and K. Y. Chiu, “Eifccts of device processing on hot—
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`[4] F.—C. Hsu and H. R. Grinolds, “Structure—enhanced MOSFET
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`Lett.. vol. EDL—S. p. 71. 1984.
`[5] T. Mizuno. T. Kobori. Y. Saitoh. S. Sawada. and T. Tanaka,
`“High dielectric LDD spacer technology for high performance
`MOSFET using gate-fringing field effects,” in IEDM Tech. Dig.,
`p. 613, 1989.
`[6] P. J. Hanop and D. S. Campbell, Thin Solid Films, vol. 2. p.
`273. 1968.
`I
`and
`S. Sawada, Y. Saitoh,
`[7] T. Mi