Beyond the
`conventional
`transistor
`
`by H.-S. P. Wong
`
`This paper focuses on approaches to
`continuing CMOS scaling by introducing
`new device structures and new materials.
`Starting from an analysis of the sources of
`improvements in device performance, we
`present technology options for achieving these
`performance enhancements. These options
`include high-dielectric-constant (high-k) gate
`dielectric, metal gate electrode, double-gate
`FET, and strained-silicon FET. Nanotechnology
`is examined in the context of continuing the
`progress in electronic systems enabled by
`silicon microelectronics technology. The
`carbon nanotube field-effect transistor is
`examined as an example of the evaluation
`process required to identify suitable
`nanotechnologies for such purposes.
`
`1. Introduction
`The semiconductor industry has been so successful in
`providing continued system performance improvement
`year after year that the Semiconductor Industry
`Association (SIA) has been publishing roadmaps for
`semiconductor technology since 1992. These roadmaps
`represent a consensus outlook of industry trends, taking
`history as a guide. The recent roadmaps [1] incorporate
`participation from the global semiconductor industry,
`including the United States, Europe, Japan, Korea, and
`Taiwan. They basically affirm the desire of the industry to
`continue with Moore’s law [2], which is often stated as the
`doubling of transistor performance and quadrupling of the
`
`number of devices on a chip every three years. The
`phenomenal progress signified by Moore’s law has been
`achieved through scaling of the metal-oxide–semiconductor
`field-effect transistor (MOSFET) [3, 4] from larger
`physical dimensions to smaller physical dimensions,
`thereby gaining speed and density.
`Shrinking the conventional MOSFET beyond the
`50-nm-technology node requires innovations to circumvent
`barriers due to the fundamental physics that constrains the
`conventional MOSFET. The limits most often cited [4 –12]
`are 1) quantum-mechanical tunneling of carriers through
`the thin gate oxide; 2) quantum-mechanical tunneling of
`carriers from source to drain, and from drain to the body
`of the MOSFET; 3) control of the density and location of
`dopant atoms in the MOSFET channel and source/drain
`region to provide a high on-off current ratio; and 4) the
`finite subthreshold slope. These fundamental limits have
`led to pessimistic predictions of the imminent end of
`technological progress for the semiconductor industry [4].
`On the other hand, the push to scale the conventional
`MOSFET continues to show remarkable progress [13, 14].
`Instead of reiterating the considerations of device
`scaling limits here, we refer the reader to our previous
`analyses [8 –10] as well as analyses by others in the
`literature [4 –7, 11, 12]. We focus this paper instead on
`approaches to circumvent or surmount the barriers to
`device scaling. The organization of this paper is as follows.
`We first address opportunities for the silicon MOSFET,
`focusing primarily on approaches that depart from
`conventional scaling techniques (for example, doping
`profile control, thin silicon dioxide gate dielectrics, SOI).
`Topics covered include high-dielectric-constant (high-k)
`
`娀Copyright 2002 by International Business Machines Corporation. Copying in printed form for private use is permitted without payment of royalty provided that (1) each
`reproduction is done without alteration and (2) the Journal reference and IBM copyright notice are included on the first page. The title and abstract, but no other portions, of this
`paper may be copied or distributed royalty free without further permission by computer-based and other information-service systems. Permission to republish any other portion of
`this paper must be obtained from the Editor.
`
`133
`
`0018-8646/02/$5.00 © 2002 IBM
`
`IBM J. RES. & DEV. VOL. 46 NO. 2/3 MARCH/MAY 2002
`
`H.-S. P. WONG
`
`TSMC 1121
`
`

`

`Source of
`improvement
`
`Charge density
`
`Carrier transport
`
`1. Mobility (␮
`eff)
`2. Carrier velocity
`3. Ballistic transport
`
`Ensuring device
`scalability to a
`shorter channel
`length
`
`1. Generalized scale length (␭).
`2. Channel length (Lg)
`
`Table 1 Device performance improvement opportunities.
`
`Parameters affected
`
`Method
`
`1. S (inverse subthreshold slope)
`2. Qinv at a fixed off-current
`
`1. Double-gate FET.
`2. Lowered operating temperature.
`
`1. Strained silicon.
`2. High-mobility and -saturation-velocity materials (e.g., Ge,
`InGaAs, InP).
`3. Reduced mobility degradation factors (e.g., reduced transverse
`electric field, reduced Coulomb scattering due to dopants,
`reduced phonon scattering).
`4. Shorter channel length.
`5. Lowered operating temperature.
`
`1. Maintaining good electrostatic control of channel potential
`(e.g., double-gate FET, ground-plane FET, and ultrathin-body
`SOI) by controlling the device physical geometry and providing
`means to terminate drain electric fields.
`2. Sharp doping profiles, halo/pocket implants.
`3. High gate capacitance (thin gate dielectrics, metal gate
`electrode) to provide strong gate control of channel potential.
`
`Parasitic resistance
`
`1. Rext
`
`1. Extended/raised source/drain.
`2. Low-barrier Schottky contact.
`
`Parasitic capacitance
`
`1. Cjn
`2. CGD, CGS, CGB
`
`1. SOI.
`2. Double-gate FET.
`
`gate dielectric, metal gate electrode, double-gate FET,
`and strained-silicon FET. The second part of this paper
`examines the space between conventional microelectronics
`technology and the more exploratory nanotechnology.
`Such a wide spectrum of nanotechnologies are being
`explored today that it is impossible to make even a modest
`attempt to cover the field. The approach adopted in this
`paper is to select an example, the carbon nanotube field-
`effect transistor, to illustrate both the opportunities
`offered by nanotechnologies and the most important
`questions that must be answered before such technologies
`can find practical use. The example is therefore chosen for
`illustrative purposes rather than an implied suggestion of
`eventual technological utility.
`
`2. Silicon MOSFET
`For digital circuits, a figure of merit for MOSFETs for
`unloaded circuits is CV/I, where C is the gate capacitance,
`V is the voltage swing, and I is the current drive of the
`MOSFET. For loaded circuits, the current drive of the
`MOSFET is of paramount importance. Historical data
`indicate that scaling the MOSFET channel length
`improves circuit speed, as suggested by scaling theory [3].
`Reference [15] illustrates data on the CV/I metric from
`recent literature. The off-current specification for CMOS
`
`has been rising rapidly to keep the speed performance
`high. While 1 nA/␮m was the maximum off-current
`allowed in the late 1990s [8], off-currents in excess of
`100 nA/␮m are proposed today [13]. This trend obviously
`cannot continue, since the on-current increases only
`linearly as off-current increases exponentially in a
`typical device design tradeoff. Means to mitigate the
`standby power increase must be found.
`Keeping in mind both the CV/I metric and the benefits
`of a large current drive, we note that device performance
`may be improved by 1) inducing a larger charge density
`for a given gate voltage drive; 2) enhancing the carrier
`transport by improving the mobility, saturation velocity,
`or ballistic transport; 3) ensuring device scalability to
`achieve a shorter channel length; and 4) reducing parasitic
`capacitances and parasitic resistances. Table 1 summarizes
`these opportunities and proposed technology options for
`capitalizing on them. These options generally fall into two
`categories: new materials and new device structures. In
`many cases, the introduction of a new material requires
`the use of a new device structure, or vice versa.
`Throughout the discussion, we direct attention to areas
`of device physics and materials science that must be
`better understood in order to advance the technology.
`
`134
`
`H.-S. P. WONG
`
`IBM J. RES. & DEV. VOL. 46 NO. 2/3 MARCH/MAY 2002
`
`

`

`Poly-Si
`
`Poly-Si
`
`Si
`
`SiO2
`
`SiO2
`
`Al2O3
`
`Si
`
`2 nm
`
`Si
`
`2 nm
`
`(a)
`
`(b)
`
`1.5 nm
`
`3.8 nm
`ZrO2
`
`(c)
`
`C
`
`inv
`
`1.5 nm
`
`1 nm
`
`Figure 1
`
`(a) Transmission electron micrograph (TEM) of a conventional silicon dioxide (oxynitride) with a physical thickness of 1.5 nm. (b) TEM of
`a 2.2-nm Al2O3 with an equivalent electrical thickness of 1 nm. (c) TEM of a 3.8-nm ZrO2 on a 1.5-nm interfacial silicon dioxide. Adapted
`with permission from Gusev et al. [20]; © 2001 IEEE.
`
`MOSFET gate stack
`Continued device scaling requires the continued reduction
`of the gate dielectric thickness. This requirement arises
`from two different considerations: controlling the short-
`channel effect and achieving a high current drive by
`keeping the amount of charge induced in the channel
`large as the power-supply voltage decreases. In both cases,
`to a first approximation, it is the electrical thickness
`that is important. The electrical thickness at inversion
`is determined by the series combination of three
`capacitances in the gate stack: the depletion capacitance
`of the gate electrode, the capacitance of the gate
`dielectric, and the capacitance of the inversion layer
`in the silicon [Figure 1, part (a)].
`On the other hand, the direct tunneling current through
`the gate dielectric grows exponentially with decreasing
`physical thickness of the gate dielectric [16]. This
`tunneling current has a direct impact on the standby
`power of the chip and puts a lower limit on unabated
`reduction of the physical thickness of the gate dielectric.
`It is likely that tunneling currents arising from silicon
`dioxides (SiO2) thinner than 0.8 nm cannot be tolerated,
`even for high-performance systems [10].
`Solutions that reduce the gate tunneling current and
`gate capacitance degradation due to polysilicon depletion
`are explored through introduction of new materials: high-
`dielectric-constant gate dielectrics and metal gate electrodes.
`
`High-k gate dielectric
`A gate dielectric with a dielectric constant (k) substantially
`higher than that of SiO2 (kox) will achieve a smaller
`equivalent electrical thickness (teq) than the SiO2, even with
`a physical thickness (tphys) larger than that of the SiO2 (tox):
`
`⫽冉 kox
`
`k
`
`冊 tphys .
`
`teq
`
`Replacing the SiO2 with a material having a different
`dielectric constant is not as simple as it may seem. The
`material bulk and interface properties must be comparable
`to those of SiO2, which are remarkably good. Basic material
`properties such as thermodynamic stability with respect
`to silicon, stability under thermal conditions relevant to
`microelectronic fabrication, low diffusion coefficients, and
`thermal expansion match are some critical examples. In
`addition, interface traps of the order of a few 1010 cm⫺2eV⫺1
`and bulk traps of the order of a few 1010 cm⫺2 are
`common among SiO2 and the closely related oxynitrides
`[17, 18]. Charge trapping and reliability for the gate
`dielectrics are particularly important considerations.
`Thermal stability with respect to silicon is an important
`consideration, since high-temperature anneals are
`generally employed to activate dopants in the source/drain
`as well as the polysilicon gate. Although many binary and
`ternary oxides are predicted to be thermally stable with
`respect to silicon [19], recent research on high-dielectric-
`constant gate insulators have focused primarily on binary
`metal oxides such as Ta2O5, TiO2, ZrO2, HfO2, Y2O3,
`La2O3, Al2O3, and Gd2O3 and their silicates [20]. Table 2
`compares the properties of the common high-k gate
`dielectrics reported in the literature. The dielectric
`constant of these materials generally ranges from
`10 to 40, which is about a factor of 3 to 10 higher than
`SiO2. Leakage current reduction from 103⫻ to 106⫻, in
`comparison with SiO2 of the same electrical thickness,
`is generally achieved experimentally for high-k gate
`dielectrics [21]. The benefits of using a very-high-
`dielectric-constant material to simply replace SiO2 for
`
`IBM J. RES. & DEV. VOL. 46 NO. 2/3 MARCH/MAY 2002
`
`H.-S. P. WONG
`
`135
`
`

`

`potential barrier and lowers the threshold voltage in a way
`similar to the well-known drain-induced barrier lowering
`(DIBL), in which the drain field modulates the source-to-
`channel potential barrier via coupling through the silicon
`substrate. The use of higher-k materials must therefore be
`combined with a concurrent reduction of the electrical
`thickness.
`A large silicon-to-insulator energy barrier height is
`desirable because the gate direct-tunneling current is
`exponentially dependent on the (square root of the)
`barrier height [23]. In addition, hot-carrier emission into
`the gate insulator is also related to the same barrier
`height [24]. The high-k material should therefore not only
`have a large bandgap, but also have a band alignment
`which results in a large barrier height. Figure 2 illustrates
`the bandgap and band alignment for several high-k gate
`dielectrics calculated by Robertson [25]. Most high-k
`materials that have other desirable properties do have
`relatively low band offsets and small bandgaps. Aluminum
`oxide (Al2O3) is probably the only material that has a
`bandgap and band alignment similar to those of SiO2.
`Figure 1 illustrates examples of thin gate dielectrics:
`SiO2, Al2O3, and ZrO2 with an interfacial SiO2 layer.
`These dielectrics are only a few atoms thick. The thin
`dielectric films can be deposited by sputtering, sol– gel,
`physical vapor deposition (PVD), metallo-organic chemical
`vapor deposition (MOCVD), or atomic-layer deposition
`(ALD). Deposition uniformity does not appear to be a
`significant issue. However, integration of the deposited
`
`E
`g (eV)
`
`HfSiO4
`ZrSiO4
`
`SrTiO3
`
`ZrO2
`HfO2
`
`Y2O3
`La2O3
`
`Ta2O5
`
`Dielectric material
`
`Si3N4
`
`Al2O3
`
`SiO2
`
`Si
`
`4
`
`2
`
`0
`
`⫺2
`
`⫺4
`
`⫺6
`
`Energy band (eV)
`
`Figure 2
`Bandgap and band alignment of high-k gate dielectrics with re-
`spect to silicon. Data from Robertson [25], with permission. The
`dashed line represents 1 eV above/below the conduction/valence
`bands.
`
`the same electrical thickness are limited because of the
`presence of two-dimensional electric fringing fields from the
`drain through the physically thicker gate dielectric [10, 22].
`The drain fringing field lowers the source-to-channel
`
`Table 2 Selected material and electrical properties of high-k gate dielectrics. Data compiled from Robertson [25], Gusev et al. [20],
`Hubbard and Schlom [19], and other sources.
`
`Dielectric
`
`Dielectric
`constant (bulk)
`
`Bandgap
`(eV)
`
`Conduction
`band offset
`(eV)
`
`Silicon dioxide (SiO2)
`Silicon nitride (Si3N4)
`Aluminum oxide (Al2O3)
`Tantulum pentoxide (Ta2O5)
`
`Lanthanum oxide (La2O3)
`Gadolinium oxide (Gd2O3)
`Yttrium oxide (Y2O3)
`Hafnium oxide (HfO2)
`Zirconium oxide (ZrO2)
`Strontium titanate (SrTiO3)
`Zirconium silicate (ZrSiO4)
`Hafnium silicate (HfSiO4)
`
`3.9
`
`7
`⬃10
`
`25
`
`⬃21
`⬃12
`⬃15
`⬃20
`⬃23
`
`9
`
`5.3
`
`8.8
`
`4.4
`
`6*
`
`6
`
`6
`
`5.8
`
`3.3
`
`6*
`
`6*
`
`3.5
`
`2.4
`
`2.8
`
`0.36
`
`2.3
`
`2.3
`
`1.5
`
`1.4
`⫺0.1
`
`1.5
`
`1.5
`
`Leakage current
`reduction w.r.t.
`SiO2
`N/A
`
`102–103⫻
`
`Thermal stability w.r.t.
`silicon (MEIS data)
`
`⬎1050⬚C
`⬎1050⬚C
`⬃1000⬚C, RTA
`
`Not thermodynamically
`stable with silicon
`
`104–105⫻
`104–105⫻
`104–105⫻
`
`Silicate formation
`⬃950⬚C
`⬃900⬚C
`
`136
`
`*Estimated value.
`
`H.-S. P. WONG
`
`IBM J. RES. & DEV. VOL. 46 NO. 2/3 MARCH/MAY 2002
`
`

`

`0.8
`
`0.6
`
`0.4
`
`0.2
`
`0.0
`0.0
`
`103
`
`102
`
`Al2O3 ⫽ 1.5 nm
`t
`qm ⫽ 1.3 nm
`L
`eff ⫽ 80 nm
`
`
`
`VG ⫺ V
`t
`1 V
`
`0.8 V
`
`0.6 V
`
`0.4 V
`
`0.2 V
`
`0 V
`
`0.5
`
`1.0
`1.5
`Drain voltage, V
`DS (V)
`(a)
`
`2.0
`
`Universal (Takagi)
`Oxynitride control
`HfO2
`Al2O3
`
`DS (mA/ m)
`
`␮
`
`Drain current, I
`
`Effective electron mobility (cm2/Vs)
`
`
`
`Effective vertical field (V/cm)
`(b)
`
`106
`
`101
`
`105
`
`Figure 3
`
`Electrical characteristics of a polysilicon-gated Al2O3 n-FET. (a)
`Drain current vs. drain voltage characteristics of an 80-nm-channel-
`length n-FET. Reproduced with permission from Buchanan et al.
`[26]; © 2000 IEEE. (b) Effective electron mobility of long-channel
`FET compared with the universal mobility curve [60]. Two HfO2
`curves show the effect of surface preparation. The Al2O3 curves
`illustrate the range of mobility for Al2O3 gate stacks. Mobility
`approximately twice as high as that of [26] is achieved due to
`improved processing. Reproduced with permission from Gusev
`et al. [21]; © 2001 IEEE.
`
`(at inversion) is required for sub-50-nm CMOS. The
`thermal instability of most high-k gate dielectrics may
`require the use of a low thermal budget process after the
`gate dielectric deposition. While junction activation may
`be performed prior to gate dielectric deposition, the high-
`temperature gate polysilicon activation step necessarily
`occurs after the gate dielectric formation. A further
`potential benefit of metal gate electrodes is the
`elimination of carrier mobility degradation due to plasmon
`scattering from the gate electrode. The plasmon frequency
`
`137
`
`dielectric with the rest of the device fabrication process
`requires further research and development in several
`areas. If a conventional self-aligned polysilicon gate is
`used, the dielectric film must be able to withstand rapid
`thermal anneals (RTAs) up to at least 950⬚C for dopant
`activation in the polysilicon gate. The typical thermal
`treatments during a polysilicon gate CMOS process pose
`potential problems such as formation of silicates and
`interfacial SiO2. In addition, diffusion (for example,
`boron, oxygen) through the gate dielectric is a serious
`concern. If a metal gate electrode is employed (using a
`low-temperature process), many of the thermal stability
`concerns can be relieved.
`Figure 3(a) shows the electrical characteristics of an
`80-nm polysilicon gate n-FET using Al2O3 as the gate
`dielectric, as reported by Buchanan et al. [26]. This work
`and that of others (for example, [21]) illustrates some of
`the obstacles for high-k gate dielectrics: 1) There are a
`significant number of traps and fixed charges in the film
`(or at the interfaces), leading to flat-band voltage shifts
`(up to 450 mV) and voltage bias instability; 2) the traps
`raise questions of reliability as channel hot carriers and
`carriers from gate tunneling traverse the gate dielectric,
`resulting in trap generation; and 3) the mobility of carriers
`in the FET channel is severely degraded (up to a factor
`of 2) for high-k gate dielectrics [Figure 3(b)].
`The cause of the mobility degradation is not clear at
`present. Presumably, some of the differences can be
`attributed to the difficulty of obtaining accurate estimates
`of the effective electric field due to the charge trapping.
`Coulomb scattering due to the trapped charge alone
`cannot explain entirely the mobility degradation observed.
`Another source of mobility lowering may be found in
`remote phonon scattering [27]. The static dielectric
`constant of a high-bandgap high-k material derives its high
`dielectric constant primarily from ionic polarizability,
`since the large bandgap results in a small electronic
`polarizability. The ionic polarizability is associated with
`the “soft” metal– oxygen bonds with low-energy phonons.
`Fischetti et al. [27] studied the scattering of electrons
`in the inversion layer by surface optical phonons and
`suggested that there is generally an inverse relation
`between surface-optical-phonon-limited mobility and the
`static dielectric constant: the higher the dielectric constant,
`the lower the surface-optical-phonon-limited mobility.
`
`Metal gate electrode
`A metal gate electrode has several advantages compared
`to the doped polysilicon gate used almost exclusively
`today. Gate capacitance degradation due to the depletion
`of the doped polysilicon gate typically accounts for
`0.4 – 0.5 nm of the equivalent-oxide thickness of the total
`gate capacitance at inversion. This is a substantial amount,
`considering that a gate equivalent oxide of less than 1.5 nm
`
`IBM J. RES. & DEV. VOL. 46 NO. 2/3 MARCH/MAY 2002
`
`H.-S. P. WONG
`
`

`

`of a highly conductive metal electrode is too high to
`interact with the carriers in the inversion layer [28].
`From a device design point of view, the most important
`consideration for the gate electrode is the work function
`of the material. While the polysilicon gate technology has
`somewhat locked in the gate work functions to values
`close to the conduction band and the valence band of
`silicon,1 the use of a metal gate material opens up the
`opportunity to choose the work function of the gate and
`redesign the device to achieve the best combination of
`work function and channel doping. For bulk or partially
`depleted SOI, because of the requirements on the
`threshold voltages and the need to use heavy dopants
`to control short-channel effects, the most suitable gate
`work-function values are still close to the conduction and
`valence bands of silicon. A mid-gap work function results
`in either a threshold voltage that is too high for high-
`performance applications, or compromised short-channel
`effects, since the channel must be counterdoped to bring
`the threshold voltage down. For double-gate FETs (see
`the section on double-gate FET electrostatics), because
`the short-channel effects are controlled by the device
`geometry, the threshold voltage is determined mainly by
`the gate work function. Therefore, the choice of the gate
`electrode is particularly important for the double-gate
`FET. For example, for symmetric double-gate FETs
`(SDG), a gate-electrode work function ⫾250 mV from
`mid-gap is suitable. The section on double-gate FET
`electrostatics expands on this discussion.
`While there are plenty of metal choices that may satisfy
`the work-function requirements [30 –32], other device
`and integration considerations narrow down the
`choices significantly. The requirements of a low gate-
`dielectric/silicon interface state density and low gate-
`dielectric fixed charges imply that a damage-free metal
`deposition process (e.g., CVD instead of sputtering) is
`required. At the same time, the deposition process
`must not introduce impurities (e.g., traces of the CVD
`precursor materials) into the gate stack. The thermal
`stability of the metal electrode must at least withstand the
`thermal anneals required to passivate the silicon/gate-
`dielectric interface (e.g., forming-gas anneal) after the
`metal deposition, as well as the thermal processing of
`the back-end metallization processes. Furthermore, it is
`desirable to have a low resistivity (at least similar to
`conventional silicides such as CoSi2 and TiSi2), although
`this requirement may be relaxed by strapping the gate
`electrode of the proper work function with a lower-
`resistivity material on top.
`In principle, a single-metal electrode is advantageous,
`since it avoids many potential problems of alloyed metals
`
`138
`
`1 The use of polySiGe gates can tailor the work function near the valence band
`somewhat, using the dependence of bandgap on the Ge fraction [29].
`
`such as composition uniformity control and phase
`separation. On the other hand, alloying provides flexibility
`in choosing the desired material properties. The gate-
`electrode work-function issue is further complicated by the
`fact that the work function measured in vacuum (values
`reported in most materials data books) is different from
`the work-function value when the metal is in contact
`with a dielectric. In general, a dipole forms at the
`metal/dielectric interface which alters the effective work
`function of the metal/dielectric combination [33, 34].
`The choice of appropriate metal electrode is then also
`dependent upon the choice of the gate dielectric: SiO2
`or high-k material.
`One of the promising process integration schemes for
`metal gate is the replacement-gate technology [35]. In this
`process, a dummy gate material (e.g., polysilicon) is used
`for forming the self-aligned gate-to-source/drain structure.
`Subsequently, the dummy gate material is removed and
`replaced with the desired gate dielectric and electrode
`[35]. Alternatively, the metal gate electrode may be etched
`in a way similar to the polysilicon gate technology.
`However, the learning curve is long and steep for
`developing the same (or a better) level of etch selectivity
`and profile control for the metal gate compared to the
`polysilicon gate. In addition, thermal stability issues
`(from the source/drain dopant activation anneal) must be
`addressed. In either case, if metals with two different
`work functions are employed for n-FET and p-FET,
`respectively, the integration of n-FET and p-FET
`in a CMOS process remains a challenge, since 1) the
`deposition of the metals for n-FET and p-FET must be
`done separately, and 2) one must find a way to strap the
`two different metals in a compact way to connect the
`n-FET and p-FET gates. It is desirable to circumvent
`these two requirements and find a way to alter the work
`function of the metal by some simple means (for example,
`one that requires only a block mask). Two interesting
`approaches, yet to be proven through more rigorous
`examination, have been reported. In the first approach, a
`single metal (molybdenum) is deposited, and the work
`function is altered using ion implantation of nitrogen into
`the metal [36]. It is not clear how the nitrogen influences
`the work function, and how thermally stable this material
`is. On the other hand, ion implantation is an attractive
`process, since it requires only a single metal deposition
`and a photoresist block mask. In another approach, metals
`are intermixed to obtain the desired work function [37].
`Two metals (Ti and Ni) are sequentially deposited on the
`gate dielectric, followed by selective etching of the top
`metal, leaving the bottom metal at desired locations. After
`thermal annealing, the metal on the top migrates to the
`metal/gate-dielectric interface and alters the work function
`locally.
`
`H.-S. P. WONG
`
`IBM J. RES. & DEV. VOL. 46 NO. 2/3 MARCH/MAY 2002
`
`

`

`V
`S
`
`V
`G
`
`Source
`
`t
`Si
`Top gate
`L
`g
`
`Bottom gate
`
`V
`D
`
`t
`eq
`
`V
`S
`
`V
`D
`
`t
`eqt
`
`V
`G
`
`t
`Si
`Top gate
`
`Drain
`
`Source
`
`L
`g
`
`Bottom gate
`
`V
`GB
`
`Drain
`
`t
`eqb
`
`V
`G
`
`V
`S
`
`V
`G
`
`V
`D
`
`t
`eq
`
`t
`Si
`
`Source
`
`Top gate
`L
`g
`
`Drain
`
`Buried oxide
`
` t
`box
`
`⫽ 200 nm
`
`Si substrate
`
`V
`G
`
`V
`G
`
`V
`G
`
`V
`G
`
`V
`G
`
`V
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`
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`GB
`
`Symmetric
`double-gate (SDG)
`
`Asymmetric
`double-gate (ADG)
`
`(a)
`
`Back gate (BG)
`Ground plane (GP)
`(b)
`
`Single-gate SOI
`
`(c)
`
`Figure 4
`
`Conceptual device schematics of (a) double-gate, (b) ground-plane (or back-gate FET, BG), and (c) single-gate SOI MOSFET. On-chip
`biasing of the ground plane is assumed The upper figures are cross-section schematics of the devices; the lower figures illustrate their
`respective band diagrams. The gate work functions of the top and bottom gates can be the same (symmetric DG FET, or SDG) or different
`(asymmetric DG FET, or ADG). Adapted with permission from Wong et al. [50]; © 1998 IEEE.
`
`Ultimately scalable FET—the double-gate FET
`
`Device concepts
`The double-gate FET (DG FET) shown in Figure 4,
`part (a) was proposed in the early 1980s [38]. The concept
`has been gradually explored both experimentally and
`theoretically by many groups [39 – 46]. The Monte Carlo
`and drift-diffusion modeling work by Fiegna et al. [41] and
`Frank et al. [42] clearly showed that a DG FET can be
`scaled to a very short channel length (25 to 30 nm) while
`achieving the expected performance derived from scaling.
`While the early work focused on the better scalability
`of DG FET, recent work suggests that the scalability
`advantage may not be as large as previously envisioned
`[10, 47], although the carrier transport benefits may be
`substantial. In this section, we first discuss the advantages
`of DG FET, followed by device design requirements, and
`conclude with a summary of latest hardware results.
`The salient features of the DG FET (Figure 4) are [48]
`1) control of short-channel effects by device geometry, as
`compared to bulk FET, where the short-channel effects
`are controlled by doping (channel doping and/or halo
`doping); and 2) a thin silicon channel leading to tight
`coupling of the gate potential with the channel potential.
`These features provide potential DG FET advantages that
`include 1) reduced 2D short-channel effects leading to a
`
`shorter allowable channel length compared to bulk FET;
`2) a sharper subthreshold slope (60 mV/dec compared to
`⬎80 mV/dec for bulk FET) which allows for a larger gate
`overdrive for the same power supply and the same off-
`current; and 3) better carrier transport as the channel
`doping is reduced (in principle, the channel can be
`undoped). Reduction of channel doping also relieves a key
`scaling limitation due to the drain-to-body band-to-band
`tunneling leakage current. A further potential advantage is
`more current drive (or gate capacitance) per device area;
`however, this density improvement depends critically on
`the specific fabrication methods employed and is not
`intrinsic to the device structure.
`The most common mode of operation of the DG FET is
`to switch the two gates simultaneously. Another use of the
`two gates is to switch only one gate and apply a bias to
`the second gate to dynamically alter the threshold voltage
`of the FET2 [49, 50]. In this mode of operation, called
`“ground plane” (GP) or back-gate (BG), the subthreshold
`slope is determined by the ratio of the switching gate
`capacitance and the series combination of the channel
`capacitance and the nonswitching gate capacitance, and is
`generally worse than the DG FET. A thin gate dielectric
`at the nonswitching gate reduces the voltage required to
`
`2 One should note that the threshold voltage adjustment is primarily effective in
`the reverse-bias condition (raising the threshold voltage) where the back-gated
`channel remains in depletion and not inverted.
`
`139
`
`IBM J. RES. & DEV. VOL. 46 NO. 2/3 MARCH/MAY 2002
`
`H.-S. P. WONG
`
`

`

`the trend of these 2D effects as the channel length
`is decreased with respect to the scale length of the
`MOSFET. Manufacturing tolerances put a premium on
`the minimum channel length. With typical tolerances of
`20 –30% gate-length variation, an L/␭ of 1.5 is required.3
`Conventional short-channel-effect theory [23] correlates
`the junction depth to the short-channel effects. In the case
`of the DG FET, consideration of junction depth is moot,
`since the 2D electrostatic behavior is controlled by the
`thickness of the silicon channel instead of the junction
`depth. However, the steepness of the source/drain junction
`is still an important consideration, as in the case of bulk
`FETs [47]. Figure 5 illustrates the threshold-voltage roll-
`off characteristics of the DG FET with lateral junction
`profile gradients of 2, 4, and 6 nm (Gaussian analytical
`profile). It is clear that a steep junction gradient
`commensurate with the channel length is required.
`Comparing scale lengths for the DG FET, ultrathin
`silicon SOI FET, and bulk devices, as well as considering
`other leakage mechanisms (such as tunneling leakages),
`leads to the conclusion that the DG FET can be scaled up
`to 50% further than the bulk FET for some applications
`[10]. Illustrations of the threshold-voltage roll-off behavior
`(an example of 2D short-channel effects) comparing DG
`FET, ultrathin-silicon FET, and ground-plane FET (in
`which the bottom gate of a DG FET is tied to a fixed bias)
`can be found in [10, 50] and many other references in the
`literature and are not repeated here. Similar analyses
`based on on-current and off-state subthreshold leakage
`current can be found in [53, 54]. Simply put, the better
`scalability of DG FET can be used to achieve a shorter
`channel length using the same gate-oxide thickness, or
`the same channel length using a thicker gate oxide.
`We now turn our discussion to the relationship of
`the channel inversion charge and the gate voltage. The
`analytical model of Taur [55] and the numerical modeling
`of Ieong et al.4 [56] form the basis for much of this
`discussion. The gate work function of the two gates can
`be the same (the SDG, with a symmetric energy-band
`diagram in the direction normal to the gate electrode)
`or different (the ADG, with an asymmetric energy-band
`diagram in the direction normal to the gate electrode), as
`illustrated in Figure 4. In the subthreshold region, where
`there is negligible inversion charge, the silicon channel is
`fully depleted, and the energy bands closely follow the
`gate bias in a one-to-one relationship. For the SDG, the
`bands remain flat throughout the subthreshold region,
`since there is little or no depletion charge. Once inversion
`charge begins to build up, the mobile charges screen the
`
`3 As discussed by Frank et al. [10], the “end of scaling” depends on the application
`at hand, which determines the amount of deleterious 2D short-channel effects
`one can tolerate. The above L/␭ ⯝ 1.5 rule should be considered only a rough
`guideline.
`4 M. Ieong and H.-S. P. Wong, “Analysis of 25 nm Double-Gate MOSFETs
`Including Self-Consistent 2-D Quantization Effects,” unpublished work, 1999.
`
` N
`a ⫽ 1 ⫻ 1014 cm⫺3,
` x ⫽ 2 nm
`a ⫽ 1 ⫻ 1014 cm⫺3,
` x ⫽ 4 nm
`a ⫽ 1 ⫻ 1014 cm⫺3,
` x ⫽ 8 nm
`␴
`
`
`
`
`
`␴ N
`
`␴ N
`
`Double-gate
`eq ⫽ 1.5 nm, t
`t
`
`Si ⫽ 10 nm
`
`10
`
`Gate length, L
`
`g (nm)
`
`100
`
`0
`
`⫺50
`
`t (mV)
`
`⌬V
`
`⫺100
`
`⫺150
`
`⫺200
`
`Figure 5
`
`Threshold voltage roll-off cha