IEEE ELECTRON DEVICE LETTERS, VOL. EDL-S, NO. 10, OCTOBER 1984
`
`389
`
`Reduced Hot-Electron Effectsin MOSFET’s
`
`with an Optimized LDD Structure
`
`D. A. BAGLEE, MEMBER, IEEE, AND C. DUVVURY, MEMBER, IEEE
`
`Abstract—A comparison of device degradation due to hot-electron
`injection is made for conventional MOSFET’s and lightly doped drain
`(LDD) structures. The studies indicate that, for an optimized LDD
`structure, critical device parameters, such as threshold voltage, trans-
`conductance, and linear and saturated current drives, show signifi-
`cantly reduced degradation when subjected to accelerated life testing.
`These results imply long-term stability for LDD devices used in VLSI
`circuits.
`
`1. INTRODUCTION
`
`NCREASED scaling of feature sizes in VLSI circuits is intro-
`ducing new concerns about long-term circuit reliability and
`the degradation of transistor characteristics due to hot-electron
`injection has been given much attention in recent years.
`Many process modifications have been suggested to either
`reduce the peak electric field in the drain region or to move the
`region of peak electric field away, from underneath the gate
`electrode. Such devices are generally known as having lightly
`doped drains (LDD’s). Intuitively, one would expect transistors
`having an LDD structure to be less susceptible to hot-electron
`injection,
`thereby, offering improved long-term reliability.
`However,
`little data has been published on the stability of
`these devices, and it was recently reported that certain LDD
`structures may actually degrade at a faster rate than conven-
`tional MOSFET’S [1] .
`In this letter, We report the results obtained on our opti-
`mized LDD structure which show reduced hot-electron trap-
`ping effects. When these results are compared to those ob-
`tained from a conventional device of similar channel length,
`we find that
`the optimized LDD structure offers much im-
`proved long-term stability for reliable circuit applications.
`
`II. DEVICE FABRICATION
`
`Both the conventional and LDD devices were fabricated in
`identical manners except for the inclusion of a “reach through
`implant” and a 450-nm spacer oxide in the case of the latter.
`This LDD structure, the details of which we reported in an
`earlier paper ['2] , has a gate oxide of 40 nm and an upper elec-
`trode consisting of a polysilicon/silicide stack. For the LDD
`device.
`the sheet-charge concentration for the n-region was
`typically 1E13—1E14 cm‘.2. In both structures a protective
`overcoat of LPCVD oxide was employed. The use of the oxide
`avoids instabilities introduced by hydrogen trapped in LPCVD
`nitride films.
`
`Manuscript received June 13. 1984; revised July 18, 1984.
`The authors are with Advanced Development, Texas Instruments, Inc.,
`Houston, TX.
`
`The effective channel lengths of both devices were deter-
`mined by using an array of transistors varying in channel
`lengths and with a width of 25 pm. By plotting 1/6 (gain)
`versus L design, we were able to extract the electrical length
`reduction for both LDD and conventional transistors. The data
`in this letter is for devices of similar L effective and notL de-
`
`sign. A previous paper [2] has described a method for deter-
`mining the effective series resistance of the n-regions in the
`LDD devices. The threshold voltage values in this study were
`obtained by solving the linear drain current equation for VT,
`ti, and 6, where Bis the device gain and 6 is the mobility degra-
`dation.
`
`III. RESULTS AND DISCUSSIONS
`
`The maximum injection of hot carriers into the gate oxide
`occurs when the substrate current is at a maximum. This max—
`
`imum occurs with approximately 3 V applied to the gate. For
`drain voltages (25 V), the peak is quite broad and relatively in-
`sensitive to small changes in Vg. Due to the nature of its struc-
`ture for any given drain voltage, the maximum substrate current
`is always less for an LDD device compared with a conventional
`transistor [2], [4]. In order to eliminate the effect of differing
`substrate currents, both types of transistors were stressed at
`the same substrate-current level. This required an applied drain
`stress voltage of 7 V for the conventional device and 8 V for
`the LDD device. In reality this means that stressing of the LDD
`transistor is much more severe than in circuit operation.
`We show the measured transconductance (gm) degradation
`of conventional and LDD devices in Fig. I, both before and
`after stress. The gm degradation for the conventional device is
`significantly larger at
`low gate voltages. This primarily indi-
`cates mobility degradation due to the generated interface
`charges at the drain junction and the associated surface scatter-
`ing [3]. The LDD device, due to the graded drain structure,
`has very little gm degradation, even at higher gate voltages.
`Therefore, the sharp series resistance increase, as attributed to
`the localized interface charge generation by Hsu and Grinolds
`[1] , is not observed here. Analysis of the I—V data on this de-
`vice showed that the total series resistance in the linear region
`was approximately constant at 1200 SZ-um before and after
`stress. In other experiments, some LDD devices did exhibit a
`slight
`increase (5—10 percent) in the total series resistance
`after stress but this was not enough to cause significant degra-
`dation. Additionally,
`for
`the conventional device there is a
`slight parallel shift of the gm curve with stress, indicating a
`shift in threshold voltage due to trapped charges. This was con-
`firmed by VT measurements. The conventional device also
`
`0741-3106/84/1coo-0389501.00 ©1984IEEE
`
`TSMC 1117
`
`TSMC 1117
`
`

`

`390
`
`IEEE ELECTRON DEVICE LETTERS. VOL. EDL-S, NO. 10, OCTOBER 1984
`
`
` CONVENTIONAL
`
`
`
`INITIAL
`
`— "' — — AFTER STRESS
`
`
`1
`2
`
`
`
`Vgs (VOLTS)
`Fig. 1. Transconductance degradation for conventional and LDD devices
`(measured at VDS = 100 mV) after stressing at peak substrate current for
`20 h.
`
`
`
` CONVENTIONAL DEVICE
`——— — LDD DEVICE
`
`
`
`
`—20 r
`-
`101
`
`r
`102
`
`t
`103
`
`l
`104
`
`I
`105
`
`106
`
`——>
`STRESS TIME
`ISECONDSI
`
`——>/.VTlmv]
`
`Fig. 2. Threshold Voltage shift as a function of stress time for conven-
`tional and LDD devices.
`
`displayed a shift in the subthreshold drain-current curve after
`stress.
`
`Measured linear region threshold voltages at VDS = 0.1 V
`are shown for both devices as a function of stress time in Fig.
`2. The dramatic increase in VT of the conventional device is
`due to the injection of hot electrons into the gate oxide,
`whereas for the graded drain device this effect is significantly
`less. Note, however, that this VT definition does not include
`the mobility degradation. Even when the mobility and series
`resistanCe degradations are included by defining a pseudo-
`threshold voltage as the gate voltage required for a drain cur-
`rent of 5 nA/um at a drain voltage of 0.1 V, the LDD device
`showed relatively less degradation.
`This differencs in behavior between LDD and conventional
`
`devices is evidenced by the current drive versus stress time
`
`plotted for both linear and saturation regions in Fig. 3.1 In the
`linear region the drain current degrades considerably more for
`the conventional device than for the LDD device. This is not
`unexpected since the linear VT for a conventional transistor
`degrades (cf. Fig. 2) in addition to the reduced mobility (cf.
`Fig. 1). The linear current drives in Fig. 3 were measured at
`VGS = 4 V, in order to represent more realistically the device
`in circuit operation. Note, however, that an abrupt degrada-
`tion of the conventional device linear current
`in the first
`10 s of stress is an anamolous effect that is not understood
`at
`this time. We have observed this phenomenon on conven-
`
`‘ Some spread in the data is seen for Conventional transistors, even when
`fabricated on the same wafer. Degradation has been seen to vary by up to a
`factor of 5. Figs. 2 and 3 are representative results.
`
`

`

`BAGLEE AND DUVVURY: REDUCED HOT-ELECTRON EFFECTS IN MOSFET’S
`
`391
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`STRESS TIME
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`
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`
`Fig. 3. Linear and saturation current drive as a function of stress time for
`conventional and LDD devices.
`
`tional devices, stressed at high gate voltages, but never on LDD
`transistors.
`
`The saturation region current drives for the LDD device does
`degrade slightly more than for
`the conventional
`transistor.
`This is due to the slight degradation in VT and mobility. In
`fact, it
`is noted from the two dashed lines in Fig. 3 that the
`linear and saturation current drives of the LDD device track
`
`with each other. On the other hand, for the conventional de—
`vice the saturation current does not degrade similar
`to its
`linear current drive. Since it was observed that the mobility
`and VT degrade for these conventional devices,
`this higher
`saturation current level can be attributed to increased drain ef-
`fect with stress. Measured I—V cur Yes for the conventional de-
`
`vice after stress do indicate an increased punchthrough behavior.
`In the LDD devices, due to the inserted n-region, the drain
`depletion region cannot significantly extend towards the source
`with the application of drain voltage to act as a Second back
`bias and hence has a much smaller drain effect, which does not
`alter much with stress. In fact, this is an attractive feature of
`the LDD device which can be utilized by proper design ofthe ‘
`n-region doping concentration and length [4-] to make it punch-
`through limited in breakdown. The details of our Optimization
`procedure are to be described elsewhere [5] .
`
`IV. CONCLUSIONS
`
`A comparison has been made to study the hot-electron ef-
`fects between conventional and optimized LDD structures.
`Our studies demonstrated that when these devices were stressed
`
`at bias conditions for peak substrate current the optimized
`LDD structure exhibited significantly reduced degradation due
`to hot electrons than the conventional device. We attribute the
`
`superior performance to an optimized LDD fabrication process
`which allows hot-electron trapping in the gate oxide to have a
`minimal effect on the long-term performance of short-channel
`transistors, even under more severe stress conditions.
`
`ACKNOWLEDGMENT
`
`The authors would like to thank R. N. Parker for much of
`
`the data taking, and M. Maekawa for providing samples. The
`authors
`also acknowledge valuable discussions with M. P.
`Duane and M. C. Smayling.
`
`REFERENCES
`[l] F.-C. Hsu and H. R. Grinolds.
`“Structure—enhanced MOSFET
`degradation due to hot-electron injection,” IEEE Electron Device
`Lett.. vol. EDL~5, Mar. 1984.
`[2] C. Duvvury, D. Baglee, M. Duane, A. Hyslop, M. Smayling, and M.
`Maekawa,
`“An analytical method for
`determining
`intrinsic
`drain/source resistance of lightly doped drain (LDD) devices,” Solid
`State Electron, vol. 27, no. 1, pp. 89—96, 1984.
`[3] F.-C. Hsu and S. Tam, “Relationship between MOSFET degradation
`and hot-electron induced interface-state generation, ' ’ IEEE Electron
`Device Lett., vol. EDL-S, Feb. 1984.
`S. Ogura, P. I. Tsang, W. W. Walker, D. L. Critchlow, and I. F.
`Shepard,
`“Design and
`characteristics of
`the
`lightly
`doped
`drain—source (LDD) insulated gate field effect transistor,” Trans.
`Electron Devices, vol. ED-27, Aug. 1980.
`I
`[5] D. A. Baglee, C. Duvvury, M. P. Duane, M. C. Smayling, “Lightly
`doped drain transistor for advanced VLSI circuits, " Trans. Electron
`Devices, to be published.
`
`[4]
`
`
`
`