Semiconductor Silicon Crystal Technology
`
`TSMC 1115
`
`TSMC 1115
`
`1
`
`

`

`Leave the beaten track occasionally
`and dive into the woods. Km will be
`certain to find something that you
`have never seen before.
`Alekander Graham Bell
`
`2
`
`

`

`,/Semiconductor
`Silicon Crystal
`Technology
`
`Fumio VII/Sghimura
`Department of Materials Science and Engineering
`North Carolina State University
`Raleigh, North Carolina
`
`Academic Press, Inc.
`Harcourt Brace Jovanovich, Publishers
`
`San Diego New York Berkeley Boston ‘
`London
`Sydney Tokyo Toronto
`
`3
`
`3
`
`

`

`COPYRIGHT © 1989 BY ACADEMIC PRESS, INC.
`ALL RIGHTS RESERVED.
`
`NO PART OF THIS PUBLICATION MAY BE REPRODUCED OR
`
`TRANSMITTED IN ANY FORM OR BY ANY MEANS, ELECTRONIC
`
`OR MECHANICAL, INCLUDING PHOTOCOPY, RECORDING, OR
`ANY INFORMATION STORAGE AND RETRIEVAL SYSTEM, WITHOUT
`PERMISSION IN WRITING FROM THE PUBLISHER.
`
`ACADEMIC PRESS, INC.
`San Diego, Caliifornia 92101
`
`<1
`
`'i‘
`
`'
`
`é.
`
`United Kingdom Edition published by ‘
`ACADEMIC PRESS LIMITED
`
`24—28 Oval Road, London NW1 7DX
`
`Library of Congress Cataloging-in-Publication Data
`
`Shimura, Fumio.
`
`Semiconductor silicon crystal technology.
`
`Includes bibliographical references and index.
`
`1. Semiconductors.
`TK7871.85.SS23
`1988
`
`2. Silicon crystals.
`621.3815’2
`
`1. Title.
`88-6279
`
`ISBN 0—12-640045-8
`
`(alk. paper)
`
`PRINTED IN THE UNITED STATES OF AMERICA
`88899091
`
`987654321
`
`4
`
`

`

`Contents
`
`Preface
`
`1. Introduction
`
`-
`
`_
`
`2. Atomic Structure and Chemical Bonds
`
`2.1 Atomic Structure
`2.2 Chemical Bond
`References
`
`3. Basic Crystallography
`3.1 Solid—State Structure
`3.2 X-Ray and Electron Diffraction
`3.3 Properties of Silicon Crystal
`3.4 Crystal Defects
`I
`References
`
`'
`
`4. Basic Semiconductor Physics
`
`4.1 Semiconductors
`4.2 Electrical Conductivity
`4.3 Electronic Device Physics
`4.4 Transistors
`References
`
`5. Silicon Crystal Growth and Wafer Preparation
`5.1 Starting Materials
`5.2 Single Crystal Growth
`5.3 Impurities
`.
`5.4 New Crystal Growth Methods
`5.5-Wafer Shaping Process and Wafer Properties
`5.6 Silicon Epitaxy
`References
`
`vii
`
`1
`
`8
`
`8
`17
`21
`
`22
`22
`33
`46
`54
`78
`
`82.
`
`82
`84
`98
`104
`1 13
`
`114
`115
`121
`146
`171
`183‘
`197
`206
`
`5
`
`

`

`vi
`
`Contents
`
`6. Crystal Characterization
`
`6.1 Electrical Characterization
`6.2 Chemical Characterization
`6.3 Physical Characterization
`
`References
`
`7. Grown-In and Process-Induced Defects
`
`_
`
`7.1 Grown—In Defects
`7.2 Process-Induced Defects
`
`'
`
`7.3 Effects of Defects on Electrical Properties
`7.4 Gettering
`References
`
`8. SilicOn Wafer Criteria for VLSI/ULSI Technology
`8.1 High-Technology Silicon Wafer Concept
`8.2 VLSI/ULSI Wafer Characteristics
`
`8.3 Concluding Remarks
`References
`
`Appendixes
`
`Index
`
`,
`
`-
`
`215
`
`216
`226
`243
`
`27 1
`
`279
`
`281
`285
`
`341
`344
`367
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`378
`378
`380
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`388
`390
`
`395
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`407
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`6
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`

`

`4.3 Electronic Device Physics
`
`103
`
`
`
`(b).
`
`Fig. 4.18. Effect of an external forward bias potential on a p—n junction: (a) behavior of carriers
`and (b) energy—band structure.
`
`
`g”
`electron
`space charge
`layer
`
`
`
`
`“Ole
`
`Fig. 4.19. Effect of an external reverse bias potential on a p-n junction: (a) behavior of carriers\
`and (b) energy band structure.
`
`(b)
`
`7
`
`

`

`104
`
`4 Basic Semiconductor Physics
`
`4.4 Transistors
`
`The term transistor17 is from “transfer resistor,” and transistors are unques—
`tionably the most important semiconductor devices. The transistors dis-
`cussed in this section include two types: (1) bipolar or carrier injection
`transistors, and (2) unipolar or field-efi'éct transistors. First the structure of
`bipolar transistors is briefly discussed. In a bipolar transistor, the internal
`currents are obtained by both majority and minority carriers, hence the name
`bipolar transistors. Then field—effect transistors, which have become more
`and more important in the VLSI/ULSI technology, are discussed.
`
`4.4.1. Bipolar Transistor
`
`A bipolar transistor consists of a three-zone structurewemitter E, collector C,
`and base Bmwith two parallel p-n junctions very near each other built in the
`same semiconductor crystal. Two distinct types of the three—zone structure
`are possible: a p-n—p transistor (Fig. 4.20) and an n—p—n transistor (Fig. 4.21).,
`In these figures, the basic conceptional structure (a), the cross section of a
`practical silicon planar bipolar transistor (b), and the circuit symbol (c) are
`shown. The operational principles of the two types are identical except for the
`
`Collector
`
`————O (C)
`
` E
`
`(c)
`
`Fig. 4.20. Structure of p—n~p transistor: (a) basic conceptional structure, (b), cross section of a
`silicon planar transistor, and (c) circuit symbol.
`
`8
`
`

`

`4L4 Tram‘iStors
`
`105
`
`
`
`Fig._ 4.21. Structure of n—p—n transistor: (a) basic conceptional structure, (b) cross section of a
`silicon planar transistor, and (c) circuit symbol.
`
`interchange of minority and majority carrier types, and the polarity of the
`applied bias voltages.
`The majority of discrete transistors made today are of the silicon planar
`type, as shown in Figs. 4.20b and 4.21b. A p—n—p planar silicon transistor
`shown in Fig. 4.20b. for example, is made by diffusing donor impurities such
`as phosphorus into a p-type Si substrate through an open window of an SiO2
`mask on the substrate, that is, base diffusion. Then acceptor impurities such
`as boron are difi‘used through a small window of a second mask for forming
`the emitter. region. Note that the thicknesses of the emitter (Xe), collector
`(XC), and substrate (Xs) as illustrated in Figs. 4.20b and 4.21b do not
`represent their realistic proportions with each other. That is, X e and X C are
`practically on the order of a few micrometers while X S is several hundreds of
`micrometers or even .closer to a millimeter in the case of a recent large—
`
`diameter Si substrate as described in Chapter 5. State—of-the—art bipolar ICs
`are commonly fabricated by planar epitaxial technology.18 The fundamental
`advantage of epitaxial substrates over bulk wafers, is that the structures such
`as high—resistivity layer/low-resistivity wafer and thin layer/wafer with oppo—
`site doping types are easily formed by epitaxial growth. Figure 4.22 shows a.
`schematic cross section of an n—p-n bipolar planar transistor built on an
`
`9
`
`9
`
`

`

`106
`
`'
`
`4 Basic Semiconductor Physics
`
`n+
`
`p-type Si
`
`n + buried layer
`
`n-type Si
`} epitaxial layer
`
`Fig. 4.22. Cross section of an n~p~n bipolar planar transistor built on an epitaxial substrate.
`
`epitaxial Si substrate. The heavily doped n+ buried layer functions as a
`subcollector, which reduces the series resistance of the devices and serves for
`alignment in subsequent wafer processing.
`
`4.4.2 Physics of MOS
`
`MOS Structure The metal oxide semiconductor
`field—effect
`transistor
`(MOSFET) has been realized as the most important device for VLSI/ULSI
`circuits such as memories and microprocessors because of its low fabrication
`cost, small size, and low power consumption. Figure 4.23 shows the structure
`of MOS or MIS (metal insulator semiconductor) and an MOS capacitor,
`which consists of a parallel—plate capacitor with one metallic plate, called the
`gate, and the other ohmic electrode.
`'
`
`C—V Characteristics The cross sections of an MOS capacitor fabricated on
`p—type Si are schematically shown with corresponding circuit symbols in Fig.
`4.24. When the gate bias voltage VG < 0 (Fig.4.24a), the MOS capacitor has
`the static capacitance CO per unit area, which is given by
`
`CO : KOXSO/tox
`
`Metal
`
`Oxide (Insulator)
`
`‘
`
`Gate
`
`
`WWI/A VII/III/IIJ/A
`
`
` Semiconductor
`Semiconductor.
`
` Ohmic contact
`(a)
`(b)
`
`Fig. 4.23. Cross-sectional structure: (a) MOS and (b) MOS capacitor.
`
`10
`
`10
`
`

`

`4 .4 Transistors
`
`107
`
`
`
`(a)
`
`(b)
`
`Fig. 4.24. Capacitance in an MOS capacitor fabricated on p—type silicon: (a) VG < 0, and
`(b) VG > 0.
`
`where K0x the dielectric constant of silicon oxide and 80 the dielectric
`permittivity of vacuum, and tox the thickness of oxide layer. When VG > 0,
`holes are repelled and a depletion layer of tdl in thickness is formed under the
`gate, as shown in Fig. 4.24b. The thickness rd] depends predominantly on VG
`and the doping level. Since there are no free carriers in the depletion layer, the
`depletion layer can be regarded as an insulator, and then the capacitance CS,
`which is nonlinearly variable with VG, is given by
`'
`
`Cs 2 KsiBO/tdl
`
`(4.37)
`
`where Ksi is the dielectric constant of silicon. The circuit model can be
`assumed as two series capacitors; the total capacitance C is then given by
`
`l/C = 1/CO + 1/CS
`
`(4.38)
`
`Figure 4.25 illustrates the relationship between the MOS capacitance
`(C/CO) and gate bias voltage (VG) for a p—type semiconductor in an ideal
`
`C/Co
`
`1 .o
`
`—
`
`0
`
`Vth
`
`VG (volt)
`
`+
`
`Fig. 4.25.
`
`Ideal CiV relation in an MOS capacitor fabricated on a p-type semiconductor.
`
`11
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`11
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`

`

`108
`
`4 Basic Semiconductor Physics
`
`_l_
`
`
`
`
`WWW/A Metal
`@
`lgggilgharge (Qm)
`
`
`Oxide Trapped
`Fixed Oxide
`
`Charge (Qot)
`Charge (Qf)
`
`
`
`Si02
`
`
`
`
`
`Trapped Charge (Qit)
`
`Interface
`
`SiOx
`
`Si
`
`Fig. 4.26. Charges associated with thermally oxidized silicon. (After Deal.20 ©1980 IEEE.)
`
`situation.* Under a reverse bias condition. (VG < 0), C is equal to C0 since no
`depletion layer exists. In the region 0 < VG < Vth (Vth is referred to as the
`threshon voltage), the total capacitance C decreases with increasing tdl, in
`turn decreasing CS. When VG is larger than Vt'h, C/CO becomes constant.
`However, the voltage due to the difference between the work functions of the
`metal and the semiconductor makes the C— V' curve deviate from the ideal
`situation. In addition, the charges such as shown in Fig. 4.2620 in the MOS
`capacitor also result in deviation of the C—V curve from the ideal situation.
`As shown in Fig. 4.27, when a positive charge exists at the SiOZ/Si interface,
`the C—V curve shifts to the ieft (a), While a negative charge shifts the C—V
`curve to the right (b). The voltage that is required on the gate of a MOS
`capacitor in order to achieve the ideal sima‘tion—that is, flat—band condition
`
`
`
`Fig. 4.27. Deviation of C—V curve from the ideal situation for a p-type semiconductor due to
`(a) positive charge (VFB > 0) and (b) negative Charge (VFB < 0).
`
`* Figure 4.25 shows the high—frequency C—V characteristics. At low frequencies, the capaci—
`tance goes through :a minimum at Vmin (~‘Kh) and then increases again as the inversion layer
`forms at the surface and C/CO reaches unity.=1"9'In the following, the high—frequency C—V plot,
`which is most commonly used to characterize MOS capacitors, is concerned.
`
`12
`
`12
`
`

`

`4.4 Transistors
`
`109 '
`
` C/Co T
`1 .0 : - u- u....
`IVFB
`""""
`l
`C-V curve
`"'
`I
`
`.
`
`—
`
`VG
`
`(a)
`
`+
`
`“
`
`+
`
`VG
`
`(b)
`
`Fig. 4.28. Deviation of C—V curve from the ideal situation for an n—type semiconductor due to
`(a) positive charge (VFB > O) and (b) negative charge (VFB < 0).
`
`—is defined as the flat-band voltage and is represented with VFB. For an
`n—type semiconductor, the Ca chrve shifts similarly due to the existing states
`as shown in Fig. 4.28.
`The fiat-band voltage directly affects the threshold voltage Vth, which is
`defined as the gate bias voltage required to form an inversion layer in the
`surface of a semiconductor and is one of the most important factors for the
`operation of MOS devices. Constant VFB is required to ensure high perfor—
`mance of MOS device operation.
`
`4.4.3 MOS Transistor
`
`Structure of MOSFET Devices in which the conduction involves only one
`polarity are referred to as unipolar devices, in contrast to bipolar devices.
`Among the unipolar devices,
`the MOSFET is the most important for
`VLSI/ULSI circuits. Many acronyms, such as MOST (MOS transistor),
`IGFET (insulated-gate FET), and MISFET (metal insulator semiconductor
`FET), represent the same device. Figure 4.29 depicts the basic structures of
`MOSFETS of two different types: (a) n—channel MOSFET (NMOS) and (b)
`p-channel MOSFET (PMOS). Note that the vertical and horizontal scales
`illustrated in Fig. 4.29, as in Figs. 4.20 and 4.21, do not represent a practical
`relation with each other. A MOSFET consists of four essential parts: source
`(S), gate (G), channel, and drain D. Heavily doped polysilicon or a combina—
`tion of silicide and polysilicon as well as metals such as aluminum are used as
`
`electrode
`field oxide
`Gate
`
`
`Gate
`
`
`
` gate oxide (3) (b)
`Fig. 4.29. Cross—sectional structure of enhancement—type MOSFETS: (a) n—channel MOSF ET ‘
`(NMOS) and (b) p—channel MOSFET (PMOS).
`
`
`
`13
`
`13
`
`

`

`110
`
`I
`
`4 Basic Semiconductor Physics
`
`
`
`n-type Si substrate
`
`Fig. 4.30. Cross—sectional structure of CMOS.
`
`the gate electrode. For NMOS, the source and drain regions are fabricated by
`either ion implantation or diffusion of donor impurities in the surface region,
`of the p—type Si substrate. For PMOS, on the other hand, they are fabricated
`similarly with acceptor impurities in the n—type Si substrate. In an IC, a
`MOSFET is surrounded by thQWflg
`oxide, to isolate it from adjacent devices.
`Although most of today’s FETs, specifically random-access memories
`(RAMs), are NMOS designs, complementary MOS (CMOS) RAMs are the
`wave of the future VLSI/ULSI devices, including memories, microprocessors,
`and random logic. The basic structure of CMOS fabricated on an n-type Si
`substrate is diagrammatically shown in
`It has aKPM‘OS device
`fabricated with source—drain diffusion iiito the nttype subStratewand an
`NMOS device fabricated with source-drain diffusion into the p—well (or p-
`tub), which was formed with p—type impurity diflusion into the SubStrate.
`Although the CMOS fabrication process is more complicated than that for
`simple NMOS or PMOS processes, CMOS technology21 permits such
`advantages as reduction of power consumption, much simpler circuit design
`resulting in a much more efficient circuit layout, and thus smaller chips. There
`remain, however, a few CMOS problems that must be solved, The most
`notorious problem is latchup, which becomes more diflicult to manage as the
`circuit geometry is reduced. For solutions,
`it
`is becoming common to
`fabricate CMOS circuits in high-resistivity epitaxial la ers on low—resistivity
`substrates, or to utilize a trench structure in order to efiectivel
`se arate each
`“£21322:
`»
`
`Operating Principles Figure 4.31 diagrammatically explains the operating
`principle for NMOS. The 72+ source and drain regions, where the majority
`carrier electrons exist, are formed in the p—type Si substrate where the
`majority carrier holes dominate. When no voltage is applied to the gate (i.e.,
`V = 0), drain current ID does not flow even when a low voltage isapplied to
`the drain, namely at VD — VS > 0, where VD and VS are the drain and source
`voltage, respectively, since no channel is formed between the two n+ regions
`
`
`
`14
`
`

`

`4.4 Transistors
`
`1 11
`
`
`7/.///////A
`
`
`l
`I
`I
`'-
`
`
`’
`o,
`o
`o
`
`
`Sourceouuau—g—«o‘xc, °5~—5-0\-\3~——5
`o o
`o
`O
`o
`0
`°
`° 0 °
`°
`h+ ° oodepoletionlayer
`°° °o° p-typeSi
`o
`o
`o
`
`
`
`.
`depletion layer
`(1))
`
`Fig. 4.31. Operating principle for NMOS:'(a) VG = 0 and (b) VG > 0.
`
`(see Fig. 4.3la). The only current that can flow from source to drainis the
`reverse leakage current. However, when a positive bias voltage VG is applied
`to the gate and VG exceeds the threshold voltage Kh, a surface inversion layer
`(i.e., n-channel) is formed between the source and drain, as shown in Fig.
`4.31b. The two regions are then connected by a conducting n—channel
`through which a large drain current I D can flow. The conductance of this
`channel can be modulated by varying the gate voltage. That is, the character—
`istics of the MOSFET are variable with the applied bias voltage to the gate.
`In the case of PMOS fabricated in n-type silicon, I D is obtained similarly by
`applying a reverse bias voltage VG, as shown in Fig. 4.32.
`
`
`
`(S
`
`depletion layer
`
`Fig. 4.32. Operating principle for PMOS at VG < 0.
`
`15
`
`15
`
`

`

`112
`
`‘
`
`.
`
`4 Basic Semiconductor Physics
`
`p-type Si
`
`n-channel
`
`p-channel
`
`n-type Si
`
`(1))
`
`Fig. 4.33. Cross—sectional structure of depletion~type MOSFETS: (a) NMOS and (b) PMOS.
`
`For the MOSFETS shown in Fig. 4.29, ID does not flow as zerogate bias.
`These transistors are considered to be “normally off.” This kind of transistor
`is called an enhancement—type device, because a gate bias voltage will enhance
`the conductivity of the channel. On the other hand, as shown in Fig. 4.33,
`MOSFETs that have a channel fabricated between the source and drain by
`channel doping are considered to be “normally on.” A device that is normally
`on is called a depletion—type device, because a gate bias voltage is required to
`deplete the channel resulting in no ID flow. In summary, there are basically
`four types of MOSFET depending on the types of channel and inversion
`layer: enhancement—type NMOS and PMOS, and depletion-type NMOS
`and PMOS. Although the operating principles of NMOS and PMOS are
`identical, NMOS is preferred to PlVIOS for devices that require high-speed
`switching. This is mainly because the mobility of electrons, Me,
`in an
`n—channel transiStor is greater than that of holes, ,uh, in a p-channel transistor.
`
`Contamination Effect on MOSFET Although the principle of a MOSFET
`device had been recognized since the late 1930s,
`the modern practical
`MOSFET was made in 19603 after the bipolar transistor was invented in
`1947.4’5 This is mainly due to the unsatisfactory technology of semiconductor
`surface preparation and oxide growth. As discussed, the field effect is highly
`sensitive to surface states, and in turn to surface contamination such as
`positive sodium ions. The presence of positive ions in the oxide at the SiOZ—Si
`interface attracts electrons in the silicon. This brings about a deleteriOus effect
`on an enhancement-type NMOS and a depletion-type PMOS (see Figs. 4.29a
`and 4.33b). For an IC structure, a current may flow between NMOSs, which
`must be isolated each other, because of the unfavorable channel formed by
`electrons attracted to the silicon surface. That is, only an enhancement—type
`PMOS may be influenced little by positive ion contamination. In fact, ICs
`using MOSFETS were originally based on PMOS devices,22 although
`NMOS is preferred to PMOS because of the higher electron mobility with
`respect to hole mobility as described above. The development of material and
`process technologies have made NMOS dominate in the IC market since the
`
`16
`
`16
`
`

`

`References
`
`1 13
`
`early 1970S. Again, it should be emphasized that the harmful effects of
`contamination on the device performance have to be minimized.
`
`References
`
`1. W. Schockley, “Electrons and Holes in Semiconductors.” Van Nostrand—Reinhold, New
`York, 1950.
`W. C. Dunlap, “An Introduction to Semiconductors.” New York, 1962.
`J. L. Moll, “Physics of Semiconductors.” .McGraW—Hill, New York, 1964.
`S. M. Sze, “Physics of Semiconductor Devices,” 2nd ed. Wiley, New York, 1981.
`E. H. Nicollian and J. R. Brews, “MOS (Metal Oxide Semiconductor) Physics and
`
`.V‘P‘EHN
`
`>19)
`
`Technology.” Wiley, New York, 1982.
`C. Kittel, “Elementary Solid State Physics: A Short Course.” Wiley, New York, 1962.
`J. M. Ziman, “Principles of the Theory of Solids.” Cambridge Univ. Press, London and New
`York, 1964.
`.
`8. A. Bar—Lev, “Semiconductors and Electronic Devices,” 2nd ed. Prentice—Hall, Englewood
`Cliffs, New Jersey, 1984.
`9. Y. P. Vashni, Temperature dependence of the energy gap in semiconductors. Physica
`(Amsterdam) 34, 149—154 (1967).
`10. C. D. Thurmond, The standard thermodynamic function of the formation of electrons and
`holes in Ge, Si, GaAs and GaP. J. Electrochem. Soc. 122, 1133~1141 (1975).
`11. B. M. Welch, Advances in GaAs LSI/VLSI processing technology. Solid State Technol. Feb,
`pp. 95—101 (1980).
`12. J. Bardeen and W. Schockley, Deformation potentials and mobilities in non—polar crystals.
`Phys. Rev. 80, 72—80 (1950).
`‘
`I
`13. E. Conwell and V. F. Wesskopf, Theory of impurity scattering in semiconductors. Phys. Rev.
`77, 388~390 (1950).
`14. L. A. Azaroff and J. J. Brophy, “Electronic Properties in Materials.” McGraw—Hill, New
`York, 1963.
`15. “Annual Book of ASTM Standards,” Vol. 10.05 Electronics (II) F723—82, pp. 598~614. Am.
`
`Soc. Test. Mater. Philadelphia, Pennsylvania, 1984.
`'
`16. J. C. Irvin, Resistivity of bulk silicon and of diffused layers in silicon. Bell Syst. Tech. J. 41,
`387—410 (1962).
`17. J. Bardeen and W. H. Brattain, The transistor, a semiconductor triode. Phys. Rev. 74,
`
`230—231 (1948).
`18. H. M. Liaw, J. Rose, and P. L. Fejes, Epitaxial silicon for bipolar integrated circuits. Solid
`State Technol. May, pp. 135-~143 (1984).
`19. A. S. Grove, B. E. Deal, E. H. Snow, and C. T. Sah, Investigation of thermally oxidized silicon
`surface using metal—oxide-semiconductors. Solid—State Electron. 1454163 (1985).
`20. B. E. Deal, Standard terminology for oxide charges associated with thermally oxidized
`silicon. IEEE Trans. Electron Devices ED—27, 606—608 (1980).
`21. D. B. Scott, K.—L. Chen, and R. D. Davies, CMOS VLSI technology. In “VLSI Handbook”
`(N. G. Einspruch, ed.), pp. 1217150. Academic Press, New York, 1985.
`22. L. C. Parrillo, VLSI process integration. In “VLSI Technology” (S. M. Sze, ed.). pp. 445—505.
`McGraw—Hill, New York, 1983.
`
`17
`
`17
`
`