DIGITAL
`
`INTEGRATED
`
`CIRCUITS
`
`A DESIGN PERSPECTIVE
`
`SECOND EDITION
`
`JAN M. RABAEY
`
`ANANTHA CHANDRAKASAN
`BORIVOJE NIKOLIC
`
`PRENTICE HALL ELECTRONICS AND VLSI SERIES
`
`CHARLES G. SODINI, SERIES EDITOR
`
`PearSon Education
`
`A
`
`Pearson Education, Inc.
`
`Upper Saddle River, New Jersey 07458
`
`TSMC 1110
`TSMC 1110
`
`

`

`Library of Congress Cataloging-in-Publication Data on file.
`
`Vice President and Editorial Director, ECS: Marcia J. Horton
`Publisher: Tom Robbins
`
`Editorial Assistant: Eric Van Ostenbridge
`Vice President and Director of Production and Manufacturing, ESM: David W. Riccardz'
`Executive Managing Editor: Vince O’Brien
`Managing Editor: David A. George
`Production Editor: Daniel Sandin
`
`Director of Creative Services: Paul Belfanz‘z'
`Creative Director: Carole Anson
`
`Art and Cover Director: Jayne Conte
`Art Editor: Greg Dulles
`t
`Manufacturing Manager: Trudy Pisciolti
`Manufacturing Buyer: Lisa McDowell
`Marketing Manager: Holly Stark
`
`About the Cover: Detail of "Wet Orange,” by Joan Mitchell (American, 1925—1992). Oil on canvas, 112x 245 in.
`(284.5 X 622.3 cm). Carnegie Museum of Art, Pittsburgh, PA. Gift of Kaufmann‘s Department Store and the
`National Endowment for the Arts, 74.11. Photograph by Peter Harholdt, 1995.
`
`Prentice ,
`«
`. H311»
`
`'
`
`© 2003, 1996 by Pearson Education, Inc.
`Pearson Education, Inc.
`
`Upper Saddle River, NJ 07458
`
`The author and publisher of this book have used their best efforts in preparing this book. These efforts include the devel-
`opment, research, and testing of the theories and programs to determine their effectiveness. The author and publisher
`shall not be liable in any event for incidental and consequential damages in connection with, or arising out of, the fur—
`nishing, performance, or use of these programs.
`
`All rights reserved. No part of this book may be reproduced, in any form or by any means,
`without permission in writing from the publisher.
`
`Printed in the United States of America
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`10
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`ISBN 0—13—597444-5
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`Pearson Education Ltd., London
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`Pearson Education Australia Pty, Ltd, Sydney
`Pearson Education Singapore, Pte. Ltd.
`Pearson Education North Asia Ltd, Hong Kong
`Pearson Education Canada Inc., Toronto
`Pearson Educacion de Mexico, SA. de CV.
`
`
`
`Pearson Education—Japan, Tokyo
`Pearson Education Malaysia, Pte. Ltd.
`Pearson Education Inc, Upper Saddle River, New Jersey
`
`

`

`Contents
`
`Preface
`
`vii
`
`___________._____.____.._._________————
`
`Part I
`The Fabrics
`1
`
`
`Chapter 1
`
`Introduction
`1.1
`A Historical Perspective
`1.2
`Issues in Digital Integrated Circuit Design
`1.3
`Quality Metrics of a Digital Design
`1.3.1 Cost of an Integrated Circuit
`1.3.2 Functionality and Robustness
`1.3.3 Performance
`1.3.4 Power and Energy Consumption
`Summary
`To Probe Further
`
`1.4
`1.5
`
`Reference Books
`
`References
`
`3
`4
`6
`15
`16
`18
`27
`30
`31
`31
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`32
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`33
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`35
`36
`36
`37
`37
`41
`42
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`47
`51
`52
`53
`59
`61
`61
`63
`64
`
`Chapter 2 The Manufacturing Process
`2.1
`Introduction
`2.2 Manufacturing CMOS Integrated Circuits
`2.2.1 The Silicon Wafer
`’
`2.2.2 Photolithography
`2.2.3
`Some Recurring Process Steps
`2.2.4 Simplified CMOS Process Flow
`Design Rules—The Contract between Designer
`and Process Engineer
`Packaging Integrated Circuits
`2.4.1
`Package Materials
`2.4.2
`Interconnect Levels
`2.4.3 Thermal Considerations in Packaging
`Perspective—Trends in Process Technology
`2.5.1
`Short—Term Developments
`2.5.2
`In the Longer Term
`Summary
`
`2.5
`
`2.6
`
`2.3
`
`2.4
`
`XV
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`

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`
`
`xvi
`
`Contents
`
`2.7
`
`To Probe Further
`
`References
`
`Design Methodology InsertA IC LAYOUT
`
`A.1
`
`To Probe Further
`
`References
`
`Chapter 3
`
`The Devices
`
`1
`
`3.1
`
`3 .2
`
`Introduction
`
`The Diode
`
`3.2.1 A First Glance at the Diode—The Depletion Region
`3.2.2 Static Behavior
`
`3.2.3 Dynamic, or Transient, Behavior
`3.2.4 I The Actual Diode—Secondary Effects
`3.2.5 The SPICE Diode Model
`
`33.3
`
`The MOS(FET) Transistor
`3.3.1 A First Glance at the Device
`
`3.3.2 The MOS Transistor under Static Conditions
`3.3.3 The Actual MOS Transistor—Some Secondary Effects
`3.3.4 SPICE Models for the MOS Transistor
`
`3.4
`
`3.5
`
`3.6
`
`3.7
`
`A Word on Process Variations
`
`Perspective—Technology Scaling
`Summary
`To Probe Further
`
`References
`
`Design Methodology Insert B Circuit Simulation
`
`References
`
`Chapter 4 The Wire
`
`4.1
`
`4.2
`
`4.3
`
`Introduction
`
`A First Glance
`
`Interconnect Parameters—Capacitance, Resistance,
`and Inductance
`
`4.3.1 Capacitance
`4.3.2 Resistance
`
`4.3.3
`
`Inductance
`
`4.4
`
`Electrical Wire Models
`
`4.4.1 The Ideal Wire
`
`4.4.2 The Lumped Model
`4.4.3 The Lumped RC Model
`4.4.4 The Distributed rc Line
`
`4.4.5 The Transmission Line
`
`64
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`64
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`67
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`71
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`71
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`73
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`74
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`74
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`75
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`77
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`80
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`84
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`85
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`87
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`87
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`88
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`114
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`117
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`120
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`122
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`128
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`129
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`130
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`131
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`134
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`135
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`136
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`136
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`138
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`138
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`144
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`148
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`150
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`151
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`151
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`152
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`156
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`159
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`Contents
`
`4.5
`
`SPICE Wire Models
`
`4.5.1 Distributed rc Lines in SPICE
`
`4.5.2 Transmission Line Models in SPICE
`
`4.5.3 Perspective: A Look into the Future
`
`4.6
`
`4.7
`
`Summary
`To Probe Further
`
`References
`
`Part 2
`
`A Circuit Perspective
`
`Chapter 5
`
`The CMOS Inverter
`
`5.1
`
`5.2
`
`5.3
`
`5.4
`
`5.5
`
`5.6
`
`5.7
`
`5.8
`
`Introduction
`
`The Static CMOS Inverter—An Intuitive Perspective
`Evaluating the Robustness of the CMOS Inverter:
`The Static Behavior
`
`5.3.1
`
`Switching Threshold -
`
`5.3.2 Noise Margins
`5.3.3 Robustness Revisited
`
`Performance of CMOS Inverter: The Dynamic Behavior
`5.4.1 Computing the Capacitances
`5.4.2 Propagation Delay: First—Order Analysis
`5.4.3 Propagation Delay from a Design Perspective
`Power, Energy, and Energy Delay
`5.5.1 Dynamic Power Consumption
`
`5.5.2
`
`Static Consumption
`
`5.5.3 Putting It All Together
`
`5.5.4 Analyzing Power Consumption Using SPICE
`Perspective: Technology Scaling and its Impact
`on the Inverter Metrics
`‘
`
`Summary
`To Probe Further
`
`References
`
`Chapter 6 Designing Combinational Logic Gates in CMOS
`
`, 6.1
`
`6.2
`
`Introduction
`
`Static CMOS Design
`6.2.1 Complementary CMOS
`
`6.2.2 Ratioed Logic
`
`6.3
`
`6.2.3
`Pass—Transistor Logic
`Dynamic CMOS Design
`6.3.1 Dynamic Logic: Basic Principles
`
`6.3.2 Speed and Power Dissipation of Dynamic Logic
`
`xvii
`
`170
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`170
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`170
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`171
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`174
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`174
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`174
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`177
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`179
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`180
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`180
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`184
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`185
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`188
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`191
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`193
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`194
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`199
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`203
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`213
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`214
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`223
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`225
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`227
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`229
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`232
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`233
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`233
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`235
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`236
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`236
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`237
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`263
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`269
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`284
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`284
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`287
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`

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`
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`xviii
`
`Contents
`
`6.4
`
`6.5
`
`6.6
`
`Signal Integrity Issues in Dynamic Design
`6.3.3
`6.3.4 Cascading Dynamic Gates
`Perspectives
`6.4.1 How to Choose a Logic Style?
`6.4.2 Designing Logic for Reduced Supply Voltages
`Summary
`To Probe Further
`References
`
`Design Methodology Insert C How to Simulate Complex
`Logic Circuits
`
`C1
`
`C2
`C3
`
`Representing Digital Data as a Continuous Entity
`Representing Data as a Discrete Entity
`Using Higher—Level Data Models
`References
`
`290
`295
`303
`303
`303
`306
`307
`308
`
`309
`
`310
`310
`315
`3 17
`
`Design Methodology Insert D Layout Techniques for Complex Gates 319
`
`Chapter 7 Designing Sequential Logic Circuits
`
`'
`
`7.1
`
`7.2
`
`7.3
`
`7.4
`
`7.5
`
`7.6
`
`7.7
`7.8
`
`Introduction
`7.1.1 Timing Metrics for Sequential Circuits
`7.1.2 Classification of Memory Elements
`Static Latches and Registers
`7.2.1 The Bistability Principle
`7.2.2 Multiplexer—B ased Latches
`7.2.3 Master—Slave Edge—Triggered Register
`’
`7.2.4 Low-Voltage Static Latches
`7.2.5
`Static SR Flip—Flops—Writing Data by Pure Force
`Dynamic Latches and Registers
`7.3.1 Dynamic Transmission-Gate Edge—triggered Registers
`7.3.2 C2MOS—A Clock—Skew lnsensitive Approach
`7.3.3 True Single-Phase Clocked Register (TSPCR)
`Alternative Register Styles*
`7.4.1
`Pulse Registers
`7.4.2 Sense-Amplifier-Based Registers
`Pipelining: An Approach to Optimize Sequential Circuits
`7.5.1 Latch- versus Register—Based Pipelines
`7.5.2 NORA-CMOS—A Logic Style for Pipelined Structures
`Nonbistable Sequential Circuits
`7.6.1 The Schmitt Trigger
`7.6.2 Monostable Sequential Circuits
`7.6.3 Astable Circuits
`Perspective: Choosing a Clocking Strategy
`Summary
`
`325
`
`326
`327
`328
`330
`330
`332
`333
`339
`341
`344
`344
`346
`350
`354
`354
`356
`358
`360
`361
`364
`364
`367
`368
`370
`371
`
`

`

`
`
`Contents
`
`7.9
`
`To Probe Further
`References
`
`xix
`
`372
`372
`
`_______________________________._____——————————-——
`Part 3
`A System Perspective
`375
`
`Chapter 8
`
`8.3
`8.4
`
`Implementation Strategies for Digital ICS
`8.1
`Introduction
`8.2
`From Custom to Semicustom and Structured—Array
`Design Approaches
`Custom Circuit Design
`Cell—Based Design Methodology
`8.4.1
`Standard Cell
`8.4.2 Compiled Cells
`8.4.3 Macrocells, Megacells and Intellectual Property
`8.4.4 Semicustom Design Flow
`Array—Based Implementation Approaches
`8.5.1
`Prediffused (or Mask—Programmable) Arrays
`8.5.2 Prewired Arrays
`Perspective——The Implementation Platform of the Future
`Summary
`To Probe Further
`References
`
`8.5
`
`8.6
`8.7
`8.8
`
`Design Methodology Insert E Characterizing Logic
`and Sequential Cells
`References
`
`Design Methodology Insert F Design Synthesis
`References
`
`A
`
`9.3
`
`Chapter 9 Coping with Interconnect
`9.1
`Introduction
`9.2
`Capacitive Parasitics
`9.2.1 Capacitance and Reliability—~Cross Talk
`9.2.2 Capacitance and Performance in CMOS
`Resistive Parasitics
`9.3.1 Resistance and Reliability—Ohmic Voltage Drop
`9.3.2 Electromigration
`9.3.3 Resistance and Performance—RC Delay
`Inductive Parasiticsx
`9.4.1
`Inductance and Reliability— Voltage Drop
`9.4.2
`Inductance and Performance—Transmission—line Effects
`Advanced Interconnect Techniques
`
`9.4
`
`9.5
`
`377
`378
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`382
`383
`384
`385
`390
`392
`396
`399
`399
`404
`420
`423
`423
`424
`
`427
`434
`
`435
`443
`
`445
`446
`446
`446
`449
`460
`460
`462
`464
`469
`469
`475
`480
`
`

`

`XX
`
`
`
`Contents
`
`9.5.1 Reduced~Swing Circuits
`
`9.5.2 Current—Mode Transmission Techniques
`Perspective: Networks-on-a-Chip
`Summary
`To Probe Further
`
`9.6
`
`9.7
`
`9.8
`
`References
`
`Chapter 10 Timing Issues in Digital Circuits
`
`10.1
`
`Introduction
`
`10.2 Timing Classification of Digital Systems
`10.2.1 Synchronous Interconnect
`10.2.2 Mesochronous interconnect
`
`10.2.3 Plesiochronous Interconnect
`10.2.4 Asynchronous Interconnect
`Synchronous Design—An In-depth Perspective
`10.3.1 Synchronous Timing Basics
`10.3.2 Sources of Skew and Jitter
`
`10.3.3 Clock—Distribution Techniques
`10.3.4 Latch—Based Clocking>s
`Self-Timed Circuit Design*
`10.4.1 Self-Timed Logic——An Asynchronous Technique
`10.4.2 Completion-Signal Generation
`
`10.4.3 Self—Timed Signaling
`10.4.4 Practical Examp1es of Self—Timed Logic
`Synchronizers and Arbiters$
`10.5.1 Synchronizers—Concept and Implementation
`10.5.2 Arbiters
`
`Clock Synthesis and Synchronization Using
`a Phase—Locked LoopX
`10.6.1 Basic Concept
`10.6.2 Building Blocks of a PLL
`Future Directions and Perspectives
`10.7.1 Distributed Clocking Using DLLs
`10.7.2 Optical Clock Distribution
`10.7.3 Synchronous versus Asynchronous Design
`Summary
`To Probe Further
`
`References
`
`10.3
`
`10.4
`
`10.5
`
`10.6
`
`10.7
`
`10.8
`
`10.9
`
`Design Methodology Insert G Design Verification
`
`References
`
`480
`
`486
`
`487
`
`488
`
`489
`
`489
`
`491
`
`492
`
`492
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`492
`
`493
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`493
`
`494
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`495
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`495
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`502
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`508
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`516
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`519
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`519
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`522
`
`526
`
`531
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`534
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`534
`
`538
`
`539
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`540
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`542
`
`546
`
`546
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`548
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`549
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`550
`
`551
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`551
`
`553
`
`557
`
`

`

`
`
`Contents
`
`Chapter 1] Designing Arithmetic Building Blocks
`"
`11.1
`Introduction
`
`11.2 Datapaths in Digital Processor Architectures
`11.3 The Adder
`
`11.3.1 The Binary Adder: Definitions
`11.3.2 The Full Adder: Circuit Design Considerations
`11.3.3 The Binary Adder: Logic Design Considerations
`
`11.4 The Multiplier
`11.4.1 The Multiplier: Definitions
`11.4.2 Partial-Product Generation
`
`11.4.3 Partial-Product Accumulation
`
`11.4.4 Final Addition
`
`11.4.5 Multiplier Summary
`
`11.5 The Shifter
`
`11.5.1 Barrel Shifter
`
`11.5.2 Logarithmic Shifter
`11.6 Other Arithmetic Operators
`11.7 Power and Speed Trade-offs in Datapath Structures*
`11.7.1 Design Time Power—Reduction Techniques
`11.7.2 Run—Time Power Management
`11.7.3 Reducing the Power in Standby (or Sleep) Mode
`11.8 Perspective: Design as a Trade—off
`11.9 Summary
`11.10 To Probe Further
`
`References
`
`Chapter 12 Designing Memory and Array Structures
`
`12.1
`
`Introduction
`
`12. 1 . 1 Memory Classification
`12.1.2 Memory Architectures and Building
`
`Blocks
`
`12.2 The Memory Core
`12.2.1 Read—Only Memories
`12.2.2 Nonvolatile Read—Write Memories
`
`12.2.3 Read—Write Memories (RAM)
`12.2.4 Contents-Addressable orAssociative Memory (CAM)
`12.3 Memory Peripheral Circuitry¥
`12.3.1 The Address Decoders
`
`12.3.2 Sense Amplifiers
`12.3.3 Voltage References
`12.3.4 Drivers/Buffers
`
`12.3.5 Timing and Control
`
`xxi
`
`559
`
`560
`
`560
`
`561
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`561
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`564
`
`571
`
`586
`
`586
`
`587
`
`589
`
`593
`
`594
`
`594
`
`595
`
`596
`
`596
`
`600
`
`601
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`611
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`617
`
`618
`
`619
`
`620
`
`621
`
`623
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`624
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`625
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`627
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`634
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`634
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`647
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`657
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`670
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`672
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`672
`
`679
`
`686
`
`689
`
`689
`
`

`

`
`
`xxii
`
`Contents
`
`12.4 Memory Reliability and Yield*
`12.4.1 Signal—to-Noise Ratio
`
`12.4.2 Memory Yield
`12.5 Power Dissipation in Memories*
`12.5.1 Sources of Power Dissipation in Memories
`
`12.5.2 Partitioning of the Memory
`
`12.5.3 Addressing the Active Power Dissipation
`12.5.4 Data—Retention Dissipation
`
`12.5.5 Summary
`12.6 Case Studies in Memory Design
`12.6.1 The Programmable Logic Array (PLA)
`12.6.2 A 4—Mbit SRAM
`
`1.2.6.3 A 1-Gbit NAND Flash Memory
`12.7 Perspective: Semiconductor Memory Trends and Evolutions
`12.8 Summary
`12.9 To Probe Further
`
`References
`
`Design Methodology Insert H Validation and Test
`of Manufactured Circuits
`
`H1
`
`H.2
`
`Introduction
`
`Test Procedure
`
`H.3 Design for Testability
`H.3.l
`Issues in Design for Testability
`
`H.3.2 Ad Hoc Testing
`H.3.3 Scan-Based Test
`
`H.3.4 Boundary—Scan Design
`
`H.3.5 Built-in Self-Test (BIST)
`
`H.4
`
`Test—Pattern Generation
`
`H.4.1 Fault Models
`
`H.4.2 Automatic Test—Pattern Generation (ATPG)
`H.4.3 Fault Simulation
`
`H.5
`
`To Probe Further
`
`References
`
`Problem Solutions
`
`Index
`
`693
`693
`
`698
`701
`701
`
`702
`
`702
`704
`
`707
`707
`707
`710
`
`712
`714
`716
`717
`
`718
`
`721
`
`721
`
`722
`
`723
`723
`
`725
`726
`
`729
`
`730
`
`734
`
`734
`
`736
`737
`
`737
`
`737
`
`739
`
`745
`
`

`

`
`
`
`CHAPTER
`
`The Manufacturing Process
`
`
`
`Overview of manufacturing process
`
`‘ DeSign rules
`
`IC packaging
`
`Future Trends in Integrated Circuit Technology
`
`
`2.1
`
`2.2
`
`2.3
`
`2.4
`
`2.5
`
`2.6
`
`2.7
`
`Introduction
`
`Manufacturing CMOS Integrated Circuits
`2.2.1
`The Silicon Water
`
`2.2.2
`2.2.3
`2.2.4
`
`Photolithography
`Some Recurring Process Steps
`Simplified CMOS Process Flow
`
`Design Rules—Between the Designer and the Process Engineer
`
`Packaging integrated Circuits
`2.4.1
`Package Materials
`2.4.2
`Interconnect Levels
`
`2.4.3
`
`Thermal Considerations in Packaging
`
`Perspective—Trends in Process Technology
`2.5.1
`Short-Term Developments
`2.5.2
`In the LongerTerm
`
`Summary
`
`To Probe Further
`
`35
`
`

`

`
`
`36
`
`Chapter 2 - The Manufacturing Process
`
`2.1
`
`Introduction
`
`Most digital designers will never be confronted with the details of the manufacturing process
`
`that lay at the core of the semiconductor revolution. Still, some insight into the steps that lead to
`
`an operational silicon chip comes in quite handy in understanding the physical constraints
`
`imposed on a designer of an integrated circuit, as well as the impact of the fabrication process on
`issues such as cost.
`
`In this chapter, we briefly describe the steps and techniques used in a modern integrated
`
`Circuit manufacturing process. It is not our aim to present a detailed description of the fabrica—
`
`tion technology, which easily deserves a complete course [PlummerOO]. Rather, we aim at pre—
`
`senting the general outline of the flow and the interaction between the various steps. We learn
`
`that a set of optical masks forms the central interface between the intrinsics of the manufacturing
`
`process and the design that the user wants to see transferred to the silicon fabric. The masks
`
`define the patterns that, when transcribed onto the different layers of the semiconductor material,
`
`form the elements of the electronic devices and the interconnecting wires. As such, these pat-
`
`terns have to adhere to some constraints, in terms of minimum width and separation, if the
`
`resulting circuit is to be fully functional. This collection of constraints is called the design rule
`
`set, and acts as the contract between the circuit designer and the process engineer. If the designer
`
`adheres to these rules, he gets a guarantee that his circuit will be manufacturable. An overview
`
`of the common design rules encountered in modern CMOS processes is given, as well as a per-
`
`spective on the IC packaging options. The package forms the interface between the circuit
`
`implemented on the silicon die and the outside world, and as such has a major impact on the per~
`
`formance, reliability, longevity, and cost of the integrated circuit.
`
`2.2 Manufacturing CMOS Integrated Circuits
`
`A simplified cross section of a typical CMOS inverter is shown in Figure 2—1. The CMOS pro—
`
`cess requires that both n—channel (NMOS) and p—channel (PMOS) transistors be built in the
`
`same silicon material. To accommodate both types of devices, special regions called wells must
`
`be created in which the semiconductor material is opposite to the type of the channel. A PMOS
`
`transistor has to be created in either an n—type substrate or an n-well, while an NMOS device
`
`resides in either a p—type substrate or a p—well. The cross section shown in Figure 2-1 features an
`
`Polysilicon
`
`A1
`
`
`
`3102
`
`Figure 2-1 Cross section of an n—weii CMOS process.
`
`p—substrate
`
`
`
`
`
`

`

`
`Et
`
`
`
`
`
`
`
`2.2 Manufacturing CMOS Integrated Circuits
`
`37
`
`gate'oxide
`
`Tungsten
`\
`
`TiSi2
`
`
`
`
`
`Figure 2-2 Cross section of modem dual-well CMOS process.
`
`n~well CMOS process, Where the NMOS transistors are implemented in the p-doped substrate,
`and the PMOS devices are located in the n—well. Modern processes are increasingly using a
`dual-well approach that uses both n~ and p-wells, grown on top of an epitaxial layer, as shown in
`
`Figure 2-2.
`The CMOS process requires a large number of steps, each of which consists of a sequence
`of basic operations. A number of these steps and/or operations are executed very repetitively in
`the course of the manufacturing process. Rather than immediately delving into a description of
`the overall process flow, we first discuss the starting material followed by a detailed perspective
`on some of the most frequently recurring operations.
`
`2.2.1
`
`The Silicon Wafer
`
`The base material for the manufacturing process comes in the form of a single—crystalline,
`lightly doped wafer. These wafers have typical diameters between 4 and 12 inches (10 and
`30 cm, respectively) and a thickness of, at most 1 mm. They are obtained by cutting a single—
`crystal ingot into thin slices (see Figure 2-3). A starting wafer of the pitype might be doped
`around the levels of 2 X 1021 impurities/m3. Often, the surface of the wafer is doped more
`heavily, and a single crystal epitaxial layer of the opposite type is grown over the surface before
`the wafers are handed to the processing company. One important metric is the defect density of
`the base material. High defect densities lead to a larger fraction of nonfunctional circuits, and
`
`consequently an increase in cost of the final product.
`
`2.2.2
`
`Photolithography
`
`In each processing step, a certain area on the chip is masked out using the appropriate optical
`mask so that a desired processing step can be selectively applied to the remaining regions. The
`processing step can be any of a Wide range of tasks, including oxidation, etching, metal and
`polysilicon deposition, and ion implantation. The technique to accomplish this selective mask—
`ing, called photolithography, is applied throughout the manufacturing process. Figure 2—4 gives
`
`

`

`
`
`38
`
`Chapter 2 - The Manufacturing Process
`
`
`
`
`
`Figure 2-3 Single-crystal ingot and sliced wafers (from [Fullman99]).
`
`optical
`mask
`
`
`
`
`
`oxidation
`
`
`
`
`photoresist coating
`
`
`photoresist
`stepper exposure
`removal (ashing)
`
`
`
`
`
` photoresist
`development
`
`
`
`process
`step
`
`spin, rinse, dry
`
`acid etch
`
`
`
`
`Figure 2-4 Typical operations in a single photolithographic cycle (from [Fullman99]).
`
`

`

`
`
`2.2 Manufacturing CMOS Integrated Circuits
`
`39
`
`a graphical overview of the different operations involved in a typical photolithographic process.
`
`The following steps can be identified:
`
`1. Oxidation layering~this optional step deposits a thin layer of SiO2 over the complete
`
`wafer by exposing it to a mixture of high—purity oxygen and hydrogen at approximately
`
`lOOOOC. The oxide is used as an insulation layer and also forms transistor gates.
`
`2. Photoresist coating—a light—sensitive polymer (similar to latex) is evenly applied to a
`
`thickness of approximately 1 pm by spinning the wafer. This material is originally soluble
`
`in an organic solvent, but has the property that the polymers cross—link when exposed to
`
`light, making the affected regions insoluble. A photoresist of this type is called negative. A
`positive photoresist has the opposite properties; originally insoluble, but soluble after
`
`exposure. By using both positive and negative resists, a single mask can sometimes be
`used for two steps, making complementary regions available for processing. Since the cost
`of a mask is increasing quite rapidly with the scaling of technology, reducing the number
`of masks surely is a high priority.
`3. Stepper exposure—a glass mask (or reticle) containing the patterns that we want to trans-
`
`fer to the silicon is brought in close proximity to the wafer. The mask is opaque in the
`
`regions that we want to process, and transparent in the others (assuming a negative photo—
`resist). The glass mask can be thought of as the negative of one layer of the microcircuit.
`The combination of mask and wafer is now exposed to ultraviolet light. Where the mask is
`
`transparent, the photoresist becomes insoluble.
`
`4. Photoresist development and bake—«the wafers are developed in either an acid or base
`
`solution to remove the nonexposed areas of photoresist. Once the exposed photoresist is
`
`removed, the wafer is “soft baked” at a low temperature to harden the remaining
`
`photoresist.
`5. Acid etchingmmaterial is selectively removed from areas of the wafer that are not covered
`by photoresist. This is accomplished through the use of many different types of acid, base
`and caustic solutions as a function of the material that is to be removed. Much of the work
`with chemicals takes place at large wet benches where special solutions are prepared for
`specific tasks. Because of the dangerous nature of some of these solvents, safety and envi-
`
`ronmental impact is a primary concern.
`6. Spin, rinse, and dry—a special tool (called SRD) Cleans the wafer with deionized water
`
`and dries it with nitrogen. The microscopic scale of modern semiconductor devices means
`that even the smallest particle of dust or dirt can destroy the circuitry. To prevent this from
`happening, the processing steps are performed in ultraclean rooms where the number of
`dust particles per cubic foot of air ranges between 1 and 10. Automatic wafer handling and
`robotics are used whenever possible. This explains why the cost of a state—of—the—art
`
`fabrication facility easily reaches multiple billions of dollars. Even then, the wafers must
`
`be constantly cleaned to avoid contamination and to remove the leftover of the previous
`
`process steps.
`
`l l 1 i2i
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`2
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`i
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`40
`
`Chapter 2 o The Manufacturing Process
`
`7. Various process steps——the exposed area can now be subjected to a wide range of process
`
`steps, such as ion implantation, plasma etching, or metal deposition. These are the subjects
`
`of the subsequent section.
`
`8. Photoresist removal (or ashtng)—a high—temperature plasma is used to selectively remove
`
`the remaining photoresist without damaging device layers.
`
`In Figure 2—5, we illustrate the use of the photolithographic process for one specific exam-
`
`ple, the patterning of a layer of SiOz. The sequence of process steps shown in the figure patterns
`
`exactly one layer of the semiconductor material and may seem very complex. Yet, the reader has
`
`to bear in mind that the same sequence patterns the layer of the complete surface of the wafer.
`
`Hence, it is a very parallel process, transferring hundreds of millions of patterns to the semicon—
`
`ductor surface simultaneously. The concurrent and scalable nature of the optolithographical pro—
`
`cess is what makes the cheap manufacturing of complex semiconductor circuits possible, and
`
`lies at the core of the economic success of the semiconductor industry.
`
`The continued scaling of the minimum feature sizes in integrated circuits puts an enormous
`
`burden on the developer of semiconductor manufacturing equipment. This is especially true for
`
`the optolithographical process. The dimensions of the features to be transcribed surpass the
`wavelengths of the optical light sources, so that achieving the necessary resolution and accuracy
`
`Si substrate
`
`(a) Silicon base material
`
`'
`
`Chemical or plasma
`etch
`
`Hardened resist
`
`Si02
`
`Photoresist
`
`Si substrate
`
`
`s102
`
`
`
`Si substrate
`
`(d) After development and etching of resist,
`chemical or plasma etch of SiOZ
`
`Si02 (b) After oxidation and deposition
`
`Hardened resist
`
`of negative photoresist
`
`Si substrate
`
`lHHHHH
`
`UV light
`Patterned
`
`optical mask
`
`(e) After etching
`
`t l imt l l
`
` Exposed resist
`
`
`Si substrate
`
`
`
`(c) Stepper exposure
`
`
`/— sro2
`—\
`
`
`
`Si substrate
`
`
`
`(f) Final result after removal of resist
`
`Figure 2-5 Process steps for patterning of 3:02.
`
`i.
`E.
`‘3’
`
`
`
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`
`
`
`2.2 Manufacturing CMOS Integrated Circuits
`
`41
`
`becomes more and more difficult. So far, electrical engineering has extended the lifetime of this
`
`process at least until the 100 nm (or 0.1 pm) process generation. Techniques such as optical mask
`
`correction (OPC) prewarp the drawn patterns to account for the diffraction phenomena, encoun—
`
`tered when printing close to the wavelength of the available optical source. This adds substan—
`
`tially to the cost of mask making. In the foreseeable future, other solutions that offer a finer
`
`resolution, such as extreme ultraviolet (EUV), X ray, or electron beam, may be needed. These
`
`techniques, while fully functional, are currently less attractive from an economic viewpoint.
`
`2.2.3
`
`Some Recurring Process Steps
`
`Diffusion and Ion Implantation
`
`Many steps of the integrated circuit manufacturing process require a change in the dopant con—
`
`centration of some parts of the material. Examples include the creation of the source and drain
`
`regions, well and substrate contacts, the doping of the polysilicon, and the adjustments of the
`
`device threshold. Two approaches exist for introducing these dopants—diffusion and ion
`
`implantation. In both techniques, the area to be doped is exposed, while the rest of the wafer is
`
`coated with a layer of buffer material, typically SiOZ.
`
`In dificusion implantation, the wafers are placed in a quartz tube embedded in a heated fur—
`
`nace. A gas containing the dopant is introduced in the tube. The high temperatures of the fur-
`
`nace, typically 900 to 1100 °C, cause the dopants to diffuse into the exposed surface both
`
`vertically and horizontally. The final dopant concentration is the greatest at the surface and
`
`decreases in a gaussian profile deeper in the material.
`
`In ion implantation, dopants are introduced as ions into the material. The ion implantation
`
`system directs and sweeps a beam of purified ions over the semiconductor surface. The accelera-
`
`tion of the ions determines how deep they will penetrate the material, while the beam current
`
`and the exposure time determine the dosage. The ion implantation method allows for an inde—
`
`pendent control of depth and dosage. This is the reason that ion implantation has largely dis-
`
`placed diffusion in modern semiconductor manufacturing.
`
`Ion implantation has some unfortunate side effects, however, the most important one being
`
`lattice damage. Nuclear collisions during the high energy implantation cause the displacement
`
`of substrate atoms, leading to material defects. This problem is largely resolved by applying a
`
`subsequent annealing step, in which the wafer is heated to around 1000°C for 15 to 30 minutes,
`
`and then allowed to cool slowly. The heating step thermally vibrates the atoms, which allows the
`bonds to reform.
`
`Deposition
`
`Any CMOS process requires the repetitive deposition of layers of a material over the complete
`
`wafer, to either act as buffers for a processing step, or as insulating or conducting layers. We
`
`have already discussed the oxidation process, which allows a layer of SiO2 to be grown. Other
`
`materials require different techniques. For instance, silicon nitride (Si3N4) is used as a sacrificial
`
`buffer material during the formation of the field oxide and the introduction of the stopper
`
`

`

`
`
`42
`
`Chapter 2 o The Manufacturing Process
`
`implants. This silicon nitride is deposited everywhere using a process called chemical vapor
`deposition or CVD. This process is based on a gas—phase reaction, with energy supplied by heat
`at around 850°C.
`
`Polysilicon, on the other hand, is deposited using a chemical deposition process, which
`flows silane gas over the heated wafer coated with SiO2 at a temperature of approximately
`650°C. The resulting reaction produces a noncrystalline or amorphous material called polysili-
`can. To increase the conductivity of the material, the deposition has to be followed by an implan—
`
`tation step.
`The Aluminum interconnect layers typically are deployed using a process known as sput—
`tering. The aluminum is evaporated in a vacuum, with the heat for the evaporation delivered by
`electron—beam or ion—beam bombarding. Other metallic interconnect materials such as Copper
`
`require different deposition techniques.
`
`Etching
`
`Once a material has been deposited, etching is used selectively to form patterns such as wires
`and contact holes. We already discussed the wet etching process, which makes use of acid or
`basic solutions. Hydrofluoric acid buffered with ammonium fluoride typically is used to etch
`
`SiOZ, for example.
`In recent years, city or plasma etching has advanced substantially. A wafer is placed into
`the etch tool's processing chamber and given a negative electrical charge. The chamber is heated
`to 100°C and brought to a vacuum level of 7.5 Pa, then filled with a positively charged plasma
`(usually a mix of nitrogen, chlorine, and boron trichloride). The opposing electrical charges
`cause the rapidly moving plasma molecules to align themselves in a vertical direction, forming a
`microscopic chemical and physical “sandblasting” action which removes the exposed material.
`Plasma etching has the advantage of offering a well—defined directionality to the etching action,
`
`creating patterns with sharp vertical contours.
`
`Planarization
`
`To reliably deposit a layer of material onto the semiconductor surface, it is essential that the sur-
`face be approximately flat. If special steps were not taken, this would definitely present prob—
`lems in modern CMOS processes, where multiple patterned metal interconnect layers are
`superimposed onto each other. Therefore, a chemical—mechanical planarization (CMP) step is
`included before the deposition of an extra metal layer on top of the insulating SiO2 layer. This
`process uses a slurry compound-a liquid carrier with a suspended abrasive component such as
`aluminum oxide or silica———to microscopically plane a device layer and to reduce the step
`
`heights.
`
`2.2.4
`
`Simplified CMOS Process Flow
`
`The gross outline of a potential CMOS process flow is given in Figure 2-6. The process starts
`with the definition of the active regions—~these are the regions where transistors will be con-
`structed. All other areas of the die will be covered with a thick layer of silicon dioxide (SiOZ)
`
`
`
`

`

`
`
`2.2 Manufacturing CMOS Integrated Circuits
`
`43
`
`
`
`Define active areas
`Etch and fill trenches
`
`
`l
`
`Implant well regions
`
`
`
`i
`
`Deposit and pattern
`polysilicon layer
`
`
`
`
`
`l
`
`Implant source and drain
`regions and substrate contacts
`
`i
`
`Create contact and Via windows
`
`Deposit and pattern metal layers
`
`
`Figure 2-6 Simplified process sequence for the manufacturing of a n-duaI—weii CMOS circuit.
`
`called the field oxide. This oxide acts as the insulator between neighboring devices, and it is
`
`either grown (as in the process of Figure 2-1) or deposited in etched trenches (Figure 2—2)—
`hence, the name trench insulation. Further insulation is provided by the addition of a reverse—
`biased np—diode, formed by adding an extra p+ region called the channel-stop implant (or field
`implant) underneath the field oxide. Next, lightly doped p— and n—wells are formed through ion
`implantation. To construct an NMOS transistor in a 19—well, heavily doped n—type source and
`drain regions are implanted (or diffused) into the lightly doped p—type substrate. A thin layer of
`SiO2 called the gate oxide separates the region between the source and drain, and is itself cov—
`ered by conductive polycrystalline silicon (or polysilicon, for short). The conductive material
`forms the gate of the transistor. PMOS transistors are constructed in an n-well in a similar fash-
`ion (just reverse n’s and p’s). Multiple insulated layers of metal