(12) United States Patent
`US 6,406,963 B2
`(10) Patent N0.:
`Woerlee et al.
`(45) Date of Patent:
`Jun. 18, 2002
`
`US006406963B2
`
`(54) METHOD OF MANUFACTURING A
`SEMICONDUCTOR DEVICE
`
`6,281,559 B1 *
`
`8/2001 Yu et a1. ................... .. 257/407
`
`FOREIGN PATENT DOCUMENTS
`
`(75)
`
`Inventors: Pierre Hermanus Woerlee; Jurriaan
`Schmitz; Andreas Hubertus Montree,
`all of Eindhoven (NL)
`
`(73) Assignee: Koninklijke Philips Electronics N.A.,
`Eindhoven (NL)
`
`EP
`EP
`EP
`JP
`WO
`
`0810647 A2
`0838849 A2
`0929105 A2
`06053237 A
`0117008 A1
`
`12/1997
`4/1998
`7/1999
`2/1994
`3/2001
`
`OTHER PUBLICATIONS
`
`*
`
`Notice:
`
`J
`y
`Sub'ect to an disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`“CMOS Metal Replacement Gate Transistors using Tanta-
`lum Pentoxide Gate Insulator”, by A. Chatterjee et al.,
`IEDM 1998, pp. 777—780.
`
`(21) Appl. No.: 09/738,917
`
`(22)
`
`Filed:
`
`Dec. 14, 2000
`
`(30)
`
`Foreign Application Priority Data
`
`* cited by examiner
`
`Primary Examiner—John F. Niebling
`Assistant Examiner—Walter L. Lindsay, Jr.
`(74) Attorney, Agent, or Firm—Aaron Waxler
`
`Dec. 17, 1999
`
`(EP) .......................................... .. 99204374
`
`(57)
`
`ABSTRACT
`
`Int. Cl.7 ............................................ .. H01L 21/336
`(51)
`(52) US. Cl.
`..................... .. 438/291; 438/299; 438/300;
`438/301
`
`(58) Field of Search ............................... .. 438/197, 299,
`438/291, 300, 305, 199, 194, 301, 585
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`................. .. 437/41
`2/1998 Chao et al.
`5,714,398 A
`10/1998 Chiang et al.
`. . . . .
`. . . .. 438/624
`5,817,572 A
`
`............. .. 438/291
`1/1999 Lee et a1.
`5,856,225 A
`
`5/2000 Rodder .................. .. 438/291
`6,063,675 A *
`
`6,127,232 A * 10/2000 Chatterjee et al.
`.
`438/291
`
`6,146,955 A * 11/2000 Lee ....................... .. 438/305
`
`6,177,303 B1 *
`1/2001 Schmitz et al.
`438/194
`
`6,200,865 B1 *
`3/2001 Gardner et al.
`438/291
`
`5/2001 Yu ........................ .. 438/301
`6,225,173 B1 *
`
`6,232,164 B1 *
`5/2001 Tsai et al.
`438/217
`
`6,245,618 B1 *
`6/2001 An et al.
`438/289
`
`8/2001 Suguro ..................... .. 257/407
`6,271,573 B1 *
`
`In a method of manufacturing a semiconductor device
`comprising a semiconductor body 1 which is provided at a
`surface 2 with a transistor comprising a gate structure 21, a
`patterned layer 10 is applied defining the area of the gate
`structure 21. Subsequently, a dielectric layer 18 is applied in
`such a way, that the thickness of the dielectric layer 18 next
`to the patterned layer 10 is substantially equally large or
`larger than the height of the patterned layer 10, which
`dielectric layer 18 is removed over part of its thickness until
`the patterned layer 10 is exposed. Then, the patterned layer
`10 is subjected to a material removing treatment, thereby
`forming a recess 19 in the dielectric layer 18, and a contact
`Window 28,29 is provided in the dielectric layer. A conduc-
`tive layer 30 is applied filling the recess 19 and the contact
`Window 28,29, which conductive layer 30 is subsequently
`shaped into the gate structure 21 and a contact structure
`26,27 establishing an electrical contact with the surface 2 of
`the semiconductor body 1.
`
`8 Claims, 12 Drawing Sheets
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`TSMC 1109
`TSMC 1109
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`

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`US. Patent
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`Jun. 18, 2002
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`Sheet 1 0f 12
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`US 6,406,963 B2
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`US. Patent
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`Jun. 18, 2002
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`Sheet 2 0f 12
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`US. Patent
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`Jun. 18, 2002
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`Sheet 3 0f 12
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`US 6,406,963 B2
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`US. Patent
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`Jun. 18, 2002
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`Sheet 4 0f 12
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`US. Patent
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`Jun. 18, 2002
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`Sheet 5 0f 12
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`US. Patent
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`Jun. 18, 2002
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`Sheet 6 0f 12
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`US 6,406,963 B2
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`

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`US. Patent
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`Jun. 18, 2002
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`US. Patent
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`Jun. 18, 2002
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`Sheet 8 0f 12
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`US. Patent
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`Jun. 18, 2002
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`Sheet 9 0f 12
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`US 6,406,963 B2
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`US. Patent
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`Jun. 18, 2002
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`Sheet 10 0f 12
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`US. Patent
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`Jun. 18, 2002
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`Sheet 11 0f 12
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`US. Patent
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`Jun. 18, 2002
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`Sheet 12 0f 12
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`US 6,406,963 B2
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`

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`US 6,406,963 B2
`
`1
`METHOD OF MANUFACTURING A
`SEMICONDUCTOR DEVICE
`
`BACKGROUND OF THE INVENTION
`
`The invention relates to a method of manufacturing a
`semiconductor device comprising a semiconductor body
`which is provided at a surface with a transistor comprising
`a gate structure, by which method a patterned layer is
`applied defining the area of the gate structure, and a dielec-
`tric layer is applied in such a way, that the thickness of the
`dielectric layer next to the patterned layer is substantially
`equally large or larger than the height of the patterned layer,
`which dielectric layer is removed over part of its thickness
`until the patterned layer is exposed, after which the patterned
`layer is subjected to a material removing treatment, thereby
`forming a recess in the dielectric layer, and a conductive
`layer is applied filling the recess, which conductive layer is
`shaped into the gate structure.
`Such a method is known from US. Pat. No. 5,856,225.
`This method is often referred to as replacement gate tech-
`nique. In order to subsequently make electrical contact with
`the surface of the semiconductor body, conventional CMOS
`process flow steps need to be carried out, that is to say a
`contact window needs to be etched in the dielectric layer at
`the area of the planned electrical contact, which contact
`window needs to be filled by applying a further conductive
`layer, which further conductive layer needs to be shaped
`locally into a contact structure establishing the electrical
`contact with the surface of the semiconductor body.
`A disadvantage of this method is that an additional
`conductive layer is required for the provision of an addi-
`tional interconnect layer comprising the contact structure
`establishing the electrical contact with the surface of the
`semiconductor body. A further disadvantage is that after
`planarisation of the dielectric layer, a contact to the gate
`structure is to be made in the same process step as a contact
`to the semiconductor body, which latter contact requires
`etching and subsequent metal filling to a larger depth than
`the former contact.
`
`SUMMARY OF THE INVENTION
`
`It is an object inter alia of the invention to provide a
`method of manufacturing a semiconductor device of the
`kind mentioned in the opening paragraph, which method
`enables the provision of an additional interconnect layer
`without increasing the number of metal deposition steps.
`Another object of the invention is to provide a method,
`which enables the provision of a contact to the gate structure
`and a contact to the semiconductor body in the same process
`step, which latter contact requires etching and subsequent
`metal filling to a similar depth as the former contact.
`According to the invention, this object is achieved in that,
`prior to the application of the conductive layer, a contact
`window is provided in the dielectric layer, which contact
`window is filled with the conductive layer, which conductive
`layer is locally shaped into a contact structure establishing
`electrical contact with the surface of the semiconductor
`
`body.
`As the gate structure and an additional interconnect layer
`comprising the contact structure are provided from a single
`conductive layer, no additional metal deposition step is
`needed.
`
`Although only part of the patterned layer may be removed
`during the material removing treatment and replaced by the
`conductive layer, it is advantageous to remove the patterned
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`layer completely during this treatment and apply an insu-
`lating layer in the recess thus formed at the area of the gate
`structure, which insulating layer forms a gate dielectric of
`the transistor. In this way, the flexibility as regards the choice
`of materials for the gate structure and the gate dielectric is
`increased.
`In order to improve the performance of the
`transistor,
`it may be advantageous to apply a dielectric
`material with a dielectric constant higher than that of silicon
`oxide (e~4) as the gate dielectric and, hence, as the insulat-
`ing layer from which the gate dielectric is formed. In this
`respect, tantalum oxide (TazOs; e~20—25), aluminum oxide
`(A1203; e~10) or silicon nitride (Si3N4; e~7) can be applied
`to advantage, as these materials are deposited in a conformal
`and reproducible way by means of chemical vapor deposi-
`tion (CVD). The conductive layer, from which the gate
`structure of the transistor and the contact structure are
`
`is advantageously applied by depositing a layer
`formed,
`comprising a metal or a combination of metals. In contrast
`with polycrystalline silicon, which is often applied as a gate
`material, metals intrinsically have a relatively low resistance
`and do not suffer from detrimental depletion effects. In this
`respect, a low-resistance metal such as aluminum, tungsten,
`copper or molybdenum can be advantageously applied. If a
`metal or a combination of metals is used, the conductive
`layer is preferably applied as a double-layer consisting of a
`layer composed of the metal or the combination of metals on
`top of a layer acting as adhesion layer, barrier layer, or
`adhesion layer and barrier layer. In this respect, titanium (Ti)
`or tantalum (Ta) may be applied as adhesion layer and
`titanium nitride (TiN), tantalum nitride (TaN) or titanium
`tungsten (TiW) as barrier layer.
`In order to increase the compactness of the semiconductor
`device, the conductive layer, which fills the recess at the area
`of the gate structure and the contact window at the area of
`the contact structure, is advantageously subjected to a mask-
`less material removing treatment until the conductive layer
`overlying the dielectric layer is removed. In this way the
`gate structure and the contact structure are fully recessed in
`the dielectric layer, which is characteristic of a damascene
`process. The above mentioned maskless removal of the
`conductive layer is preferably accomplished by means of
`chemical-mechanical polishing (CMP). A subsequent mask-
`less removal of the insulating layer is not required, but can
`be beneficial if the insulating layer involves a high dielectric
`constant material.
`
`In order to suppress e.g. short-channel effects such as
`punch-though and short-channel
`threshold-voltage
`reduction, which effects start to play an important role in the
`device behavior of MOS transistors with channel lengths
`decreasing below 2 pm, impurities can be advantageously
`introduced via the recess at the area of the gate structure into
`the semiconductor body in a self-registered way by using the
`dielectric layer as a mask. The impurities are advantageously
`introduced into the semiconductor body by means of ion
`implantation, which in general includes a high-temperature
`anneal, which is used to restore the damage in the crystal
`lattice caused by the implantation and to activate the
`as-implanted impurities.
`In order to further increase the compactness of the semi-
`conductor device, the contact structure is advantageously
`applied covering at least part of an oxide field insulating
`region, which is provided at the surface of the semiconduc-
`tor body to separate active regions in the semiconductor
`body. Such a contact structure is also referred to as a
`borderless contact In certain circumstances it may be advan-
`tageous that the contact structure establishes an electrical
`contact between active regions separated from each other by
`
`

`

`US 6,406,963 B2
`
`3
`an oxide field insulating region. In case of a CMOS inverter,
`an electrical contact needs to be established between the
`
`drain of an NMOS transistor and the drain of an adjacent
`PMOS transistor.
`
`The contact window may be provided in the dielectric
`layer by locally etching this layer on the basis of a fixed time
`or using end-point detection. However, in order to counter-
`act serious etching of the underlying oxide field insulating
`region, the surface of the semiconductor body at the area of
`the contact structure is advantageously provided with an
`etch stop layer prior to the application of the dielectric layer,
`which etch stop layer is composed of a material with respect
`to which the dielectric layer is selectively etchable. In this
`respect, it is advantageous to apply silicon nitride as the etch
`stop layer and silicon oxide as the dielectric layer.
`Alternatively, aluminum oxide can be used instead of silicon
`nitride and/or PSG (phosphosilicate glass) or BPSG
`(borophosphosilicate glass) instead of silicon oxide.
`The patterned layer defining the area of the gate structure
`of the transistor may be applied composed of, for example,
`silicon nitride or aluminum oxide. However, in order to
`match the process flow to conventional CMOS processing,
`the patterned layer is advantageously applied comprising a
`semiconductor material.
`
`The patterned layer may be advantageously applied by
`depositing and patterning a layer comprising a silicon ger-
`manium alloy. The layer may be composed of a silicon
`germanium alloy, which is given by the chemical formula
`GexSi(1_x), or a silicon germanium alloy with a small per-
`centage of carbon, which is given by the chemical formula
`GexSi(1_x_y)Cy. In these formulas x represents the fraction of
`germanium lying in the range between about 0.1 and 1, y the
`fraction of carbon lying in the range between about 0.001
`and 0.05, and (1—x) respectively (1—x—y)
`the fraction of
`silicon. When subjected to a wet chemical etching treatment
`in e.g. a hot, concentrated sulphuric acid (H2804) solution,
`such a silicon germanium alloy etches about 10 times or
`more faster than silicon.
`One embodiment of the method in accordance with the
`
`invention, in which silicon is advantageously used as the
`semiconductor material,
`is characterized in that
`the pat-
`terned layer is applied by depositing and patterning a layer
`comprising silicon, and the dielectric layer is applied, after
`which the patterned layer is subjected to the material remov-
`ing treatment wherein the silicon of the patterned layer is
`etched away, thereby forming the recess at the area of the
`gate structure, after which the dielectric layer is provided
`with the contact window at the area of the contact structure.
`Another embodiment of the method in accordance with
`
`the invention, in which silicon is advantageously used as the
`semiconductor material, is characterized in that, prior to the
`application of the patterned layer, a masking layer is applied
`to the surface of the semiconductor body, which semicon-
`ductor body is a silicon body,
`the masking layer being
`composed of a material with respect to which silicon is
`selectively etchable, after which the patterned layer is
`applied by depositing and patterning a layer comprising
`silicon, and the dielectric layer is applied, which dielectric
`layer is provided with the contact window at the area of the
`contact structure, which contact window exposes the mask-
`ing layer, after which the patterned layer is subjected to the
`material removing treatment wherein the silicon of the
`patterned layer is etched away, thereby forming the recess at
`the area of the gate structure. The masking layer is applied
`in order to protect the surface of the silicon body at the area
`of the contact structure from being attacked by the etching
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`mixture applied for etching of the silicon present in the
`patterned layer.
`In this respect, silicon oxide may,
`for
`example, be advantageously applied as the masking layer,
`although other materials may also be used.
`The dielectric layer is advantageously removed over part
`of its thickness by means of chemical-mechanical polishing.
`Experimentally, it is observed that the moment of stopping
`the chemical-mechanical polishing (CMP) of the dielectric
`layer is rather critical
`if the patterned layer comprises
`semiconductor material. If the CMP process is stopped too
`early, remainders of the dielectric layer are left on the
`patterned layer which hinder the subsequent removal of the
`patterned layer or part of the patterned layer. If the CMP
`process is carried on too long, the definition of the height of
`the planned gate structure is adversely affected. In order to
`improve the height definition of the process, it is advanta-
`geous to apply the patterned layer as a double-layer with a
`first sub-layer comprising the semiconductor material with
`on top a second sub-layer composed of a material having a
`larger resistance towards the removal of the dielectric layer
`than the semiconductor material and being selectively etch-
`able with respect to the dielectric layer. Hence, the second
`sub-layer will act as etch stop layer during the removal of the
`dielectric layer. In this respect, it is advantageous to apply
`silicon nitride as the second sub-layer and silicon oxide as
`the dielectric layer. Alternatively, aluminum oxide can be
`used instead of silicon nitride and/or PSG (phosphosilicate
`glass) or BPSG (borophosphosilicate glass) instead of sili-
`con oxide.
`
`After shaping the conductive layer into the gate structure
`and the contact structure, a further dielectric layer is applied,
`in which further dielectric layer vias are etched exposing at
`least part of the gate structure and at least part of the contact
`structure, which vias are filled by applying a further con-
`ductive layer. By using the method in accordance with the
`invention,
`the vias exposing the gate structure and the
`contact structure are of a similar depth, which facilitates
`etching and conformal filling of these vias.
`These and other aspects of the invention will be apparent
`from and elucidated with reference to the embodiments
`
`described hereinafter and shown in the drawings.
`BRIEF DESCRIPTION OF THE DRAWING
`
`In the drawings:
`FIGS. 1 to 13 show in diagrammatic cross-sectional views
`successive stages in the manufacture of a semiconductor
`device, using a first embodiment of the method in accor-
`dance with the invention, FIGS. 14 to 20 show in diagram-
`matic cross-sectional views successive stages in the manu-
`facture of a semiconductor device, using a second
`embodiment of the method in accordance with the invention.
`
`Although the invention is illustrated hereinafter on the
`basis of a MOS transistor, it will be evident to those skilled
`in the art that the invention may also be advantageously
`applied in the manufacture of a MOS transistor with a
`floating gate, also referred to as floating gate transistor, or of
`CMOS and BICMOS integrated circuits known per se.
`FIGS. 1 to 13 show in diagrammatic cross-sectional views
`successive stages in the manufacture of a semiconductor
`device, using a first embodiment of the method in accor-
`dance with the invention.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`With reference to FIG. 1, a semiconductor body 1 of a first
`conductivity type, in the present example a silicon body of,
`
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`5
`for example, p-type conductivity, is provided at a surface 2
`with relatively thick oxide field insulating regions 3, which
`are at least partly recessed in the semiconductor body 1 and
`which define an active region 4 in which a transistor, in the
`present example an NMOS transistor, is to be manufactured.
`Besides the active region 4 an adjacent active region 5 is
`shown, in which adjacent active region 5 a transistor, in the
`present example a PMOS transistor, is to be manufactured.
`The adjacent active region 5 has been included in order to
`illustrate the formation of a contact structure establishing an
`electrical contact between the drain of an NMOS transistor
`and the drain of a PMOS transistor in a CMOS inverter. It
`
`should be noted that masks needed to screen the adjacent
`active region 5 during processing of the active region 4, for
`example during implantation of the active region 4, and vice
`versa will not be shown in the figures nor mentioned in the
`description. For a person skilled in the art it will be clear that
`such masks are used in several stages of the process.
`The thick oxide field insulating regions 3 are formed in a
`usual way by means of LOCOS (LOCal Oxidation of
`Silicon) or by means of STI (Shallow Trench Isolation). The
`adjacent active region 5 is provided with a well 6 of a
`second, opposite conductivity type, in the present example
`n-type, by means of ion implantation of a dose of, for
`example, phosphorus or arsenic, which ion implantation
`may be advantageously carried out after having provided the
`surface 2 of the semiconductor body 1 with a sacrificial
`silicon oxide layer (not shown) by means of, for example,
`thermal oxidation. Optionally, the active region 4 may be
`provided with a well of the first conductivity type, in the
`present example p-type. Subsequently, the surface 2 of the
`semiconductor body 1 is provided with a layer 7 composed
`of, for example, silicon oxide, which is covered by a
`patterned layer 10 defining the area of a gate structure to be
`provided in a later stage of the process. In the present
`example, the patterned layer 10 is obtained by depositing a
`double-layer consisting of a first sub-layer 8 of, for example,
`polycrystalline silicon, and, on top thereof, a second sub-
`layer 9 composed of, for example silicon nitride, and pat-
`terning the double-layer e.g. in a usual photolithographic
`way. Any other suitable material such as, for example,
`aluminum oxide or a combination of materials can be used
`
`instead of silicon nitride. Instead of polycrystalline silicon,
`another semiconductor material such as, for example, amor-
`phous silicon, GexSi(1_x) or GexSi(1_x_y)Cy can be used, with
`x representing the fraction of germanium roughly lying in
`the range between 0.1 and 1, y the fraction of carbon lying
`in the range between about 0.001 and 0.05, and (1—x) and
`(1—x—y) the fraction of silicon. It is to be noted that the
`patterned layer 10 may be a single layer as well, composed
`of, for example, silicon nitride or aluminum oxide or a
`semiconductor material such as, for example, polycrystal-
`line silicon, amorphous silicon, GexSi(1_x) or GexSi(1_x_y)Cy.
`After applying the patterned layer 10, source/drain exten-
`sions 1 1 of the second, opposite conductivity type, in the
`present example n-type, are formed on opposite sides of the
`patterned layer 10 by means of a self-aligned implantation of
`a relatively light dose of,
`for example, phosphorus or
`arsenic, using the patterned layer 10 together with the oxide
`field insulating regions 3 as a mask. In an analogous way, the
`adjacent active region 5 is provided with source/drain exten-
`sions 12 of the first conductivity type, in the present example
`p-type (source extension not shown).
`Subsequently,
`the patterned layer 10 is provided with
`sidewall spacers 13 e.g. in a known way, for example, by
`means of deposition and anisotropic etch-back of a silicon
`oxide layer (FIG. 2). After formation of the sidewall spacers
`
`10
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`13, a highly-doped source zone 14 and a highly-doped drain
`zone 15 of the second conductivity type, in the present
`example n-type, are formed on opposite sides of the sidewall
`spacers 13 by means of a self-aligned implantation of a
`heavier dose of, for example, phosphorus or arsenic, using
`the oxide field insulating regions 3 together with the pat-
`terned layer 10 and the sidewall spacers 13 as a mask. In an
`analogous way, the adjacent active region 5 is provided with
`a highly-doped source zone (not shown) and a highly-doped
`drain zone 16 of the first conductivity type, in the present
`example p-type.
`With reference to FIG. 3, an etch stop layer 17, in the
`present example composed of silicon nitride, and a relatively
`thick dielectric layer 18, in the present example composed of
`silicon oxide, are applied,
`the dielectric layer 18 being
`applied in such a way, that the thickness of the dielectric
`layer 18 next
`to the patterned layer 10 is substantially
`equally large or larger than the height of the patterned layer
`10. Alternatively, aluminum oxide can be used instead of
`silicon nitride and/or BPSG (borophosphosilicate glass) or
`PSG (phosphosilicate glass) can be used instead of silicon
`oxide. The etch stop layer 17 needs to be composed of a
`material with respect to which the dielectric layer 18 is
`selectively etchable, in order to counteract serious etching of
`the oxide field insulating regions 3.
`Subsequently, the dielectric layer 18 is removed over part
`of its thickness until the patterned layer 10 is exposed (FIG.
`4). This can be accomplished by means of, for example,
`chemical-mechanical polishing (CMP) e. g. using a commer-
`cially available slurry. During the CMP treatment, the sec-
`ond sub-layer 9, in the present example composed of silicon
`nitride, will act as a stop layer.
`In a next step (FIG. 5), the second sub-layer 9, which is
`composed of silicon nitride in the present example,
`is
`removed selectively with respect to the dielectric layer 18
`and the sidewall spacers 13, both composed of silicon oxide
`in the present example, by means of, for example, wet
`etching using a mixture of, for example, hot phosphoric acid
`and sulphuric acid. In this way the dielectric layer 18 is
`provided with a recess 19 in which the first sub-layer 8 is
`exposed.
`With reference to FIG. 6, the first sub-layer 8 and the layer
`7 are removed in two separate etching steps. The first
`sub-layer 8, in the present example composed of polycrys-
`talline silicon, can be removed selectively by means of wet
`etching using, for example, a hot KOH solution or by means
`of plasma etching with, for example, a HBr/Cl2 mixture. The
`layer 7, in the present example composed of silicon oxide,
`can be removed by means of wet etching using HF. It should
`be noted that, alternatively, the layer 7 may be preserved in
`the recess 19 and used as a gate dielectric of the transistor.
`The semiconductor body 1 is provided with an impurity
`region 20 of the first conductivity type,
`in the present
`example p-type, by introducing p-type impurities such as,
`for example, boron (B), via the recess 19 at the area of the
`gate structure 21 into the semiconductor body 1 in a self-
`registered way by using the dielectric layer 18 as a mask.
`The impurity region 20 can be applied as, for example, a
`shallow region to suppress short-channel threshold-voltage
`reduction and/or a deeper region to suppress punch-through
`between the extended source zone 14,11 and the extended
`drain zone 15,11 of the NMOS transistor. The impurities are
`advantageously introduced into the semiconductor body 1
`by means of ion implantation as depicted by arrows 22. In
`this respect, boron may be implanted at an energy ranging
`from about 20 to 60 keV and a dose of about 2.1013
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`7
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`atoms/cm2. It is understood by those skilled in the art that
`phosphorus (P) ions or arsenic
`ions may be implanted
`in the PMOS transistor for similar reasons. For example,
`phosphorus may be implanted at an energy ranging from
`about 100 to 130 keV and a dose of about 2.1013 atoms/cm2,
`whereas arsenic may be implanted at an energy ranging from
`about 180 to 240 keV and a dose of about 2.1013 atoms/cm2.
`The implantation may be carried out substantially perpen-
`dicularly to the surface 2 of the semiconductor body 1.
`However, in order to counteract channeling of the impurities
`along crystal directions and planes,
`it is advantageous to
`perform the implantation at a small angle of a few, for
`example seven, degrees with respect to the normal to the
`surface 2 of the semiconductor body 1 by tilting the semi-
`conductor body 1 before implantation. It is to be noted that
`the shallow region for the suppression of short-channel
`threshold-voltage reduction and the deeper region for punch-
`through suppression may be formed in two implantation
`steps carried out at different energies, or simultaneously in
`one implantation step at a single energy. In connection with
`the ion implantation, a high-temperature anneal is carried
`out at a temperature as high as about 900° C. in order to
`restore the damage in the crystal
`lattice caused by the
`implantation and to activate the as-implanted impurities.
`As shown in FIG. 7, an insulating layer 23 is applied to
`all exposed surfaces, providing a gate dielectric 24 of the
`transistor. The insulating layer 23 may be composed of
`silicon oxide, however, a dielectric material with a dielectric
`constant higher than that of silicon oxide, such as tantalum
`oxide, aluminum oxide or silicon nitride may be more
`favorable. If silicon oxide is to be applied for the gate
`dielectric 24, it may be obtained by means of, for example,
`chemical vapor deposition or thermal oxidation of silicon.
`The high dielectric constant materials tantalum oxide, alu-
`minum oxide and silicon nitride can be applied, for example,
`by means of chemical vapor deposition (CVD).
`It is to be noted that the above-mentioned ion implanta-
`tion for punch-through suppression and/or suppression of
`short-channel threshold voltage reduction may alternatively
`be carried out before the removal of the layer 7 or after the
`application of the insulating layer 23. It is known that a thin
`layer composed of, for example, silicon oxide, which is
`present at
`the surface of the semiconductor body, may
`improve the characteristics of ion implantation. However, if
`the insulating layer 23 is composed of a dielectric material
`with a high dielectric constant, the high-temperature anneal
`associated with the ion implantation may degrade the dielec-
`tric properties of the material applied if the anneal is carried
`out afterwards.
`
`In a next step (FIG. 8), a resist mask 25 is applied to the
`semiconductor body 1, which resist mask 25 exposes the
`insulating layer 23 at the area of contact structures 26,27 to
`be provided in a later stage of the process. It should be noted
`that a thin metal layer (not shown) can be advantageously
`applied prior to the application of the resist mask 25, in order
`to protect
`the gate dielectric 24 against contamination.
`Subsequently, contact windows 28,29 are etched in the
`insulating layer 23 and the dielectric layer 18 at the area of
`the contact structures 26,27, which contact windows 28,29
`expose the etch stop layer 17. Etching of the dielectric layer
`18, in the present example composed of silicon oxide, may
`be carried out by means of dry etching in, for example, a
`CO/C4F8 gas mixture. Since the dielectric layer 18, in the
`present example composed of silicon oxide, etches much
`faster in this mixture than the etch stop layer 17, in the
`present example composed of silicon nitride, the etch pro-
`cess will stop the moment the etch stop layer 17 is reached.
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`Subsequently, the etch stop layer 17 and the layer 7 in the
`contact windows 28,29 are removed, thereby exposing the
`surface 2 of the semiconductor body 1 and the oxide field
`insulating regions 3 at the area of the contact structures
`26,27, the result of which is shown in FIG. 9.
`With reference to FIG. 10, a conductive layer 30 is applied
`to the semiconductor body 1 in a usual way, thereby filling
`the recess 19 at the area of the gate structure 21 and the
`contact windows 28,29 at the area of the contact structures
`26,27. Polycrystalline silicon, amorphous silicon, GexSi1_x
`or GexSi1_x_yCy may be used for the conductive layer 30,
`with x being the fraction of ger