(12) United States Patent
`(10) Patent N0.:
`US 6,228,777 B1
`
`Arafa et al.
`(45) Date of Patent:
`May 8, 2001
`
`U5006228777B1
`
`(54)
`
`INTEGRATED CIRCUIT WITH
`BORDERLESS CONTACTS
`
`(75)
`
`Inventors: Mohamed Arafa, Hillsboro; Scott
`Thompson’ Portland’ both of OR (Us)
`Intel Corporation, Santa Clara, CA
`US
`(
`)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(73) Assignee:
`
`( * ) Notice:
`
`(21) Appl’ No” 09/328’190
`(22)
`Filed:
`Jun, 8, 1999
`
`7
`
`................................................. .. H01L 21/302
`Int. Cl.
`(51)
`........................................... .. 438/740; 438/740
`(52) US. Cl.
`(58) Field of Search ................................... .. 438/664, 666,
`438/683, 674, 704, 740, 970, 634, 675,
`655, 221, 437, 291, 910
`_
`REfeI‘ences CltEd
`
`(56)
`
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`4,557,036
`4,650,696
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`/
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`) ‘
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`~
`.
`(List continued on next page.)
`Primary Examiner—David Nelms
`Assistant Examiner—David Nhu
`(74) Attorney, Agent, or Firm—Mark Seeley
`
`ABSTRACT
`(57)
`An integrated Circuit comprising a conductive region formed
`.
`.
`.
`on a semiconductor substrate, a s111cate glass layer formed
`.
`.
`0“ theFonduCtlve reglm an an “Ch SFOPJayer formed 0“
`the s111cate glass layer. The integrated c1rcuit also includes a
`borderless contact that is coupled to the conductiVe region
`
`10 Claims, 3 Drawing Sheets
`
`
`
`TSMC 1108
`TSMC 1108
`
`

`

`US 6,228,777 B1
`
`Page 2
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`OTHER PUBLICATIONS
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`
`V. Jain, D. Praminik, “Impact of Inter Metal OXide Struc-
`tures and Nitride Passivation on Hot Carrier Reliability of
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`
`(VMIC), Jun. 1992, pp. 417—419.
`N. Shimoyama, K. Machida, K. Murase, T. Tsuchiya,
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`A. Hamada, T. Furusawa, E. Takeda, “A New Aspect on
`Mechanical Strress Effects in Scaled MOS Devices”, IEEE
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`Papers, 6/90 p.
`M. Noyori, T. Ishihara, H. Higuchi “Secondary Slow Trap-
`ping—A New Moisture Induced Instability Phenomenon in
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`Reliability 1982, p.
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`J. Mitsuhashi, H. Muto, Y. Ohno, T. Matsukawa, “Effect of
`P—SiN Passivation Layer on Time—Dependent Dielectric
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`K.P. MacWilliams, L.E. Lowry, D.J. Swanson, J. Scarpulla,
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`Digest of Technical Papers, Jun. 1992, pp. 100—101.
`
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`and Hydrogen Effects on Hot Carrier Injection, IEE—IEDM
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`Y. Ohno, A. Ohsaki, T. Kaneoka,
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`
`W. Abadeer, W. Tonti, et al, Bias Temperature Reliability of
`N+ and P+ Polysilicon Gates NMOSFETs and POMSFETs,
`IEEE 31st Annual Proceedings Reliability, 8/93, pp.
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`
`K.O. Jeppson, C.M. Svensson “Negative bias stress of MOS
`devices at high electric fields and degradation of MNOS
`devices” Journal of Applied Physics V48, #5, 5/77 pp.
`2004—2014.
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`R.T. Fuller, W.R. Richards, Y. Nissan—Cohen, J .C. Tsang,
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`
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`
`Stanley Wolf, “Silicon Processor the VLSI Era”, vol. 1, pp.
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`
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`392—396.
`
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`Induced by Secondary Slow Trapping in Scaled CMOS
`Devices”, IEEE Transactions Reliability, 8/83 pp. 323—329.
`
`* cited by examiner
`
`

`

`US. Patent
`
`May 8, 2001
`
`Sheet 1 0f3
`
`US 6,228,777 B1
`
`102
`
`108
`
`103
`
` .f.lllllll’ll),'._
`
`
`FIGURE 2
`
`

`

`US. Patent
`
`May 8, 2001
`
`Sheet 2 0f3
`
`US 6,228,777 B1
`
`
`'
`
` III/111111;f_.
`
`FIGURE 3
`
`

`

`US. Patent
`
`May 8, 2001
`
`Sheet 3 0f 3
`
`US 6,228,777 B1
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`.\\\\\ |m\
`
`V
`
`‘\\\\“\\\\\‘\
`V-
`.
`
`_ \
`
`FIGURE 4
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`

`

`US 6,228,777 B1
`
`1
`INTEGRATED CIRCUIT WITH
`BORDERLESS CONTACTS
`
`FIELD OF THE INVENTION
`
`The present invention relates to integrated circuits and a
`method for making them.
`BACKGROUND OF THE INVENTION
`
`To continue adding transistors to integrated circuits with-
`out significantly increasing die sizes, the distance between
`transistors and other devices may have to be reduced. The
`need to reduce the distance between devices may require
`reducing the width of the landing area for the contacts. As
`a result, when contact is made to the landing area, part of the
`contact may extend laterally over the isolation structure,
`forming a borderless contact. To prevent the contact etch
`step from etching into the isolation structure, an etch stop
`layer may be formed on the surface of the device prior to
`performing the contact etch. Such a layer may comprise
`silicon nitride.
`In conventional devices, which do not include borderless
`contacts, an interlayer dielectric (“ILD”) that includes a
`silicon dioxide, PSG, or BPSG layer is frequently formed on
`a silicide. The presence of that layer, and the processes used
`to deposit and etch it, give the resulting device certain
`properties. When a silicon nitride layer is formed between
`the silicide and such an ILD layer, for enabling borderless
`contacts, the silicon nitride layer (and processes used to form
`and etch it) may cause the resulting device’s characteristics
`to differ from those of a device that lacks such a layer.
`Some of those changes may be undesirable. For example,
`adding such a silicon nitride layer may introduce certain
`stresses that can degrade the saturation current or cause the
`device’s threshold voltage to shift. Depositing a silicon
`nitride layer directly on top of a silicide may increase the
`silicide’s sheet resistance and adversely affect the way the
`silicide agglomerates. When using a plasma process to
`remove silicon nitride, different charging characteristics
`may result, when compared to those that result when etching
`the ILD layer. Also, when such a silicon nitride etch stop
`layer is deposited using a hot wall chemical vapor deposition
`(“CVD”) process, significant portions of the silicide may
`oxidize.
`
`Accordingly, there is a need for a method for making a
`device having borderless contacts that mitigates against the
`type of device characteristic changes and performance deg-
`radation that the silicon nitride etch stop layer may cause. In
`particular, there is a need for a device that is not adversely
`affected by stresses, unwanted changes to silicide properties,
`or undesirable charging effects, which may result from
`forming such a layer. There is also a need for a process for
`making a device that includes such a silicon nitride layer that
`permits use of a hot wall CVD process to deposit such a
`layer, without causing significant oxidation of the silicide.
`SUMMARY OF THE INVENTION
`
`The present invention covers an integrated circuit com-
`prising a conductive region formed on a semiconductor
`substrate, a silicate glass layer formed on the conductive
`region, and an etch stop layer formed on the silicate glass
`layer. The integrated circuit also includes a borderless con-
`tact that is coupled to the conductive region. The present
`invention further covers a method for forming such an
`integrated circuit.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1. is an illustration of a cross-section of a device that
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`2
`FIG. 2 is an illustration of a cross-section of the device
`shown in FIG. 1 that includes a silicate glass layer formed
`on a silicide.
`FIG. 3 is an illustration of a cross-section of the device
`shown in FIG. 2 that includes an etch stop layer formed on
`the silicate glass layer.
`FIG. 4 is an illustration of a cross-section representing an
`embodiment of the integrated circuit of the present inven-
`tion.
`
`DETAILED DESCRIPTION OF THE PRESENT
`INVENTION
`
`An improved integrated circuit and method for making it
`are described. FIG. 1 illustrates a device 100 that may be
`made using conventional process steps for forming an
`integrated circuit. Device 100 represents a structure that may
`be used to form an MOS transistor, and includes well 149
`upon which is formed gate oxide 101 and gate 102. As
`shown, gate 102 comprises polysilicon 146 and silicide 148.
`On the sides of gate 102 is oxide 103, which serves as a
`stress buffer for the nitride layer used to form nitride spacers
`104. On either side of spacers 104 are conductive regions
`130 and 131, which are formed on well 149. In this embodi-
`ment of the present invention, conductive regions 130 and
`131 comprise suicides 105 and 106, which rest on diffused
`regions 107 and 108, respectively. Also shown in FIG. 1 is
`shallow trench isolation structure 109 formed adjacent to
`well 149.
`
`Well 149 may be a heavily doped (e.g., p+ or n+) p-well
`or n-well, depending upon whether the device formed above
`well 149 is an n-MOS or p-MOS device. Gate oxide 101,
`gate 102, oxide 103, nitride spacers 104, suicides 105 and
`106 and diffused regions 107 and 108 may be made from
`materials conventionally used to form such structures using
`conventional process steps, as is well understood by those
`skilled in the art.
`
`Although conductive regions 130 and 131 shown in FIG.
`1 include suicides 105 and 106 formed on diffused regions
`107 and 108, any conductive structure or material that may
`receive a borderless contact may comprise a conductive
`region, as that term is used herein. The term “conductive
`region” is thus not intended to be limited to the structure
`shown in FIG. 1.
`
`Shallow trench isolation structure 109 may comprise a
`combination of grown and deposited oxide and may be
`formed in numerous ways, such as using the process
`described in US. Pat. No. 5,719,085, assigned to this
`application’s assignee.
`When making one embodiment of the integrated circuit of
`the present invention, relatively thin silicate glass layer 111
`is formed on the surface of device 100, as shown in FIG. 2.
`Preferably, layer 111 is between about 100 and about 1,000
`angstroms thick, and more preferably between about 200
`and about 400 angstroms thick.
`Silicate glass layer 111 may comprise an undoped silicon
`dioxide, phosphosilicate glass (PSG) or borophosphosilicate
`glass (BSPG) layer. Such a layer may be formed on the
`surface of device 100 by applying a conventional plasma
`enhanced CVD (PECVD), atmospheric pressure CVD
`(APCVD) or
`low pressure CVD (LPCVD) process.
`Preferably, layer 111 comprises silicon dioxide deposited
`onto the surface of device 100 using a PECVD process,
`which employs conventional equipment and materials, e.g.,
`silane, tetraethylorthosilicate (TEOS), or some other silicon
`source.
`
`may be formed when making an embodiment of the inte-
`grated circuit of the present invention.
`
`After forming silicate glass layer 111, etch stop layer 120
`is formed on silicate glass layer 111, as shown in FIG. 3.
`
`

`

`US 6,228,777 B1
`
`3
`Layer 120 preferably comprises silicon nitride, which may
`be deposited onto silicate glass layer 111 using conventional
`techniques for forming a silicon nitride layer, some of which
`are described in US. Pat. No. 5,633,202, assigned to this
`application’s assignee. In this embodiment of the present
`invention, layer 120 preferably is between about 100 and
`about 1,500 angstroms thick, and more preferably between
`about 200 and about 500 angstroms thick.
`When made from silicon nitride, layer 120 may be formed
`using a hot wall LPCVD or a PECVD process. When the hot
`wall process is used, dichlorosilane and ammonia may be
`fed into the reactor at a temperature that
`is preferably
`between about 550 and about 800° C. Such a hot wall
`
`process is preferred to a PECVD process for depositing
`silicon nitride as the resulting layer should provide more
`favorable selectivity, uniformity and quality. Unlike a
`PECVD process, a LPCVD process should not produce
`undesirable charging effects. In addition, because such an
`LPCVD process is a batch process, such a process may
`provide higher throughput than a PECVD process.
`After etch stop layer 120 is deposited, ILD layer 125 is
`formed.
`ILD layer 125 may be formed from the same
`insulating material used to form silicate glass layer 111 using
`the same equipment and similar process steps, but modified
`to produce a layer that is between about 3,000 and about
`10,000 angstroms thick. Alternatively, ILD layer 125 and
`layer 111 may be formed from different materials.
`Preferably, ILD layer 125 is a PSG layer formed using a
`PECVD process that employs TEOS—although other CVD
`processes, which use other silicon sources, may be used.
`Although ILD layer 125 preferably is a PSG layer, ILD layer
`125 could instead comprise a silicon dioxide or BPSG layer
`or be formed from other materials that may provide an
`insulating function. When a PSG layer,
`the phosphorus
`source may be phosphine, diphosphide or trimethylphos-
`phide. When a BPSG layer,
`the boron source may be
`diborane or trimethylborate.
`Following deposition of ILD layer 125, that layer may be
`planarized, such as by applying a chemical mechanical
`polishing step. A layer of oxide (not shown) may then be
`deposited on top of ILD layer 125, e.g., by using TEOS in
`a PECVD process.
`After the dielectric layer or layers have been formed on
`etch stop layer 120, a three step etch may be performed to
`etch the via for the contact through ILD layer 125, etch layer
`120, and silicate glass layer 111. A single wafer,
`low
`frequency, parallel plate etcher may be used. The etch
`chemistry preferably employs Freon gases, e.g., CHF3, CF4,
`C2F6, as the active species. The etch chemistry may also
`include conventionally used amounts of argon and oxygen
`and/or nitrogen. By using an etch chemistry that has high
`etch selectivity for the material used to make ILD layer 125,
`when compared to the selectivity of silicon nitride layer 120,
`layer 120 may act as an etch stop preventing that etch step
`from reaching shallow trench isolation region 109.
`After ILD layer 125 is etched, silicon nitride layer 120 is
`etched. Silicon nitride layer 120 may be etched using the
`same equipment used to etch ILD layer 125, but employing
`an etch chemistry having a high selectivity to silicon nitride,
`when compared to the selectivity of the material used to
`make layer 111. After layer 120 is etched, silicate glass layer
`111 is etched. Silicate glass layer 111 may be etched using
`the same equipment and etch chemistry used to etch ILD
`layer 125, while modifying the process to account for the
`differences in thickness between those two layers. Although
`a three step etch process is preferred for making the via for
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`4
`the contact, a two step process may be used instead, where
`the first step etches through ILD layer 125 and the second
`step etches through both silicon nitride layer 120 and silicate
`glass layer 111.
`After the via has been etched through layers 125, 120 and
`111, borderless contact 110 is formed to make electrical
`contact to conductive region 130, e. g., by contacting silicide
`105, as shown in FIG. 4. Borderless contact 110 is formed
`by filling the via with a conductive material. As shown in
`FIG. 4, that conductive material may comprise relatively
`thin titanium and titanium nitride layers 119 and 118 and
`tungsten plug 117, which are successively deposited to fill
`the via.
`
`Forming silicate glass layer 111 between silicide 105 and
`silicon nitride layer 120 may provide a number of advan-
`tages over processes that deposit a silicon nitride layer
`directly on the silicide. Silicate glass layer 111 acts as a
`stress reliever, which should reduce the shift
`in device
`characteristics that the silicon nitride layer may otherwise
`cause. Devices that include such a layer may also show
`reduced variance in resistance in both the silicide and the
`
`contacts, and may be more reliable. In addition, the presence
`of such a silicate glass layer may decrease the amount of
`silicide degradation and adverse charging effects, which
`otherwise may result from the silicon nitride etch step.
`Forming a silicate glass layer between the silicide and the
`silicon nitride layer may thus enable selection of a silicon
`nitride etch process without having to consider the effect that
`such a process may have on silicide degradation or device
`charging.
`Another advantage of this new process is that silicon
`nitride layer 120 may be formed using a hot wall CVD
`process instead of a PECVD process, because silicon glass
`layer 111 may protect the silicide from oxygen used in such
`a process. Such a relatively high temperature hot wall
`process may produce a higher quality furnace nitride, with
`improved uniformity, than may be produced by a relatively
`low temperature PECVD process. In addition, such a hot
`wall process should not generate potentially troublesome
`charging effects that a PECVD process may produce.
`Features shown in the above referenced drawings are not
`intended to be drawn to scale, nor are they intended to be
`shown in precise positional relationship. For example, bor-
`derless contact 110 could be formed further to the right from
`the position shown in FIG. 4 and the relative thickness of
`layer 111 to layer 120 may vary from what is shown in the
`figures. Additional process steps that may be used to make
`the embodiments described above have been omitted when
`
`not useful to describe aspects of the present invention.
`Although the foregoing description has specified an inte-
`grated circuit that includes certain features, and has specified
`certain materials and process steps for making such an
`integrated circuit, those skilled in the art will appreciate that
`many modifications and substitutions may be made.
`Accordingly,
`it
`is intended that all such modifications,
`alterations, substitutions and additions be considered to fall
`within the spirit and scope of the invention as defined by the
`appended claims.
`What is claimed is:
`
`1. A method for forming an integrated circuit comprising:
`forming a conductive region on a semiconductor sub-
`strate;
`forming a silicate glass layer on the conductive region;
`forming an etch stop layer on the silicate glass layer; and
`forming a borderless contact coupled to the conductive
`region by etching through the etch stop layer,
`then
`
`

`

`US 6,228,777 B1
`
`5
`etching through the silicate glass layer to form a via,
`then filling the via with a conductive material.
`2. The method of claim 1 wherein the silicate glass layer
`comprises a silicon dioxide layer; and the etch stop layer
`comprises silicon nitride, and further comprising forming a
`phosphosilicate glass (PSG) layer on the silicon nitride
`layer.
`3. The method of claim 2 wherein the borderless contact
`
`5
`
`is formed by etching a via through the PSG layer, the silicon
`nitride layer, and the silicon dioxide layer, then filling the via
`with a conductive material.
`
`10
`
`4. The method of claim 3 wherein the silicon nitride layer
`is formed using a hot wall chemical vapor deposition
`process.
`5. The method of claim 4 wherein the via is etched
`
`the silicon nitride layer, and the
`through the PSG layer,
`silicon dioxide layer in three separate etching steps.
`6. The method of claim 5 wherein the borderless contact
`
`is formed by successively depositing in the via relatively
`thin titanium and titanium nitride layers and a relatively
`thick tungsten plug.
`7. Amethod for forming an integrated circuit comprising:
`forming a conductive region on a semiconductor sub-
`strate;
`
`forming an undoped silicon dioxide layer on the conduc-
`tive region;
`
`6
`forming a silicon nitride layer on the undoped silicon
`dioxide layer;
`forming a PSG layer on the silicon nitride layer; and
`forming a borderless contact coupled to the conductive
`region by etching through the silicon nitride layer, then
`etching through the undoped silicon dioxide layer to
`form a via,
`then filling the via with a conductive
`material.
`
`8. The method of claim 7 wherein the undoped silicon
`dioxide layer formed on the conductive region is between
`about 200 and about 400 angstroms thick, and the silicon
`nitride layer is between about 200 and about 500 angstroms
`thick.
`
`15
`
`20
`
`25
`
`9. The method of claim 8 wherein the silicon nitride layer
`is formed using a hot wall chemical vapor deposition
`process and the silicon dioxide and PSG layers are both
`formed using a plasma enhanced chemical vapor deposition
`process.
`10. The method of claim 9 further comprising etching a
`via through the PSG layer, the silicon nitride layer, and the
`silicon dioxide layer in three separate etch steps,
`then
`successively depositing in the via relatively thin titanium
`and titanium nitride layers and a relatively thick tungsten
`plug.
`
`

`

`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`CERTIFICATE OF CORRECTION
`
`PATENT NO.
`DATED
`INVENTOR(S)
`
`: 6,228,777 Bl
`: May 8, 2001
`: Arafa el a].
`
`Page 1 of l
`
`It is certified that error appears in the above-identified patent and that said Letters Patent is
`hereby corrected as shown below:
`
`Column 2
`
`Line 24, delete "suicides" and insert -- silicides —-.
`
`Line 32, delete "suicides" and insert -- silicides --.
`
`
`
`Signed and Sealed this
`
`Seventh Day of May, 2002
`
`Arresting Oflicer
`
`JAMES E. ROGAN
`Director of the United States Patent and Trademark Office
`
`