Docket No.: 079195-0566
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`PATENT
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re Application of
`Masafumi TSUTSUI, et al.
`Application No.: 12!170,191
`Filed: July 09, 2008
`
`: Customer Number: 53080
`Confirmation Number: 1644
`Group Art Unit: 2814
`Examiner: Howard Weiss
`
`For:
`
`SEMICONDUCTOR DEVICE INCLUDING MISFET HAVING INTERNAL STRESS
`FILM (as amended)
`
`AMENDMENT
`
`Mail Stop Amendment
`Commissiorler for Patents
`
`PO. Box 1450
`
`Alexandria, VA 22313-1450
`
`Sir:
`
`In response to the Office Action dated May 10, 2010, wherein a three-month shortened
`
`statutory period for response is set to expire on August 10, 2010, Applicants respectfillly request
`
`reconsideration of the above-identified application in View of the following amendments and
`
`remarks.
`
`WDC99 [9032764 .0T9195.0566
`
`TSMC 1103
`
`TSMC 1103
`
`
`
`PATENT
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re Application of
`Masafumi TSUTSUI, et al.
`Application No.: 12!170,191
`Filed: July 09, 2008
`
`: Customer Number: 53080
`Confirmation Number: 1644
`Group Art Unit: 2814
`Examiner: Howard Weiss
`
`For:
`
`SEMICONDUCTOR DEVICE INCLUDING MISFET HAVING INTERNAL STRESS
`FILM (as amended)
`
`AMENDMENT
`
`Mail Stop Amendment
`Commissiorler for Patents
`
`PO. Box 1450
`
`Alexandria, VA 22313-1450
`
`Sir:
`
`In response to the Office Action dated May 10, 2010, wherein a three-month shortened
`
`statutory period for response is set to expire on August 10, 2010, Applicants respectfillly request
`
`reconsideration of the above-identified application in View of the following amendments and
`
`remarks.
`
`WDC99 [9032764 .0T9195.0566
`
`TSMC 1103
`
`TSMC 1103
`
`
`
`Application No.: 12!] 70, 191
`
`IN THE CLAIMS:
`
`This listing ofciaims will replace all prior versions and listings ofclaims in the application
`
`Listing of Claims
`
`1-14.
`
`(Cancelled)
`
`15.
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`(Currently Amended) A semiconductor device, comprising a MISFET, wherein
`
`the MISFET includes:
`
`an active region made of a semiconductor substrate;
`
`a gate insulating film formed on the active region;
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`a gate electrode formed on the gate insulating film;
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`sourcez’drain regions formed in regions of the active region located on both sides of the
`
`gate electrode; and
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`a silicon nitride film formed over from side surfaces of the gate electrode to upper
`
`surfaces of the sourceidrain regions, wherein;
`
`the silicon nitride film is not formed on an upper surface of the gate electrode, m
`
`
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`the gate electrode protrudes upward from a surface level of parts of the silicon nitride
`
`film located at both side surfaces of the gate electrode.
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`WDC99 1903364 3791950566
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`
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`Application No.1 12f170,191
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`16.
`
`(Previously presented) The semiconductor device of claim 15, wherein
`
`the silicon nitride film is for generating a stress in a substantially parallel direction to the
`
`gate length direction in a channel region located in the active region under the gate electrode.
`
`1?.
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`(Previously presented) The semiconductor device of claim 16, wherein
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`the substantially parallel direction of the stress includes a direction tilted by an angle of
`
`less than 10 degree from a direction in which carriers move.
`
`18.
`
`(Previously presented) The semiconductor device of claim 15, wherein
`
`the silicon nitride film is directly in contact with the sourcefdrain regions,
`
`19.
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`(Previously presented) The semiconductor device of claim 15, wherein
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`the silicon nitride film is formed above the sourcefdrain regions with a thin film
`
`interposed therebetween.
`
`20.
`
`(Currently amended) The semiconductor device of claim 15, wherein
`
`the source/drain regions include lightly doped impurin regions formed in regions of the
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`active region located on both sides of the gate electrode, heavily doped impurity regions formed
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`in regions of the active region respectively extending outwardly from the lightly doped impurity
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`regions to be in contact with the lightly doped impurity regions and having a higher impurity
`
`concentration than that of the lightly doped impurity regions, and a silicide layer.
`
`21.
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`(Currently amended) The semiconductor device of claim 15, further comprising:
`
`WDC99 19032764379195.0566
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`
`
`Application No.: 12f170,191
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`a sidewall formed on the side surface of the gate electrode wherein
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`the silicon nitride film is formed over the side surfaces of the gate electrode with the
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`sidewall interposed between the silicon nitride film and the side surface of the gate electrode.
`
`22.
`
`(Previously presented) The semiconductor device of claim 15, wherein
`
`a principal surface of the semiconductor substrate is substantially a {100} plane, and
`
`the gate length direction of the gate electrode is substantially a <011> direction.
`
`23.
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`(Previously presented) The semiconductor device of claim 15, further
`
`comprising:
`
`an interlevel insulating film formed on the silicon nitride film; and
`
`a contact plug provided so as to pass through the interlevel insulating film and the silicon
`
`nitride film and to be connected to the sourcefdrain regions.
`
`24.
`
`(Currently amended) The semiconductor device of claim 15, wherein;
`
`the active region is divided by an isolation region formed in the semiconductor substrate,
`
`the silicon nitride film is formed to extend over the isolation region as well as the
`
`sourcer'drain regions.
`
`25.
`
`(Previously presented) The semiconductor device of claim 15, wherein
`
`the gate insulating film is a silicon oxide film.
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`WDC99 |90327IS—l .079 1 95.0566
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`Application No.: 12(170, l 91
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`26.
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`(Previously presented) The semiconductor device of claim 15, wherein
`
`the gate insulating film is a silicon oxynitride film.
`
`2?.
`
`(Previously presented) The semiconductor device of claim 15, wherein
`
`the gate electrode has a polysilicon film.
`
`28.
`
`(Previously presented) The semiconductor device of claim 15, wherein
`
`the gate electrode has a metal film.
`
`29.
`
`(Previously presented) The semiconductor device of claim 15, wherein
`
`the silicon nitride film is provided so as to cover at least part of at least one of the
`
`sourcefdrain regions.
`
`30.
`
`(Previously presented) The semiconductor device of claim 15, wherein
`
`the silicon nitride film covers at least respective parts of the sourcefdrain regions.
`
`31.
`
`(Previously presented) The semiconductor device of claim 15, wherein
`
`the silicon nitride film covers at least respective parts of both side surfaces of the gate
`
`electrode.
`
`32.
`
`(Previously presented) The semiconductor device of claim 15, wherein
`
`the MISFET is an nMISFET and
`
`the source/drain regions are n—type sourcefdrain regions.
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`WDC‘JQ [90327640139195.0566
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`Application No.: 131370,] 91
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`33.
`
`(Previously presented) The semiconductor device of claim 32, wherein
`
`the silicon nitride film is for generating a tensile stress in a substantially parallel direction
`
`to the gate length direction in a channel region located in the active region under the gate
`
`electrode.
`
`34.
`
`(Previously presented) The semiconductor device of claim 32, wherein
`
`the n—type sourcefdrain regions include an n-type lightly doped impurity region, an n-type
`
`heavily doped impurity region and a silicide layer.
`
`35.
`
`I
`
`(Previously presented) The semiconductor device of claim 15, wherein the silicon
`
`nitride film directly contacts with the side surfaces of the gate electrode.
`
`36.
`
`(Previously presented) The semiconductor device of claim 24, wherein a lower
`
`Surface of the isolation region is located in the semiconductor substrate and is in direct contact
`
`with the semiconductor substrate.
`
`3?.
`
`(New) The semiconductor device of claim 15, wherein
`
`an upper surface of the gate electrode is higher than an upper surface of the parts of the
`
`silicon nitride film located at both side surfaces of the gate electrode.
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`W DC99 19032764 3191910566
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`Application No.: 12f170,191
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`38.
`
`(New) The semiconductor device of claim 15, wherein
`
`the gate insulating film is formed only under a lower surface of the gate electrode.
`
`39.
`
`(New) The semiconductor device of claim 15, further comprising:
`
`a sidewall formed on the side surface of the gate electrode;
`
`an interlevel insulating film formed on the silicon nitride film;
`
`an isolation region formed in the semiconductor substrate to divide the active region; and
`
`a contact plug provided so as to pass through the interlevel insulating film and the silicon
`
`nitride film and to be connected to the sourcefdrain regions, wherein
`
`the silicon nitride film is formed over the side surfaces of the gate electrode with the
`
`sidewall interposed between the silicon nitride film and the side surface of the gate electrode and
`
`to extend over the isolation region as well as the sourcefdrain regions.
`
`WDC9'9 l903276—L0791950566
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`Application No.: 12l1?0,191
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`Status of Claims
`
`REMARKS
`
`Claims 15-39 are pending, of which claim 15 is independent.
`
`Claims 15, 20, 21 and 24 have been amended to correct informalities in the claim
`
`language and to more clearly define the claimed subject matter. Claims 32-39 have been added.
`
`Support for the amendment and the new claims is found at, for example, FIGS. 1 and 4A. Care
`
`has been taken to avoid introducing new matter.
`
`Rejection under 35 U.S.C. § 103
`
`Claims 15-21, 23-34 and 36 were rejected under 35 U.S.C. § 103(a) as being
`
`unpatentable over Xiang et al. (US 6,43 7,404) and Matsuda et a]. (US 6,870,230). Claims 22
`
`and 35 were rejected under 35 U.S.C. § 103(a) as being unpatentable over Xiang et a1. and
`
`Matsuda et al., and further in View of Tatsuta (US 5,023,676). These rejections are traversed for
`
`at least the following reasons.
`
`Applicants respectfully submit that, at a minimum, none of the cited references discloses
`
`or suggests that “the gate electrode protrudes upwardfrom a surface level ofparts ofthe silicon
`
`nitridefilm located at both side surfaces ofthe gate electrode,” as recited by amended claim 15.
`
`In the present subject matter, as shown in, for example, FIGS. 1 and 4A, the gate electrode 6a, 6b
`
`protrudes upward from a surface level of parts of the silicon nitride film 8a, 8b located at both
`
`side surfaces of the gate electrode 6a, 6b. In other words, a height of the gate electrode from the
`
`surface of the substrate is higher than a height of the silicon nitride film disposed at the sides of
`
`the gate electrode.
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`WDC9’9 [9032?6-1 0291950566
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`Application No.: 12f170,191
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`In contrast, as shown in FIG. 1 of Xiang, it is clear that the upper surface of the gate
`
`electrode 56 is at the same level as that of an upper end surface of the etch stop layer 80, 82 (Le,
`
`the alleged silicon nitride film) located at both side surfaces of the gate electrode 56. As such, in
`
`Xiang, the gate electrode 56 does not protrude from a surface level of the parts of the silicon
`
`nitride film 80, 82 located at the both side surfaces of the gate electrode 56.
`
`In Matsuda, as shown in FIG. 9A, it is also clear that the upper surface of the gate
`
`electrode 6a is at the same level as that of an upper end surface of the parts of the protective
`
`insulating film 9a (i.e., the alleged silicon nitride film) located at both side surfaces of the gate
`
`electrode 6a. As such, it is clear that Matsuda also fails to disclose or suggest that the gate
`
`electrode protrudes upward from a surface level of parts of the silicon nitride film located at both
`
`side surfaces of the gate electrode.
`
`Accordingly, it is clear that the combination of Xiang and Matsuda still fails to disclose
`
`the above identified features of amended claim 15. Further, it is also clear that the remaining
`
`cited reference does not cure the deficiencies of Xiang and Matsuda, and it would not have been
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`obvious to add these features to any combination of the cited references. Thus, Applicants
`
`submit that claim 15 and all claims dependent thereon are patentable over the cited references.
`
`New claims
`
`Since new claims 37-39 depend upon claim 15, claims 37-39 are patentable for at least
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`the same reasons as claim 15.
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`W DC99 19032?6-|.079195.0566
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`
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`Application No.: 12/170,191
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`W
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`Having fully responded to all matters raised in the Office Action, Applicants submit that
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`all claims are in condition for allowance, an indication for which is respectfully solicited. If
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`there are any outstanding issues that might be resolved by an interview or an Examiner’s
`
`amendment, the Examiner is requested to call Applicants’ attorney at the telephone number
`
`shown below.
`
`To the extent necessary, a petition for an extension of time under 37 CPR. § 1.136 is
`
`hereby made. Please charge any shortage in fees due in connectiou with the filing of this paper,
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`including extension of time fees, to Deposit Account 500417 and please credit any excess fees to
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`such deposit account.
`
`Respectfully submitted,
`
`McDERMOTT WILL & EMERY LLP
`
`Takashi Saito
`
`Limited Recognition No. L0123
`
`Please recognize our Customer No. 53080
`as our correspondence address.
`
`600 13th Street, NW.
`Washington, DC 20005-3096
`Phone: 202.756.8000 TS:MaM
`
`Facsimile: 202.756.8087
`
`Date: August 6, 2010
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`WDC99 1903276-1.0T9|95.0566
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`-10-
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