UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
`Petitioner
`
`v.
`
`GODO KAISHA IP BRIDGE 1
`Patent Owner.
`
`Case IPR2017-01842
`
`DECLARATION OF STANLEY R. SHANFIELD, PH.D.
`REGARDING U.S. PATENT NO. 7,893,501
`CLAIMS 5, 6, 12, 13, 15, 19, and 21 (Petition #2)
`
`TSMC 1102
`
`

`

`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`TABLE OF CONTENTS
`
`Page
`BACKGROUND ............................................................................................. 1 
`I. 
`LEGAL PRINCIPLES ..................................................................................... 6 
`II. 
`PERSON OF ORDINARY SKILL IN THE ART .......................................... 9 
`III. 
`IV.  TECHNOLOGY BACKGROUND ............................................................... 10 
`V.  OVERVIEW OF THE ’501 PATENT .......................................................... 22 
`A. 
`Priority Date of the ’501 Patent........................................................... 27 
`B. 
`Summary of the Prosecution History .................................................. 28 
`VI.  CLAIM CONSTRUCTION .......................................................................... 29 
`VII.  GROUNDS FOR FINDING THE CHALLENGED CLAIMS INVALID ... 29 
`A.  Ground 1: Claims 5, 6, 12, 15, 19, and 21 would have been
`obvious over Igarashi in view of Woerlee .......................................... 30 
`1. 
`Independent Claim 1 ................................................................. 30 
`2. 
`Dependent Claim 5 ................................................................... 54 
`3. 
`Dependent Claim 6 ................................................................... 62 
`4. 
`Dependent Claim 12 ................................................................. 68 
`5. 
`Dependent Claim 15 ................................................................. 72 
`6. 
`Dependent Claim 19 ................................................................. 75 
`7. 
`Dependent Claim 21 ................................................................. 78 
`Ground 2: Claim 13 would have been obvious over Igarashi in
`view of Woerlee and Hokazono .......................................................... 80 
`1. 
`Dependent Claim 13 ................................................................. 80 
`VIII.  AVAILABILITY FOR CROSS-EXAMINATION ...................................... 83 
`IX.  RIGHT TO SUPPLEMENT .......................................................................... 84 
`X. 
`JURAT ........................................................................................................... 85 
`
`
`B. 
`
`i
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`I, Stanley R. Shanfield, Ph.D., declare as follows:
`
`1. My name is Stanley R. Shanfield.
`
`I.
`
`BACKGROUND
`2.
`I am a Distinguished Member of Technical Staff and Technical
`
`Director in Advanced Hardware Development at the Charles Stark Draper
`
`Laboratory (“Draper Laboratory”) in Cambridge, Massachusetts.
`
`3.
`
`I received a B.S. in Physics from the University of California, Irvine
`
`in 1977, Phi Beta Kappa. In 1975, I received the University of California Regents
`
`Award for Outstanding Research Project for my experimental and theoretical work
`
`on rotating relativistic electron beams. Under full Energy Research and
`
`Development Administration (DOE) scholarship, I received a Ph.D. in Physics
`
`from the Massachusetts Institute of Technology in 1981.
`
`4.
`
`After receiving my doctorate degree, I worked at Spire Corporation in
`
`Bedford, Massachusetts from 1981-1984, where I served as a Staff Scientist, and
`
`later, a Senior Staff Scientist. At Spire, I developed a new method of plasma-
`
`assisted CVD epitaxial silicon for low temperature semiconductor processing. In
`
`addition, I built, operated, and characterized an ion-assisted deposition system for
`
`making semiconductor coatings.
`
`5.
`
`From 1985-1999, I worked at Raytheon Corporation. In my early
`
`years at Raytheon, I was a staff member, then Section Manager for
`
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`

`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`Semiconductors and Integrated Circuits. My work focused primarily on designs,
`
`layout and fabrication technology for CMOS silicon and MISFET GaAs integrated
`
`circuits. I developed thin film, dry etch and photolithographic processes for
`
`fabricating high frequency multi-function integrated circuits. In one major design
`
`and fabrication program, I combined high performance CMOS digital and analog
`
`devices in a family of integrated circuits designs for a phased array radar system. I
`
`was responsible for developing a power MOSFET process sequence later used in a
`
`variety of Raytheon products. From 1992-1996, I served as a Research Laboratory
`
`Manager at Raytheon, and became responsible for semiconductor materials, wafer
`
`fab, testing, and some of the IC design and layout center. I led a 90 employee
`
`organization in work related to high-performance semiconductor devices and
`
`integrated circuits, advanced measurement and modeling, and state-of-the-art
`
`CMOS wafer fabrication. I led a team that invented and implemented a major
`
`revenue-generating technology ($100 million) based on a novel semiconductor
`
`device, specifically, a pseudomorphic high electron mobility transistor.
`
`6.
`
`In 1996, I became the Manager of Semiconductor Operations at
`
`Raytheon Commercial Electronics. As Manager, I built and led a 300 employee,
`
`$60 million revenue-generating semiconductor development, commercial circuit
`
`design, and electronic module manufacturing operation. My group developed the
`
`first Iridium handset electronic modules, designed and built chips and supplied
`
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`circuit board assemblies for AT&T wireless base stations. I was heavily involved
`
`as a decision-maker in Raytheon’s acquisition of a design and wafer fab group at
`
`Texas Instruments, providing significant expert opinion on semiconductor, printed
`
`circuit board assembly and design facilities. I was involved in setting up
`
`packaging, assembly and test operations in South Korea, and was directly involved
`
`in electronics package design and characterization.
`
`7.
`
`From 1999-2001, I worked at AXSUN Technologies as part of the
`
`founding team, first as the Director of Manufacturing & Wafer Fab Technology,
`
`and later, as the Vice President of Operations. As Director of Manufacturing &
`
`Wafer Fab Technology, I led device and module manufacturing, creating a wafer
`
`fab and circuit board assembly infrastructure; my responsibilities included hiring
`
`over 70 individuals and leading production design efforts. In my role as Vice
`
`President of Operations, I designed, fabricated, and productized AXSUN’s
`
`microelectromechanical (MEM) Fabry-Perot optical filter, and managed a new
`
`generation of electronics module design. In addition, I established a process and
`
`fabrication facility in Belfast, Northern Ireland for producing thick oxide silicon-
`
`on-insulator devices. As a result of my work at AXSUN, I was awarded patents on
`
`semiconductor processing and control electronics. This company was eventually
`
`sold.
`
`3
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`I have served since 2003 at the Draper Laboratory, ultimately
`
`8.
`
`becoming a Distinguished Member of Technical Staff and Technical Director in
`
`Advanced Hardware Development. I led the Advanced Hardware Development
`
`Division (approximately 80 staff) in their work on the laboratory’s multi-chip
`
`integrated circuit and module facility. I have been the technical leader for
`
`numerous micro-electronics-related programs, typically involving integrated circuit
`
`processing technology, circuit design and layout, circuit modeling, wafer
`
`fabrication (foundry and in-house), packaging and test. For example, I developed a
`
`new concept for miniature, extremely stable frequency source chip set and led the
`
`successful design, layout, and testing efforts. I was responsible for the design,
`
`fabrication and testing of an experimental direct digital receiver system using time-
`
`of-flight telemetry. I led a study evaluating state-of-the-art memory design and
`
`fabrication technology, focusing on reduced operating power.
`
`9.
`
`I have received awards and recognition for my work, including the
`
`Draper 2010 Distinguished Performance Award and the 2010 Best Patent Award
`
`for “Systems and Methods for High Density Multi-Component Electronic
`
`Modules.”
`
`10.
`
`I have authored more than 25 journal and conference papers; my
`
`publications include numerous papers on topics relating to semiconductor
`
`processing, advanced semiconductor devices, electronic circuit design and
`
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`packaging. I have been invited to give professional talks at various conferences. In
`
`1997, I gave an invited talk on “IC Technologies for Wireless Applications Beyond
`
`2000,” and received an Author’s award for work in that area.
`
`11.
`
`I am a co-inventor of seven U.S. Patents, including U.S. Patent No. 5,
`
`223,458, entitled “Method of Manufacturing a III-V Semiconductor Device Using
`
`a Self-Biased Substrate and a Plasma Containing an Electronegative Species”
`
`(issued June 29, 1993), and U.S. Patent No. 5,880,483, entitled “Semiconductor
`
`Devices” (issued March 9, 1999).
`
`12. A copy of my curriculum vitae is attached as Appendix A.
`
`13.
`
`I have reviewed the specification and claims of U.S. Patent No.
`
`7,893,501 (the “’501 patent”; Ex-1101). I have been informed that the ’501 patent
`
`claims priority to Application No. 11/730,988, filed on April 5, 2007, now U.S.
`
`Patent No. 7,417,289, which is a continuation of Application No. 10/859,219, filed
`
`on June 3, 2004, now U.S. Patent No. 7,205,615.
`
`14.
`
`I have also reviewed the following references, all of which I
`
`understand to be prior art to the ’501 patent:
`
` U.S. Patent Publication No. 2002/0145156 to Igarashi et al. (“Igarashi,”
`Ex-1104).
`
` U.S. Patent No. 6,406,963 to Woerlee et al. (“Woerlee,” Ex-1109).
`
` U.S. 2002/0000611 (“Hokazono,” Ex-1107).
`
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`In addition to the documents listed above, I have also reviewed the
`
`15.
`
`file history of the ’501 patent and all of the documents listed in Petitioner’s List of
`
`Exhibits in the accompanying petition.
`
`16.
`
`I am being compensated at my normal consulting rate for my work.
`
`17. My compensation is not dependent on and in no way affects the
`
`substance of my statements in this Declaration.
`
`18.
`
`I have no financial interest in the Petitioner. I similarly have no
`
`financial interest in the ’501 patent.
`
`II. LEGAL PRINCIPLES
`19.
`I am not an attorney. For the purposes of this declaration, I have been
`
`informed about certain aspects of the law that are relevant to my opinions. My
`
`understanding of the law was provided to me by Petitioner’s attorneys.
`
`20.
`
`I understand that prior art to the ’501 patent includes patents and
`
`printed publications in the relevant art that predate the priority date of the alleged
`
`invention recited in the ’501 patent. I have applied the date of June 16, 2003, the
`
`filing date of the foreign application to which the ’501 patent claims priority, as the
`
`priority date, although the ’501 patent may actually not be entitled to such an early
`
`priority date.
`
`21.
`
`I understand that a claim is unpatentable if it would have been obvious
`
`to a person of ordinary skill in the art at the time the alleged invention was made. I
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`understand that a claim could have been obvious from a single prior art reference
`
`or from a combination of two or more prior art references.
`
`22.
`
`I understand that an obviousness analysis requires an understanding of
`
`the scope and content of the prior art, any differences between the alleged
`
`invention and the prior art, and the level of ordinary skill in evaluating the
`
`pertinent art.
`
`23.
`
`I further understand that certain factors may support or rebut the
`
`obviousness of a claim. I understand that such secondary considerations include,
`
`among other things, commercial success of the patented invention, skepticism of
`
`those having ordinary skill in the art at the time of invention, unexpected results of
`
`the invention, any long-felt but unsolved need in the art that was satisfied by the
`
`alleged invention, the failure of others to make the alleged invention, praise of the
`
`alleged invention by those having ordinary skill in the art, and copying of the
`
`alleged invention by others in the field. I understand that there must be a nexus,
`
`that is, a connection, between any such secondary considerations and the alleged
`
`invention. I also understand that contemporaneous and independent invention by
`
`others is a secondary consideration tending to show obviousness.
`
`24.
`
`I further understand that a claim would have been obvious if it unites
`
`old elements with no change to their respective functions, or alters prior art by
`
`mere substitution of one element for another known in the field, and that
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`combination yields predictable results. Also, I understand that obviousness does
`
`not require physical combination/bodily incorporation, but rather consideration of
`
`what the combined teachings would have suggested to persons of ordinary skill in
`
`the art at the time of the alleged invention.
`
`25. While it may be helpful to identify a reason for this combination, I
`
`understand that there is no rigid requirement of finding an express teaching,
`
`suggestion, or motivation to combine within the references. When a product is
`
`available, design incentives and other market forces can prompt variations of it,
`
`either in the same field or a different one. If a person of ordinary skill in the art
`
`can implement a predictable variation, obviousness likely bars its patentability. For
`
`the same reason, if a technique has been used to improve one device and a person
`
`of ordinary skill in the art would recognize that it would improve similar devices in
`
`the same way, using the technique would have been obvious. I understand that a
`
`claim would have been obvious if a person of ordinary skill in the art would have
`
`had reason to combine multiple prior art references or add missing features to
`
`reproduce the alleged invention recited in the claims.
`
`26.
`
`I am not aware of any allegations by the named inventors of the ’501
`
`patent or any assignee of the ’501 patent that any secondary considerations tend to
`
`rebut the obviousness of any claim of the ’501 patent discussed in this declaration.
`
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`I understand that in considering obviousness, it is important not to
`
`27.
`
`determine obviousness using the benefit of hindsight derived from the patent being
`
`considered.
`
`28.
`
`I understand that other challenges to the validity of a patent, including
`
`patent ineligibility, enablement, written description, and definiteness, cannot be
`
`raised in IPR proceedings before the Board to challenge the validity of the ’501
`
`patent. Accordingly, I did not consider those other challenges.
`
`29. The analysis in this declaration is in accordance with the above-stated
`
`legal principles.
`
`III. PERSON OF ORDINARY SKILL IN THE ART
`30.
`I understand that the level of ordinary skill may be reflected by the
`
`prior art of record, and that a person of ordinary skill in the art to which the
`
`claimed subject matter pertains would have the capability of understanding the
`
`scientific and engineering principles applicable to the pertinent art. I understand
`
`that one of ordinary skill in the art has ordinary creativity, and is not a robot.
`
`31.
`
`I understand there are multiple factors relevant to determining the
`
`level of ordinary skill in the art, including (1) the levels of education and
`
`experience of persons working in the field at the time of the invention, (2) the
`
`sophistication of the technology, (3) the types of problems encountered in the field;
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`and (4) the prior art solutions to those problems. There are likely a wide range of
`
`educational backgrounds in the technology fields pertinent to the ’501 patent.
`
`32. A technology field pertinent to the ’501 patent is semiconductor
`
`manufacturing of integrated circuits. A person of ordinary skill in the art
`
`(“POSITA”) at the time of the alleged invention of the ’501 patent would have had
`
`the equivalent of a Master’s degree in electrical engineering, physics, chemistry,
`
`materials science, or equivalent training, and two years of work experience in field
`
`of semiconductor manufacturing. Additional graduate education could substitute
`
`for work experience, and additional work experience/training could substitute for
`
`formal education. As described in more detail above, I would have been a person
`
`with at least ordinary skill in the art of the ’501 patent as of the time of its alleged
`
`invention.
`
`IV. TECHNOLOGY BACKGROUND
`33. The challenged claims relate to semiconductor devices, which existed
`
`long before the filing of the application that became the ’501 patent. The claims
`
`recite features that were standard to many, if not all, MISFET transistors, such as
`
`an active region made of a semiconductor substrate, a gate insulating film, a gate
`
`electrode, source/drain regions, and a silicon nitride film.
`
`34. Metal-insulator-semiconductor field effect transistors (MISFETs) with
`
`standard features claimed in the ’501 patent were first developed long before the
`
`10
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`’501 patent. The small size of MISFETs as compared with prior vacuum tube
`
`technologies helped enable much of the modern computer and electronics industry
`
`that developed from the 1970s and 1980s through the present.
`
`35. MOS transistors are a type of MISFET where the insulating film is an
`
`oxide, such as silicon dioxide or silicon oxynitride. MOS transistors are by far the
`
`most common type of MISFET. The figure below shows an example of a
`
`MISFET, and more particularly, a MOS transistor. Single crystal silicon is a
`
`semiconductor, and can be “doped” to become a conductor with a preponderance
`
`of negative charge carriers (n-type) or a preponderance of positive charge carriers
`
`(p-type). The layers containing dopant materials such as arsenic or phosphorous
`
`are sometimes described as “impurity diffusion layers.” This term refers to the
`
`addition of the dopant (“impurity”) and subsequent high temperature diffusion of
`
`impurity atoms in the pure silicon crystal. One very useful three-electrode device
`
`is a Metal-Insulator-Semiconductor Field Effect Transistor, commonly known as a
`
`“MISFET,” which can be formed on the surface of a single crystal silicon substrate
`
`(see figure below). In a MISFET, current flowing between two electrodes in
`
`electrical contact with a doped silicon layer (these contacts are called “source” and
`
`“drain”) can be controlled by the voltage on a third electrode called a “gate”
`
`electrode. The gate electrode is separated by a thin insulating layer from the
`
`current-carrying layer of silicon. The gate electrode draws almost no current. At
`
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`

`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`the time the application that led to the ’501 patent was filed, the most commonly
`
`used insulator separating the gate electrode from doped semiconductor was silicon
`
`dioxide (SiO2). The SiO2 was typically grown directly on silicon by oxidizing the
`
`surface at high temperature in the presence of water vapor.
`
`
`
`
`
`Fig. 1. Cross-sectional view of NMOS and PMOS devices1
`
`36. This type of SiO2 is called thermally-grown oxide, or simply “thermal
`
`oxide,” to distinguish it from the same material deposited by chemical vapor
`
`1 Fig. 1 was taken from Plummer et al, Silicon VLSI Technology: Fundamentals,
`
`Practice and Modeling, at 86 (1st ed. 2000) (Ex-1106). Color and labels have been
`
`added to facilitate the description.
`
`12
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`deposition, sputtering, or some other method. Devices using a silicon dioxide gate
`
`insulator are called Metal-Oxide-Semiconductor-Field-Effect-Transistors,
`
`“MOSFETs” or “MOS” transistors. MOSFETs are a type of MISFET. The region
`
`between the source and drain electrodes where current flows is called the channel
`
`region (also shown in Fig. 1 above), and a process that combines MOSFETs with
`
`p-doped channels and MOSFETs with n-doped channels is referred to as a
`
`Complementary-Metal-Oxide-Semiconductor Process or CMOS process. CMOS
`
`circuits have advantages over circuits using just one doping type MOSFET (i.e.
`
`only n-type MOSFETs or only p-type MOSFETs). The most important advantages
`
`of using CMOS in circuit designs are reduced power consumption, and reduced
`
`electrical noise.
`
`37. Fig. 1 (above) shows a cross section of a MISFET, and more
`
`particularly, a well-known n-channel MOSFET (NMOS) and an adjacent p-
`
`channel MOSFET (PMOS) device, with labels highlighting all important regions in
`
`these devices. To reduce clutter in the diagram, some labels shown on just the
`
`NMOS or just the PMOS device in Fig. 1 also apply to the complementary device.
`
`MISFETs include active regions made of a semiconductor substrate. The active
`
`regions of each device are found between the “shallow trench isolation” (STI),
`
`shown as grey regions in Fig. 1. (See J. Rabaey et al., Digital Integrated Circuits,
`
`at 42-43 (2d ed. 2003) (“Rabaey”) (Ex-1110).) The active regions are where the
`
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`transistors are formed and are present in every transistor. (Id. at 42.) The source
`
`and drain regions (green), the channel (area between the source and drain regions),
`
`and the well (“N Well” and “P Well”) are formed in regions of the active regions.
`
`(Plummer at 86 (Ex-1106).) Active areas in transistors are so well-known that they
`
`are usually not labeled in transistor drawings. The gate electrode (orange) is
`
`formed above the channel.
`
`38. The gate electrode (orange) is separated from the channel by an
`
`insulating film (red). (Plummer at 86 (Ex-1106).) The doped regions of the source
`
`and drain regions (green) are formed by doping the substrate with impurities. (Id.
`
`at 80-82.) It was common and conventional for source and drain regions (green) to
`
`have a lightly-doped region, a heavily doped region, and a silicide film, as shown
`
`in Fig. 1 above. (Id.) The lightly-doped and heavily doped regions are sometimes
`
`referred to as LDD (lightly-doped drain) and HDD (heavily-doped drain), although
`
`it is understood that both the source and drain are lightly and heavily doped.
`
`39. The STI are formed using the trench method and define the active
`
`region. This process is illustrated in textbooks such as Rabaey and Plummer.
`
`Rabaey explains: “The process starts with the definition of the active regions—
`
`these are the regions where the transistor will be constructed. All other areas of the
`
`die will be covered with a thick layer of silicon dioxide (SiO2) call the field oxide.
`
`This oxide acts as the insulator between neighboring devices, and it is either grown
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`(as in the process of Figure 2-1) or deposited in trenches (Figure 2-2)—hence, the
`
`name trench isolation.” (Rabaey at 42 (Ex-1110).) Figure 2-6 illustrates this
`
`process, which begins with the step “Define active areas” and “Etch and fill
`
`trenches.”
`
`(Rabaey at 43, Fig. 2-6 (Ex-1110).) Figure 2-7(c) shows the process of forming
`
`the trenches through a “plasma etch of insulating trenches using the inverse of the
`
`active area mask” to form an “NMOS and a PMOS transistor”:
`
`
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`
`
`
`(Rabaey at 44, Fig. 2-7 (Ex-1110).)
`
`40. The Plummer textbook similarly includes sections on “Active Region
`
`Formation” (section 2.2.2) and “Process Options for Device Isolation—Shallow
`
`Trench Isolation” (section 2.2.3). Plummer explains that “Modern CMOS chips
`
`integrate millions of active devices (NMOS and PMOS) side by side in a common
`
`silicon substrate” and that “it is usually assumed that the individual devices do not
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`interact with each other except through their circuit interconnections.” (Plummer
`
`at 52-53 (Ex-1106).) Plummer further explains that “individual devices on the chip
`
`are electrically isolated from each other … by growing a fairly thick layer of SiO2
`
`in between each of the active devices.… The regions between these thick SiO2
`
`layers, where transistors will be built, are called the ‘active’ regions of the
`
`substrate.” (Id. at 53.) Plummer also explains that active regions may be defined
`
`by STI regions: “STI actually etches trenches in the silicon substrate between
`
`active devices and then refills them with SiO2.” (Id. at 57.) Figures 2-6 through 2-
`
`9 illustrate this process of forming the STI regions that separate and define the
`
`active regions:
`
`
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`
`
`
`(Id. at 57-59, Figs. 2-6 to 2-9.)
`
`41. The source and drain contacts are formed with a metal silicide, which
`
`is an electrically conductive metal-silicon compound. The silicide source and
`
`drain layers are in electrical contact with a shallow, heavily doped (highly
`
`conductive) semiconductor region, connected to a lightly doped region near the
`
`gate. This two level doping structure is called a “lightly doped drain” (LDD)
`
`structure, although LDD also implies a symmetric, lightly doped source layer. The
`
`LDD structure allowed the NMOS and PMOS devices to be dramatically reduced
`
`in size while minimizing “short channel effects” that occur as dimensions are
`
`reduced. One important such short channel effect, called “hot electron injection,”
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`results in unstable MOSFET electrical characteristics, and is caused by an increase
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`in the number of very energetic electrons (hot electrons) generated as device size is
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`reduced. The LDD doping structure is most easily fabricated using a gate spacer,
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`shown as the labelled dark blue region immediately surrounding each gate in Fig.
`
`1—first the LDD doping, second the formation of the gate spacer, and third the
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`HDD doping using the gate spacer as a mask. The spacer dimensions help control
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`the doping level introduced by ion implantation (high energy implantation) of
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`dopant atoms near each gate. The use of a gate with a gate spacer to align the
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`source and drain implants and contact metal is sometimes called “self-aligned
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`contacts” or “SAC.” The term “self-aligned” is used because the process aligns the
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`gate, the contact metal, and the contact implants to each other.
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`42. The gate electrodes (orange) shown in Fig. 1 consist of two layers,
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`and this layered structure was typical of state-of-the-art MOSFETs at the time the
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`initial ’501 patent application was filed. The topmost layer of the gate is a metal
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`silicide, usually of the same composition as the silicide used to form the source and
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`drain contacts. The lower layer of the gate electrode can be made of materials such
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`as a highly doped polysilicon (i.e., polycrystalline silicon) or a metal. The top
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`layer of metal silicide is considerably more electrically conductive than the
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`underlying polysilicon, and this characteristic is a key benefit in reducing the
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`overall gate electrode resistance. 2 The gate insulator (red) can be made of
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`materials such as thermally-grown silicon dioxide (SiO2) or silicon oxynitride
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`2 For historical reasons, the term “MOSFET” refers to both devices with
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`polysilicon/silicide gates and devices with metal gates.
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`20
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`(SiOxNy). The polysilicon (underneath the metal silicide) was advantageous in the
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`gate structure because it forms an electrically favorable interface with the top side
`
`of the gate insulator. However, polysilicon is more resistive than metal, and
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`polysilicon forms a depletion region that effectively increases the gate insulator
`
`thickness. Since thinner gate insulator was required for further reduction in
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`MOSFET size, the depletion region was an undesirable feature of the polysilicon.
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`43. Silicon dioxide (SiO2), grown thermally forms a nearly ideal (stable,
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`almost charge-free) interface with the underlying doped silicon layer carrying
`
`current between the source and the drain. Silicon dioxide was well established as
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`an extremely reliable gate insulating layer, and nearly all MISFETs produced at the
`
`time used thermally grown SiO2 as the gate insulator. However, gate insulating
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`materials with a higher dielectric constant, called “high-k” dielectrics, were known
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`at the time to be needed for MISFETs with extremely small gate dimensions (tens
`
`of nm). At the time, those skilled in the art were aware that an all-metal gate
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`would work more advantageously than a silicide/polysilicon gate with a high-k
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`dielectric gate insulator.
`
`44. Silicon nitride films were commonly included over the source and
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`drain regions (green) in MISFET devices, with the gate electrode (orange)
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`protruding above the silicon nitride film long before the alleged invention of the
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`’501 patent. (E.g., Igarashi at [0117-0118], Fig. 12 (Ex-1104); Misra at 5:52-55;
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`6:67-7:15 (describing formation of protruding gate illustrated in Fig. 7), Fig. 7 (Ex-
`
`1105).) Silicon nitride films were commonly used for applications like etch stops.
`
`(E.g., Igarashi at [0047] (etch stop) (Ex-1104); Misra at 5:24-27 (etch stop) (Ex-
`
`1105).) Etch stops are included to control the etching process during
`
`manufacturing. The use of silicon nitride films in MISFET devices and design
`
`choices about what portions of the device to cover and how to locate the height of
`
`the gate relative to the nitride film were well understood before the alleged
`
`invention of the ’501 patent.
`
`V. OVERVIEW OF THE ’501 PATENT
`45. As discussed below, the challenged claims are directed to a transistor
`
`with the standard structures of conventional MISFETs at the time. As depicted in
`
`Figure 1 of the ’501 patent, reproduced below with annotations, the claimed device
`
`of the ’501 patent includes: (1) an active region 1a made of a substrate 1, (2) a
`
`gate insulating film 5 (red), (3) a gate electrode 6a (orange), (4) source and drain
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`regions 3a, 4a including a silicide layer (green), (5) a silicon nitride film 8a (blue),
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`and (6) the gate electrode 6a (orange) that protrudes from the silicon nitride film 8a
`
`(blue). (’501 patent at 3:19-64, Fig. 1 (Ex-1101).) The active region 1a is located
`
`between the isolation regions 2 and is where the transistor is formed. (’501 patent
`
`at 3:19-64, Fig. 1 (Ex-1101.)
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`U.S. Patent 7,893,501
`Declaration of Stanley R. Shanfield, Ph.D.
`
`
`
`(’501 Patent, Fig. 1 (Ex-1101).)
`
`46. The allegedly distinguishing feature of the claims of the ’501 patent is
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`gate 6a (orange) protruding above the silicon nitride film 8a (blue).3 (See
`
`
`3 The alleged invention described in the specification of the ’501 patent involves
`
`generating stress in the transistor channel by using tensile and compressive stresses
`
`of various layers. (See, e.g., ’501 patent, Abstract, 1:20-23 (Ex-1101).) However,
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`the stress limitations are only recited in claims 2, 3, and 20. The vast majority of
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`the claims, including all of the challenged claims in this declaration fail to recite
`
`any stress limitati