Fundamentals, Practice and Modeling
`
`SILICON VLSI
`TECHNOLOGY
`
`Prentice Hall Electronics and VLSI Series—Charles Sodini, Series Editor
`
`aee
`
`James D. Plummer ° Michael D. Deal » Peter B. Griffin
`
`TSMC 1008
`
`

`

`Silicon VLSI Technology
`
`Fundamentals, Practice and Modeling
`
`James D. Plummer
`Michael Deal
`Peter B. Griffin
`Departmentof Electrical Engineering
`Stanford University
`
` eee
`
`Hall
`
`Prentice Hall
`Upper Saddle River, NJ 07458
`
`

`

`Library of Congress Cataloging-in-Publication Data
`Silicon VLSI technology
`p.
`cm.
`ISBN 0~13-085037-3
`1. Integrated circuits—Very large scale integration—Design and
`construction.
`2.Silicon.
`3. Silicon oxide films.
`4. Metal oxide
`semiconductors.
`5. Silicon technology.
`TK7874.75.854
`2000
`621.39'S—de21
`
`99-42745
`CIP
`
`*,
`
`Me
`
`Publisher: Tom Robbins
`Associate Editor: Alice Dworkin
`Editorial/Production Supervision: Rose Kernan
`Vice President and Editorial Director, ECS: Marcia Horton
`Vice President ofProduction and Manufacturing: David W.Riccardi
`Executive Managing Editor: Vince O’Brien
`Marketing Manager: Danny Hoyt
`Managing Editor: David A. George
`Manufacturing Buyer: Pat Brown
`Manufacturing Manager: Trudy Pisciotti
`Art Director: Jayne Conte
`Cover Design: Bruce Kenselaar
`Editorial Assistant: Jesse Power
`Copy Editor: Martha Williams
`Composition: D&G Limited, LLC
`
`cK §—©2000 by Prentice Hall, Inc.
`pone=Upper Saddle River, New Jersey 07458
`
`All rights reserved. No part of this book may be
`reproduced, in any form or by any means,
`without permission in writing from the publisher.
`
`The author and publisher of this book haveused their best efforts in preparing this book. These efforts include the
`development, research, andtesting of the theories and programs to determine their effectiveness. The author and
`publisher make no warranty of any kind, expressed or implied, with regard to these programs or the documentation
`contained in this book. The author and publishershall notbe liable in any event for incidental or consequential damages
`in connection with, or arising out of, the furnishing, performance,or use of these programs.
`
`Printed in the United States of America
`
`10
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`9
`
`8
`
`7 65 43 2
`
`ISBN 0-13-085037-3
`
`Prentice Hall International (UK) Limited, London
`Prentice Hall of Australia Pty. Limited, Sydney
`Prentice Hall Canada Inc., Toronto
`Prentice Hall Hispanoamericana, S.A., Mexico
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`Editora Prentice? Hali do Brasil, Ltda., Rio de Janeiro
`
`

`

`
`
`
`
`
`
`
`
`Preface... cc cece een cena e nee e ben teneeeneunennenees
`
`. Xi
`
`Chapter 1
`
`1.3.
`1.4
`
`Introduction and Historical Perspective
`1.1
`Introduction. 0.0.0... 00... ccc e cnet een nnenen
`1.2
`Integrated Circuits and the Planar Process—Key Inventions That Made
`It All Possible. 2... nee ete n nee n nee enes
` Semiconductors...... 0... eee cence nee teen eben eeaes
`Semiconductor Devices»... 0...6.e eee n nen es
`33
`1.4.1
`PN Diodes..... 0... cnn tenet nen eneees
`33
`1.4.2©MOS Transistors ..... 2... cence tenn ene nees
`36
`1.4.3
`Bipolar Junction Transistors ..... 2... cette eee ees
`39
`Semiconductor Technology Families. ...........0.0.0.0.00 000. cece cece eee eae
`1.5
`41
`1.6 Modern Scientific Discovery—Experiments, Theory, and
`Computer Simulation. 2.0.0.0... cece cece e eee eens
`43
`
`if6-Tine Plan. Por Tits Bo@k ..asaaememeamwasd $$644445 $4? kesaamwamaammawmnmnawne 45
`1.8
`Summary of Key Ideas... 1.0... ccc cette eee eeees
`46
`1.9 References....... ccc eee e eee n en bette ene eenes
`46
`1.10
`Problems ....... ccc cece cent tte t nent ene e beens
`47
`
`1
`
`el
`
`.7
`
`13
`
`Chapter 2 Modern CMOSTechnology
`Zui,
`TWGROOWOHOM,
`. 2: 22i:2:nemmmanmumememsa ttt bb 15+ tec am amnawnammenmnnmonnn
`2.2
`CMOSProcess Flow........... 000s 2+: epee rePueesesasseuseee
`2.2.1
`The Beginning—Choosing a Substrate ...........0.. 0.0 eee
`2.2.2
`Active Region Formation ........ 0... cece eee eee eee eens
`2.2.3
`Process Option for Device Isolation—Shallow Trench Isolation.........
`2.2.4 Nand P Well Formation. .......... 0.0... ee
`2.2.5
`Process Options for Active Region and Well Formation................
`2o20
`‘GEIS FOMNGNOMs sunanwacaasecad tei ets tere mnanemewmmnmewmnnewwean
`2.2.7.
`‘Tip or Extension (LDD) Formation. ............ 0... cece eee eee
`226
` ‘Source/Drait POA cee csee ces 5 455258 ReRRe Seed denen semswwan
`2.2.9
`Contact and Local Interconnect Formation .....................00005
`2.2.10 Multilevel Metal Formation ...........0. 0.00. cece eens
`Summary of Key Ideas... 0... eee eee e eens
`Probems... 1.2... eee n cnet tenn eee e eee eens
`
`2.3
`2.4
`
`49
`
`49
`50
`51
`52
`57
`60
`63
`71
`76
`80
`82
`84
`90
`91
`
`

`

`Contents
`
`Chapter 3
`
`Crystal Growth, Wafer Fabrication and Basic Properties
`of Silicon Wafers
`
`93
`
`3.4.2
`
`3.1
`3.2
`
`Introduction. 2.0.0... ccc ccc eee cence eens enn eetnneeuannns 93
`Historical Development and Basic Concepts ...........0.0000 0c cece eee eee eee 93
`3.2.1
`Crystal Structure... ccc cee cece ence ee nanes 94
`222
`Detects in Crystals .: asassadsannnnun ce sescessceseeesssupppunnpanen oF
`3.2.3
`Raw Materials and Purification .......0..0.0 00.00 cc cece ee ccc eeeees 101
`3.2.4
`Czochralski and Float-Zone Crystal Growth Methods................ 102
`3.2.5 Wafer Preparation and Specification............0.0.0 00000 cece eee eee 105
`3.3. Manufacturing Methods and Equipment.............0000 00. c cece cece cues 109
`3.4 Measurement Methods..........0.0. 0.00. cece eee cece e ee eeunneeeecueneas 111
`3.4.1
`Electrical Measurements.........0.00. 00000. c cece eee ecceeeeeneues lil
`3.4.1.1 Hot Point Probe....... 0. ccc cece eeeees 112
`“3.4.1.2
`Sheet Resistance ........0 00000 cece cece eee ne eees 113
`3.4.1.3 Hall Effect Measurements ...........000 0. ccc cc cece ce uees 115
`Physical Measurements ..........0..0. 000000 c cece cece e ee euaeeeues 117
`3.4.2.1 Defect Etches.......00 00.0. c ce cece ees nee eeeunees 117
`3.4.2.2
`Fourier Transform Infrared Spectroscopy (FTIR)............ 118
`3.4.2.3
`Electron Microscopy...........0.. 0c ccc cece cece eee eeuas 119
`3.5 Models and Simulation.......0..0.0000 0000 ccc cece cece neces cern eeeteeeuua 121
`3.5.1
`Czochralski Crystal Growth .......0.00. 000000 ccc ccc cece e eee eeees 122
`3.5.2
`Dopant Incorporation during CZ Crystal Growth. ................... 125
`3.5.3
`Zone Refining and FZ Growth.........0.0 00.00. e cece cece e ee aes 128
`3.5.4
`Point Defects........ 0000. ec eee eee cena eneeveeeeues 131
`3.5.5
` Oxygenin Silicon... ccc cece nee ence eeeeenaes 138
`3.5.6
`Carbon in Silicon 2.0... 0.0 ccc ccc cece cece eees 142
`3.5.7
`Simulation.........0.000 0000 ccc cc cece eee eee ennneenes 143
`Limits and Future Trends in Technologies and Models .................00000% 144
`3.6
`Summary of Key Ideas... ccc ccc eee eee aeeennnaes 146
`3.7.
`3.8 References... cece cece ence eect eeeeebbbeeeenes 147
`3.9
`PYODICMS «ccs sees eS Smmmunme veseserss+ nny appanasannenuseseenennes 148
`
`Chapter 4
`
`Semiconductor Manufacturing—Clean Rooms, Wafer Cleaning,
`and Gettering
`
`151
`
`4 Introduction. 0... ccc ccc cece cee cece ee ee been eeees 151
`4.2
`Historical Development and Basic Concepts ...........0. 0.0 ccc eee eeeeeeees 154
`4.2.1
`Level 1 Contamination Reduction: Clean Factories................... 157
`4.2.2
`Level 2 Contamination Reduction: Wafer Cleaning................... 159
`4.2.3
`Level 3 Contamination Reduction: Gettering..........0.0........004. 161
`4.3 Manufacturing Methods and Equipment.............000. 00. cccceceeecuseeae 165
`4.3.1
`Level 1 Contamination Reduction: Clean Factories..............00004 165
`4.3.2
`Level 2 Contamination Reduction: Wafer Cleaning................... 166
`43.3
`Level 3 Contamination Reduction: Gettering....................000. 167
`4.4 Measurement Methods.........0.0.0.00 00. ccc cece ccc cece nese eeeeeenennns 169
`44.1
`Level 1 Contamination Reduction: Clean Factories...............008. 169
`
`

`

`Contents
`
`
`
`
`Level 2 Contamination Reduction: Wafer Cleaning................... 173
`442
`Level 3 Contamination Reduction: Gettering....................00.. 176
`443
`4.5 Models and Simulation.......... 0.00...ocee ce cena 180
`4.5.1
`Level 1 Contamination Reduction: Clean Factories................... 181
`4.5.2
`Level 2 Contamination Reduction: Wafer Cleaning................... 184
`45.3.
`Level 3 Contamination Reduction: Gettering.....................05. 186
`4.5.3.1
`Step 1: Making the Metal Atoms Mobile ................... 186
`4.5.3.2
`Step 2: Metal Diffusion to the Gettering Site................ 187
`4.5.3.3.
`Step 3: Trapping the Metal Atomsat the Gettering Site....... 190
`Limits and Future Trends in Technologies and Models ....................... 193
`Summary of Key Ideas...:.2..00cesqnssenennemsseeseusneeeansaeaeasanags 196
`References... 00... eee tne e eee ee eee nee 196
`Problems ...... 0... ce eee teeter eee e bene ens 198
`
`4.6
`472
`4.7
`4.9
`
`Chapter5
`
`5.2.3
`
`201
`Lithography
`5.1
`Introduction. ...... 0... cece cence renee ence ee eee 201
`5.2
`Historical Development and Basic Concepts ............ 0.0.0. c cece eee 203
`S21
`Light SOUTSES...........2525.85485 SERRE OR ERE ERR O EERE REESE ER EAS 206
`5.2.2. Wafer Exposure Systems... 00... cece tenes 208
`5.2.2.1
`Optics Basics—RayTracing and Diffraction ................ 209
`5.2.2.2
`Projection Systems (Fraunhofer Diffraction)................ 242
`5.2.2.3
`Contact and Proximity Systems (Fresnel Diffraction) ........ 219
`Photoresists........... 00 ccc c eee cece eee eee e eee ete ene ees 221
`5.2.3.1
`g-line and i-line Resists... 0.0... eee eee 223
`5.2.3.2 Deep Ultraviolet (DUV) Resists..................000 000 225
`5.2.3.3.
`Basic Properties and Characterization of Resists ............ 22/7
`5.2.4 Mask Engineering—Optical Proximity Correction and Phase Shifting. .
`. 230
`5.3. Manufacturing Methods and Equipment............ 0... cece eee eee 234
`5.3.1 Water BROSUPS SYSICHIS...cccaceeesuseeeussateesszeseresssssseit 234
`5.3.2
`PhotoresistS.. 0.0... ec eee teen teen ees 238
`Ba. Measurement Methods, .<.cccscicssetceessiteastsesteeaiseeensceeeesaess 241
`5.4.1 Measurement of Mask Features and Defects .....................00, 242
`5.4.2 Measurement of Resist Patterns.......... 2.0... ccc cee eee 244
`54.3
`Meéedasitrement of Etched Features... 2. wcsssscunnas wusmaasceeseezase 244
`5.5 Models and Simulation............ 00. cece ccc eee eee eee e eens 246
`55.. Water EXposite SYSICHIS. .2:3:55csn,cenemaenonenaauasaerrrrrere es 247
`5.5.2
`Optical Intensity Pattern in the Photoresist .................000000-- 253
`5.55
`PHOLOPESISE EXPOSUTC anucsanuusssneneeesauneusseuaueussanuarseess 259
`5.5.3.1
`g-line and i-line DNQ Resists........0....0 0.0 cee eee ee eee 259
`§.5.3.2 DUV Resists..... 0.00.0 eee 263
`Postexposure Bake (PEB)...........00cnnnnnnnnd du dGeES SETS EDS ESS 264
`5.5.4.1
`g-line and i-line DNQ Resists. ............. 000 c cece eee ees 264
`5542
`DUYV RGSS. 2... nn cane mewoueda eid dS ces REET OEAe EE 266
`Photoresist Developing .... 0... eee ees 267
`Phoetorésist POSthake on. wnwewnw ve die ibs ESSE SATO EEE RES 270
`
`5.5.4
`
`5.5.5
`5.5.6
`
`

`

`Contents
`
`Advanced Mask ERGMEEHS ..5....0cunesenssosysumananmanaaeere ss 271
`5.5,/
`Limits and Future Trends in Technologies and Models .............0....0000 DVL
`5.61
`BEléctron Beam Lithography o«anssascsceswsnsseemsenanennemeesere se 273
`5.6.2
`X-ray Lithography ........ 0... cece eee eee 213
`5.6.3.
`Advanced Mask Engineering .........000 0.00 ee eee 277
`564
`MNew RESIS........c0rencumns > souundduddIdIISAIOEE SORTS SEO RBRS 278
`Summary of Key Ideas... 1... eee eens 281
`RGTSPEHCES 0. oon oad SAMBUB SSSR 222555257558 22EE LER EEE REE EN HEE Tess < 281
`Problems ......0.. 0.0. c cc eee ee ene eee e ete e eee 283
`
`5.6
`
`5.7
`SS
`5.9
`
`Chapter6
`
`Thermal Oxidation and the Si/SiO2 Interface
`
`287
`
`Introduction. ....... 0... ce een ene e eens 287
`6.1
`Historical Development and Basic Concepts ... 0.0... 290
`6.2
`6.3. Manufacturing Methods and Equipment...........6... 296
`6.4 Measurement Methods.......... 0... ccc cee eee eens 298
`64.1
`‘Pliysical Measurements ; isi sasassaasassaensseetesttieseseeeseeers 299
`6.4.2
`Optical Measurements... 0.0.0.6 cee eee eee 299
`6.4.3.
`Electrical Measurements—The MOS Capacitor ........... 0.0... eee 301
`6.5 Models and Simulation. .......0.0.0 000. ee net eens 312
`6.5.1.
`First-Order Planar Growth Kinetic —The Linear Parabolic Model ..... 313
`6.5.2
`Other Models for Planar Oxidation Kinetics ...........0......00055. 322
`6.5.3.
`Thin Oxide SiOz Growth Kinetics ........ 0.00... cece eee 326
`65.4
`Dependence of Growth Kinetics on Pressure... ...sessneeaneeseeesrs 328
`6.5.5
`Dependence of Growth Kinetics on Crystal Orientation .............. 329
`6.5.6 Mixed Ambient Growth Kinetics.........00. 0... c eee eee eee 332
`6.5.7
`2D.-$10> Growih KinehGs...........0.0085688008 9 EERE DESO SEeEEER EOE 333
`6.5.8
`Advanced Point Defect Based Models for Oxidation................. 339
`659
` Suistate Doping Prete, 12sscccceseeneeeucwecenouasuccnasueeanes 343
`6.5.10 Polysilicon Oxidation. . 00.0... eee eee 345
`6.5.11
`SisNs Growth and Oxidation Kinetics ....... 0.00222. 347
`65.12
`Silicide OxidatiOl...... wwe cee FEE EEE ESddSSIES LARS R CARRE ES 350
`6.5.13
`Si/SiOs Interface Charges ..... 0... nee eens 352
`6.5.14 Complete Oxidation Module Simulation .............. 0... 357
`Limits and Future Trends in Technologies and Models ....................05. 259
`Summary of Key Ideas... 0...ee eee eens 361
`PRELPENCES0. mm eee neon eens FESEEISESETEFEESERERERAEEEEEESE 361
`Problems ....... 0... ee eee eee eee e eens 364
`
`6.6
`6.7
`GS
`6.9
`
`371
`DopantDiffusion
`TA
`Introduction... 0.0 een eens 371
`7.2
`Historical Development and Basic Concepts .......... 6.0 eee eee eee eee 374
`7.2.1
`Dopant Solid Solubility...00... 375
`7.2.2
`Diffusion from a Macroscopic Viewpoint ..........000 2. eee ee eee eee 377
`7.2.3
`Analytic Solutions of the Diffusion Equation. ................--0005- 379
`7.2.4
`Gaussian Solution in an Infinite Medium .................. 020220085 380
`
`Chapter 7
`
`

`

`Contents
`
`Gaussian Solution Near a Surface ....... 0.0... ccc ccc e cece eee 381
`7.2.5
`Error-Function Solution in an Infinite Medium....................., 382
`7.2.6
`Error-Function Solution Near a Surface .................000005 re 384
`7.2.7
`Intrinsic Diffusion Coefficients of Dopants in Silicon................. 386
`7.2.8
`Effect of Successive Diffusion Steps 0.0.2.0... 0.0.00 388
`7.2.9
`7.210 Design and Evaluation of Diffused Layers................0000000005 389
`7.2.11
`Summary of Basic Diffusion Concepts ............ 000000 392
`7.3. Manufacturing Methods and Equipment.................0 00 cece eee eee eee 302,
`7.4 Measurement Methods......... 00... cece eet eee beeen eens B95
`fet
`SUNS casesssasanesmanencenscernaddddad $452.45 5ecenmnnnuconnnnnn 396
`7.4.2
`Spreading Resistance... 0... eee eee aes 397
`7.4.3
`Sheet Resistance....... 0... cece cence eees 398
`7.4.4
`Capacitance Voltage.... 00... ccc eee ees 399
`7.4.55
`TEM Cross Section. ...... 000.e een n en nns 399
`7.4.6
`2D Electrical Measurements Using Scanning Probe Microscopy ....... 400
`7.4.7.
`Inverse Electrical Measurements............ 000 c cece eee eee 402
`7.5 Models and Simulation. ....... 0.0...n eee e eee eees 403
`7.5.1.
`Numerical Solutions of the Diffusion Equation...................05. 403
`7.5.2|Modifications to Fick’s Laws to Accountfor Electric Field Effects...... 406
`7.5.3. Modifications to Fick’s Laws to Account for
`Concentration-Dependent Diffusion............ 0.0... cee eee 409
`Segregation .... 0... eee eee eee e ene ees 413
`TS54
`Interfacial Dopant Pileup ........ 2... cece eee 415
`7.5.5
`Summary of the Macroscopic Diffusion Approach ................60. 417
`7.5.6
`The Physical Basis for Diffusion at an Atomic Scale...............05. 417
`7.5.7.
`Oxidation-Enhanced or -Retarded Diffusion.....................0.. 419
`7.5.8
`Dopant Diffusion Occurs by BothIandV....................00 00 ee 422
`7.5.9
`7.5.10 Activation Energy for Self-Diffusion and Dopant Diffusion........... 426
`7.5.11 Dopant-Defect Interactions .......00 0... ccc cece es 426
`7.5.12 Chemical Equilibrium Formulation for Dopant-Defect Interactions ... . 432
`7.5.13
`Simplified Expression for Modeling........ ccc eee eee e eee e eens 434
`Tai@ Charge Siate Etec’. -..asaacuaeusaessereanOhdusacammnannmemomune 436
`Limits and Future Trends in Technologies and Models ....................00. 439
`7.6.1
`Doping Methods......... 0.0.0... cece cece eee nes 44()
`7.6.2
`Advanced Dopant Profile Modeling—Fully Kinetic Description
`of Dopant-Defect Interactions .............. 00. e eee eee eee 4AQ)
`Summary of Key Ideas... 0... cet tne enes 442
`References. ... 0.0... cece t etn e tne e tees 443
`Problems 1.0.0.0... eee nen c eee n tenn nnn eees 44S
`
`7.7
`7.8
`7.9
`
`7.6
`
`Chapter 8
`
`Ion Implantation
`
`451
`
`C4
`8.2
`
`SLPOGUCNON seen 5: aanasneanamEnORnsRDaTRG GEER SSG duabwoennennomannane 451
`Historical Development and Basic Concepts ............-..00 0000 cece eee eees 451
`8.2.1
`Implants in Real Silicon—TheRole of the Crystal Structure........... 461
`8.3. Manufacturing Methods and Equipment.............. 0... cece eee eee es 463
`
`

`

` Contents
`
`Chapter9
`
`High-Energy Implants .........0. 0.0. c cece eee cc ccc cece een ees 466
`8.3.1
`Ultralow Energy Implants........ 00.0.0... ccc cece cee eee cece eee 468
`8.3.2
`Jon Beam Heating ....... 00.0.e eee eees 469
`8.3.3
`8.4 Measurement Methods. ...........0. 0.0.00. ccc cece cc eect cee ee eenneeaaas 469
`8.5 Models and Simulations. ......... 0.00 c ccc cece ence cece eee een aes 470
`8.5.1
`Nuclear Stopping ..... 0.60.0.c ccc eee eeeenes 471
`8.5.2
`Nonlocal Electronic Stopping.............000 000 cece cece cence ees 473
`8.5.3
`Local Electronic Stopping. .......0. 0... ccc cee cece cece eee ees 474
`8.5.4
`Total Stopping Powers .... 0.0... cece cece ee eee eeee 475
`8.5.5
`Damage Production. ......0.0 0... ccc cece cence eee e ees 476
`8.5.6
`Damage Annealing........0.... 0.0 c ccc eee ccc eee e cece ene cece 479
`8.5.7
`Solid-Phase Epitaxy .... 0.00... c cece cece cence eee n ene eees 482
`8.5.8
`Dopant Activation 0.0.0... 6 cece cece cee eee e ene eenes 484
`8.5.9
`| Transient-Enhanced Diffusion .......... 0.0.0.0... ccc cece cece eeee 486
`8.5.10 Atomic-Level Understanding of TED...............0 0.0... c eee eee 488
`8.5.11 Effects on Devices .... 0... cee cece eee eee enneeeens 497
`Limits and Future Trends in Technologies and Models ................00.000: 499
`Summary of Key Ideas... 6... cece cece cece nee eeneennee 500
`References... 0... ccc eee cece ence eeneennneennas 500
`Problems ©... 2... ccc cece eee e beeen eee eennneeeennas 502
`
`8.6
`8.7
`8.8
`8.9
`
`9.2.2
`
`509
`Thin Film Deposition
`9.1
`Introduction. 00... ccc ec n ccc cece nee eeeeeeenueenas 509
`9.2
`Historical Development and Basic Concepts ............ 0.00 ccc ccc e eee ees 511
`9.2.1
`Chemical Vapor Deposition (CVD)..........0000 0.0. cece cece eee eee 512
`9.2.1.1 Atmospheric Pressure Chemical Vapor Deposition (APCVD). 513
`9.2.1.2
`Low-Pressure Chemical Vapor Deposition (LPCVD) ........ 525
`9.2.1.3
`Plasma-Enhanced Chemical Vapor Deposition (PECVD)....527
`9.2.1.4 High-Density Plasma Chemical Vapor Deposition
`(HDPCVD) .... 10 cece nce eee e ene ennes 530
`Physical Vapor Deposition (PVD) ........... 000. c ccc cece eee e eens 530
`9.2.2.1
`Evaporation ...... 0.0. ec ccc eee e ence ees 531
`9.2.2.2
`Sputter Deposition ........... 0000. c eee e eee en eees 539
`9.3. Manufacturing Methods.......... 00... cece cece cece eee eeeeeeeeeanes 554
`9.3.1
`Epitaxial Silicon Deposition .............0. 000 ccc ccc eee eee eens 556
`9.3.2
`Polycrystalline Silicon Deposition ............ 0.00. cc eevee eee eeees 558
`9.3.3.
`Silicon Nitride Deposition. .........00.0.0 0000 c cece cece ene eeeeeeees 561
`9.3.4
`Silicon Dioxide Deposition. .......0.0.0. 0000. c cece e cece eeneeuas 563
`9.3.5
`Al Deposition ...... 0... 0c ccc cence cence eneeenaeees 565
`9.3.6
` Tiand Ti-W Deposition.......0.00. 00.00. c ccc cece ccc ee cee eseaes 566
`9.3.7 W Deposition ....... 0... cece cece cece ee esnseeeneunees 567
`9.3.8 TiS and WSin Deposition....... 0.0.e cece en aes 567
`9.3.9
`TiN Deposition .........0 0.0.00 ccc cece cece eens eeeeseenueeees 568
`9.3.10 Cu Deposition... 0.00...e ences eeeeunanes 570
`9.4 Measurement Methods....... 00000. .cccccccc ee cence eee cence eeneeuees 572
`
`

`

`Contents
`
`9.5.2
`
`9.5 Models and Simulation........... 00.00 cee eee teen ents 573
`9.5.1 Models for Deposition Simulations ........... 0.00 eee eee eee eee eee 573
`9.5.1.1 Models in Physically Based Simulators Such as SPEEDIE ....574
`9.5.1.2 Models for Different Types of Deposition Systems........... 582
`9.5.1.3
`Comparing CVD and PVD and Typical Parameter Values ... . 587
`Simulations of Deposition Using a Physically Based
`Simulator, SPEEDIE............scccceceeasscassteeseteteeeeen 590
`Other Deposition Simulations ............ 6... eee eee eee eee 598
`9.5.3
`Limits and Future Trends in Technologies and Models ...............-----55- 601
`Summary of Key Ideas... 2...ee eee eens 602
`References. .... 0c. ccc ee eee ene ene eee nett eet eens 603
`Problems . 2.2.46. ¢ gece ce cece ee cee FRESE SEES ESTEE TES HEE EERE REE ee 605
`
`9.6
`9.7
`9.8
`OG
`
`Chapter 10
`
`609
`Etching
`101 Uetroduction..............asa5sn:eumsseeonndeneemner rE eee ee mae 609
`10.2 Historical Development and Basic Concepts .........0... 612
`1021 “WerHtchiig. ......sssasscsusanmsmegr ne eee ea ww mmmmnmn SEE BS ME 612
`10.2.2 Plasma Etching ........... 0. cece cee ee eee eee ene nee eeenees 619
`10.2.2.1 Plasma Etching Mechanisms ...........6 0.6: e cece eee eee 621
`10.2.2.2 Types of Plasma Etch Systems ..........- 2.0. e eee seen eee 628
`10.2.2.3. Summary of Plasma Systems and Mechanisms ............-. 636
`10.3. Manufacturing Methods......... 0... cece eee ccc teenies 637
`10.3.1 Plasma Etching Conditions and Issues .........- 2... e eee eee eee 638
`10.3.2 Plasma Etch Methods for Various Films ..........--- 0c sees eee eee ee 643
`10.3.2.1 Plasma Etching Silicon Dioxide........... 25... cece eee eee 644
`10.3.2.2 Plasma Etching Polysilicon......... 6... eee eee renee eens 647
`10.3.2.3 Plasma Etching Aluminum. ............. 6. eee eee eee 649
`10.4 Measurement Methods. ........... 0.0 c cece ee eee enn ene ees 650
`105: Models and SilatiOl. .......ancaaoasnsusmar ere penne ma manmnnm makes 653
`10.5.1 Models for Etching Simulation. ........... 5. 6c cece ee eee eee ees 653
`10.5.2 Etching Models—Linear Etch Model ...........-. 6c eee eee eee eens 656
`10.5.3 Etching Models—Saturation/Adsorption Modelfor
`Ton-Enhanced Etching....... 0.0.0.0 c cece eens 663
`10.5.4 Etching Models—More Advanced Models..........-- 00.0 eee seers 669
`10.5.5 Other Etching Simulations ..... 66... 6 cece eee eee 671
`Limits and Future Trends in Technologies and Models ..........-.--.00--0055 675
`10.6
`Summary of Key Ideas... 6... ene nee es 676
`10.7.
`10.8 References... 0... ttn tert nen eens 677
`1O9
`Problems ... cc cc cece ccc ens mwa w nnn beebahkbas HRP RENE ERE PPO ee 679
`
`Chapter 11
`
`681
`Back-End Technology
`ALA JardtichOta. nners spam e enn enew none dd R ROTOR SAERREORR AES Hw ema mmm 681
`11.2 Historical Development and Basic Concepts ........- 606s eee eee eee es 687
`LUDA COVERS oop p cnn ewmmnnn remem DEER RETR ET NE DCE ww wm mH 688
`11.2.2
`Interconnects and ViaS... 0... cece ee een eee enee 695
`
`

`

`Contents
`
`11.2.3 Dielectrics 2.00... ccc cece cece cee bebeebbeeeeeeees 707
`11.3. Manufacturing Methods and Equipment.............00.0 00 0c c cee eee eueeee 715
`11.3.1
`Silicided Gates and Source/Drain Regions..........0.00.0.cc cee euee 716
`11.3.2 First-level Dielectric Processing .......0000 00. 0c cece cece ceeeeeees 718
`11.3.3 Contact Formation.....0.00 0000 ccc cece cece cc ceeeevececees 719
`11.3.4 Global Interconnects .....0 000 ccc cece eee eeccceeee 721
`11.3.5
`IMD Deposition and Planarization ..........0.00 000. c cece cece cece eee dae
`11.3.6 Via Formation........0.00.0 0000 c cece eee cece eee eee ebeebbnnens 724
`11.3.7
`Final Steps... cece ere cece ee eeneeenees 725
`11.4 Measurement Methods. .....00000 000 ccc cece ccc eee cece ccc eccbeeeeceee. 725
`11.4.1 Morphological Measurements .........0.0.00 00 cece cece ee ceceeeas 726
`11.4.2 Electrical Measurements.......00 000 c cece cccceeeeecceee 726
`11.4.3 Chemical and Structural Measurements .............0. 00-00 cceeeucee. 732
`11.4.4 Mechanical Measurements .........0.0.0 0000s ccc ccc cece cece eeees 734
`11.5 Models and Simulation. .....0.0.0.000 000000 cc cece ene ceeeences 737
`11.5.1
`Silicide Formation......0000 00000 cee cc cece cee cbeeeecee 738
`11.5.2 Chemical-Mechanical Polishing .........0.00 000000 c ccc eeceecceucees 744
`F153 ReOW casnmicaconnusunnsnmnuwr ne eaaQEeaeEUNOMEEEEEEenannmunnae 746
`11.5.4 Grain Growth 2.0.0.0... 0c ccc cece cece cee bebeeeee. 753
`11.5.5 Diffusion in Polycrystalline Materials ........00000 00. c cece eee ceee 762
`11.5.6 Electromigration.. 0.0.0... cc ccc cece neuen eeeeneas 765
`Limits and Future Trends in Technologies and Models ...................005. 776
`11.6
`Summary of Key Ideas... 0... ccc cece cece ence eeeeeecnenes 780
`11.7
`11.8 References...... 0.0... cece eee e ee be bbb eeebbbbecccee. 781
`11.9
`Problems ...... 0.0.00.e nett e tebe bbe ebeebbecccee. 784
`
`787
`Appendices
`Al
`Standard Prefixes ......0 0.0.0 cece ebbe ee becebecc ec, 787
`A.2. Useful Conversions. .......0.0000.0 00 ccc ccc eeeeceeeenee 787
`A.3
`Physical Constants .....0.0.0.0 000 ccc cece cence cece ene eee eceeec cele, 788
`A.4
`Physical Properties of Silicon ....0 000. c cece cccececcecee. 788
`A.5
`Properties of Insulators Usedin Silicon Technology .........0. 0... cece eee eee 789
`A.6
`Color Chart for Deposited SisN, Films Observed Perpendicularly under
`Daylight Fluorescent Lighting.......000 00000000 ccc ccc cece ccccceceeeee 789
`A.7—Color Chart for Thermally Grown SiO, Films Observed Perpendicularly
`under Daylight Fluorescent Lighting...........00. 000. c cece cccceuseeuee 790
`Irwin Curves 2.200...e eee been ebb ebb cece eee, 791
`A.8
`AQ Error Function. .....00.00.000 0000 ccc ccc cece cence eee bee cbecbeecbe ee ecee. 793
`A.10 List of Important Symbols......0 00000 ccc ccc ccc cece ce cbccecccce. 797
`A.11 List of Common PCPODYMS 506556 menesenowunnnnononggamennneneusmutbate 798
`A.12 Tables in Text... 0.00.0 c cece eee bebe ecb ee bce cbce ees ce. 801
`A.13 Answers to Selected Problems ...... 00.00.0000 cc cece ccc cccccccccccececceee. 802
`
`Index
`
`805
`
`

`

`
`
`
`
`Modern CMOS
`Technology
`
`2.1
`
`Introduction
`
`In most of the remaining chapters in this book, we will discuss the process technolo-
`gies usedin silicon IC manufacturing individually. Individual technologies are clearly
`most useful when they are combined in a complete process flow sequence to produce
`chips. It is often the case that unit process steps are designed the waythat they are be-
`cause of the context in which those steps are used. For example, while a dopant may
`be diffused into a semiconductorto a desired final junction depth using many combi-
`nations of times and temperatures, the fact that the junction being formed might be
`diffused in the middle of a complex process flow may greatly restrict the possible
`choices of times and temperatures. In other words, the wafer’s past history and the fu-
`ture process steps it may see can greatly influence how one chooses to perform a par-
`ticular unit process step.
`For this reason, and because we believe that understanding how complete process
`flows are put together aids understanding of individual process steps, we will describe in
`this chapter a complete modern Very Large Scale Integrated (VLSI)circuit processflow.
`The example we have chosenis typical of today’s state of the art. CMOStechnology has
`dominatedsilicon integrated circuits for the past 15 years and most people in the indus-
`try today believe that its dominance will continue for the foreseeable future for the rea-
`sons discussed in Chapter 1 (high performance, low power, supplyvoltagescalability, and
`circuit flexibility). In fact the SIA industry roadmap (NTRS)that we discussed in Chap-
`ter 1 assumes the continuation of CMOStechnology throughatleast 2012.
`For readers who are newto silicon technology, some of the ideas introducedin this
`chapter may not be fully appreciated until after later chapters on individual process
`steps have been read. However, we recommendthat such people read this chapter be-
`fore proceeding further because doing so will make the later material more under-
`standable. A second reading of this chapter after the remainder of the book has been
`studied may also prove useful. In manycases, typical process conditions that might be
`used in a given step are presented in this chapter without full explanation. This is sim-
`ply because we have not yet discussed the quantitative models and other tools at our
`disposal to calculate such parameters. As we dosoin later chapters, we will revisit the
`CMOSprocess flow described here and discuss in more detail the reasons for particu-
`lar process conditions used in this chapter.
`
`49
`
`

`

`
`
`Chapter 2 Modern CMOS Technology
`
`2.2 CMOS Process Flow
`Two typical CMOScircuits are shown in Figure 2-1. The simple inverter circuit on the
`left was described in Chapter 1. The NORgate onthe rightillustrates how additional
`NMOSand PMOSdevices can be added to the invertercircuit to realize more complex
`logic functions. In the NORcircuit,if either input 1 or input 2 or both of them are high,
`the output will be pulled to ground through one or both of the NMOSdevices which
`will be turned on. Only if both inputs are low will the output be pulled high through the
`two series PMOSdevicesthat are both turned on under this condition. Thecircuit thus
`implements the NORfunction. To build these types of circuits, we need a technology
`that can integrate NMOS and PMOSdevices on the samechip. In fact, many CMOS
`technologies also implement varioustypesof resistors, capacitors, thin film transistors,
`and perhaps other typesof devices as well. We will limit our discussion here to the two
`basic devices and describe a technology to build them. Extensionsof this technology to
`include other components are reasonably straightforward and we will see some exam-
`ples of such extensionsin later chapters.
`The endresult of the process flow we will discuss is shown in Figure 2-2. To fabricate
`a structurelike this, we will find that 16 photolithography steps and well over 100 indi-
`vidual processsteps are required. The final integrated circuit may contain millions of
`componentslike those shownin the figure, each of which must work correctly.
`There are two active device types shown in the figure, corresponding to those re-
`quired to implementthecircuits in Figure 2-1. The individualsource,drain, and gate re-
`gions of the NMOSand PMOSdevices are identifiable in the cross section. In addition
`to the active devices, there are many otherparts to the overall structure. Some ofthis
`“overhead”is required to electrically isolate the active devices from each other. Other
`
`+V
`
`+V
`
`ny
`
`PMOS
`
`
`
`Ing
`
`Input
`
`PMOS
`
`Output
`
`ane
`
`Gnd
`
`Output
`
`Figure 2-1 Simple CMOScircuits. An inverter is shown ontheleft and a NORcir-
`cuit on the right. The NORcircuit implements the function Output = IN; + IN2.
`
`

`

`
`
`CMOSProcess Flow
`
`D
`
`D
`
`G
`
`|
`im sub
`|
`
`s
`
`G
`
`_
`i<<— Sub
`|
`
`S
`
`y)
`
`ma
`// / pl
`
`Figure 2-2 Coss section of the final CMOSintegrated circit. A PMOStransistoris shown
`on the left, an NMOSdevice on the right.
`
`parts of the structure provide multiple wiring levels above the active devicesto inter-
`connect them to perform particular circuit functions. Finally, some regions are included
`simply to improve the performanceof the individual devices by decreasing parasitic re-
`sistances or improving voltage ratings. As we proceed through the steps required to
`build this chip, we will discuss each of these points in greater detail.
`
`2.2.1 The Beginning—Choosing a Substrate
`Before we begin actual wafer fabrication, we must of course choosethe starting wafers.
`In general this meansspecifying type (N or P), resistivity (doping level), crystal orienta-
`tion, wafer size, and a numberof other parameters having to do with waferflatness, trace
`impurity levels, and so on. The major choices are the type, resistivity, and orientation.
`
`

`

`
`
`
`
`Chapter 2 Modern CMOSTechnology
`
`Figure 2-2 indicates that the final structure hasia P-type substrate. In most CMOSin-
`tegrated circuits, the substrate has a moderately high resistivity (25-50 Qcm) which cor-
`respondsto a doping level on the order of 10° cm~* (Figure 1-18). As is apparent from
`Figure 2-2, the active devices are actually built in wells diffused into the surface of the
`wafer. The doping levels in these wells are chosen to optimize the electrical properties
`of the active devices, as we will see later in this chapter. Typically the well doping levels
`are on the order of 10° — 10°’ em~? near the wafer surface. In order to reproducibly
`manufacture such wells, the background doping (the substrate doping in this case)
`needsto besignificantly less than the well doping. Thus the substrate dopin