Dr. Glew Declaration re IPR 2016-003 86
`U.S. Patent No. 8653672
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG ELECTRONICS CO. LTD.
`
`MICRON TECHNOLOGY INC. and
`
`SK HYNIX INC.
`
`PETITIONERS
`
`V.
`
`ELM 3DS INNOVATIONS LLC
`
`PATENT OWNER
`
`CASE IPR2016-003 86
`
`PATENT No. 8653672
`
`DECLARATION OF ALEXANDER D. GLEW Ph.D.
`REGARDING PATENT OWNER RESPONSE FOR INTER PARTES
`REVIEW OF U.S. PATENT NO. 8653672
`
`EXHIBIT O.
`
`M. D.
`
`o
`
`am.
`EXHIBITNO/hýý
`D. 0 tt of
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`TSMC 1023
`TSMC v. GODO KAISHA
`IPR2017-01841
`
`
`U.S. Patent No. 8653672
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG ELECTRONICS CO. LTD.
`
`MICRON TECHNOLOGY INC. and
`
`SK HYNIX INC.
`
`PETITIONERS
`
`V.
`
`ELM 3DS INNOVATIONS LLC
`
`PATENT OWNER
`
`CASE IPR2016-003 86
`
`PATENT No. 8653672
`
`DECLARATION OF ALEXANDER D. GLEW Ph.D.
`REGARDING PATENT OWNER RESPONSE FOR INTER PARTES
`REVIEW OF U.S. PATENT NO. 8653672
`
`EXHIBIT O.
`
`M. D.
`
`o
`
`am.
`EXHIBITNO/hýý
`D. 0 tt of
`
`TSMC 1023
`TSMC v. GODO KAISHA
`IPR2017-01841
`
`
`
`I Dr. Alexander D. Glew hereby declare as follows
`
`Dr. Glew Declaration re IPR 2016-00386
`U.S. Patent No. 8653672
`
`1.
`
`I received a Bachelor of Science degreein Mechanical Engineering
`
`from University of California Berkeley in 1985 a Master of Science degree in
`
`Mechanical Engineering from University of California Berkeley in 1987 a Master
`
`of Science in Materials Science and Engineering from Stanford University in 1995
`
`and Doctor of Philosophy degree in Materials Science and Engineering from
`
`Stanford University in 2003. A copy of my Curriculum Vitae CV is attached to
`
`this report as Exhibit A.
`
`2.
`
`The subject matter of my doctoral dissertation at Stanford University
`
`related to chemical vapor deposition CVD of dielectric films. CVD generally
`
`consists of mixing two or more gases in a process reactor or chamber and having
`
`the gases meet on the surface of a substrate to deposit a thin film. Many of the
`
`CVD films that I worked on were deposited on undoped silicon glass SI02 and
`
`boron and phosphorous doped glass. For my doctoral dissertation I constructed a
`
`CVD reactor. Then I developed CVD processes for certain low-k dielectric films
`
`such as diamond like carbon and fluorinated amorphous carbon. Further I
`
`characterized those thin films for their engineering properties optical electrical
`
`and mechanical. Also I analyzed the chemical composition of the thin films.
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`2
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`
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`Dr. Glew Declaration re IPR 2016-00386
`U.S. Patent No. 8653672
`From 1987-1997 I was employed by Applied Materials Inc.
`
`3.
`
`Applied Materials one of the worlds largest and most advanced manufacturers
`
`of among other things CVD-related equipment.
`
`I was hired by the CVD division.
`
`The first process tool that I worked on was the Precision 5000 CVD tool.
`
`It was the
`
`first cluster tool a tool with multiple CVD processing chambers. Because this tool
`
`demonstrated the major advance in tool architecture multiple chambers attached to
`
`a central vacuum load lock chamber
`
`resulting in the ability to process one
`
`workpiece at a time instead of in batch it was eventually placed in the Smithsonian
`
`Institute Natural History Museum.
`
`4.
`
`From approximately 1987-1989 I was a Systems Engineer for
`
`Applied Materials.
`
`In this position I designed semiconductor processing
`
`equipment and worked with all aspects of the process tool. After a period of time
`
`along with the product marketing manager I signed off on every tool or machine
`
`that we shipped. My signature was required to ensure that the manufactured
`
`process tool and the chemical processes it produced matched what was required by
`
`the purchase order and that it was built accordingly and safely.
`
`1989-1991
`
`5.
`
`Subsequent
`
`to being a Systems Engineer from approximately
`
`I was an Engineering Manager at Applied Materials responsible for customer
`
`engineering specials CES. This included customization of equipment
`
`to meet
`
`3
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`
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`Dr. Glew Declaration re IPR 2016-00386
`U.S. Patent No. 8653672
`customer requests and specifications. The CES requests were diverse and covered
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`nearly all aspects of the equipment ranging from modifying process chambers gas
`
`panels wafer handlers/robotics wafer storage elevators sensors vacuum systems
`
`framing and other. We worked on very tight schedules and exercised disciplined
`
`project management.
`
`If our engineering work was not completed on time and the
`
`materials not procured then it would hold up the shipment of a multimillion dollar
`
`CVD process tool. Because we exercised disciplined project management such
`
`delays rarely happened. We also had to accurately estimate the cost of our work
`
`materials and labor because the CES projects were billed to the customer.
`
`6.
`
`Next I was the manager of the engineering design and support group
`
`for the CVD division of Applied Materials.
`
`In this capacity I was in charge of all
`
`of the designers and drafters generating all of the engineering drawings and
`
`reviewing all of the engineering design work.
`
`I am intimately familiar with
`
`computer aided design CAD and engineering documentation.
`
`7.
`
`In the early 1990s I was awarded the position of Core Technologist
`
`one of only 15 in Applied Materials. My area of expertise was gas and chemical
`
`ultra-high
`
`systems and components. The gas and chemical systems largely delivered
`
`purity fluids to the process chambers and reactors. Components used in the
`
`systems included the following valves flow controllers pressure regulators
`
`4
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`
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`Dr. Glew Declaration re IPR 2016-00386
`U.S. Patent No. 8653672
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`filters purifiers pressure transducers and related devices and systems as a whole.
`
`As a core technologist
`
`I was responsible for consulting with different divisions
`
`during the design of new products testing fluid delivery components reviewing
`
`invention disclosures and reviewing papers written by Applied Materials
`
`personnel holding meetings across the divisions for workers in the field setting
`
`technology trends with suppliers and reviewing technology trends with customers.
`
`Our different divisions included product
`
`lines such as at
`
`least CVD ETCH. CMP
`
`implant TFT and more. I also represented the company at industry consortium
`
`meetings. The core technology group met monthly with the president or other
`
`senior executives of the company.
`
`8.
`
`From 1994-1996 I managed a project
`
`funded by SEMATECH that I
`
`proposed to its factory working group. These efforts resulted in the publication of
`
`two SEMATECH technology transfer standards. The goal of this project was to
`
`develop industry standard methods to determine the effects of trace chemicals and
`
`contamination on semiconductor processing and on semiconductor equipment
`
`reliability. As part of this project
`
`I designed built and tested gas delivery systems
`
`1 SEMATECH stands for Semiconductor Manufacturing Technology a
`
`non-profit consortium that performs research into semiconductor manufacturing.
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`5
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`Dr. Glew Declaration re IPR 2016-00386
`U.S. Patent No. 8653672
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`including the components contained therein such as filter cartridges or assemblies
`
`flow controllers valves and pressure regulators and tested them to failure.
`
`Approximately 90% of wafer yield loss is from particles so the industry was very
`
`interested in the particle effect of the chemical delivery system. I also tested the
`
`effect of micro-contamination in the process gas stream on tungsten CVD
`
`deposition and on metal etching.
`
`In some of the tests we introduced controlled
`
`amounts of fluid into corrosive gas streams and then measured the effect on
`
`system reliability including particle generation.
`
`9.
`
`As part of the SEMATCH project we studied the effects of trace
`
`chemical contamination on tungsten CVD processing and on metal etching. We
`
`introduced trace chemicals into a standard process measured the amounts of
`in the process chamber by residual gas analyzer RGA and then
`
`chemical
`
`measured the resulting film quality and properties by multiple techniques and
`
`incorporation of the trace chemicals into the deposited layers.
`
`10.
`
`From 1994-1997 I was a CVD Supplier Quality Engineering Manager
`
`at Applied Materials. During this time I was the engineering manager responsible
`
`for the suppliers of the components of the fluid delivery systems such as valves
`
`flow controllers pressure regulators filters purifiers pressure transducers and
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`6
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`
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`Dr. Glew Declaration re IPR 2016-00386
`U.S. Patent No. 8653672
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`related devices and systems as a whole.
`
`I tested and evaluated fluid delivery
`
`components.
`
`I both supervised and personally conducted this testing.
`
`11.
`
`Since leaving Applied Materials in 1997 and until
`
`the present
`
`I have
`
`served as president of Glew Engineering Consulting Inc. Glew Engineering of
`
`Mountain View California. Glew Engineering provides consulting and
`
`engineering services relating to various technology or engineering areas including
`
`CVD technology. My responsibilities at Glew Engineering include acting as a
`
`consultant and as a principal managing the company.
`
`12.
`
`At Glew Engineering I have worked on projects that include project
`
`turnaround for failed projects testing / metrology gas panel design integrated
`
`circuits failures semiconductor equipment
`
`failures Excimer laser sources for
`
`photolithography KrF and Arf. I have assisted component suppliers and
`
`equipment suppliers and to a lesser extent investors.
`
`13.
`
`Glew Engineerings practice also includes multi-physics finite
`
`element analysis FEA computational
`
`fluid dynamics CFD and computer aided
`design CAD modeling. This is typically used for three dimensional modeling of
`
`equipment and processes and analysis of the heat transfer radiation fluid flow
`
`resultant stresses and strains from running such equipment and processes.
`
`7
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`
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`Dr. Glew Declaration re IPR 2016-00386
`U.S. Patent No. 8653672
`I am or have been a member of a number of professional
`
`14.
`
`organizations including American Society of Mechanical Engineers Materials
`
`Research Society IEEE Institute of Electrical and Electronics Engineers and
`
`International Microelectronics
`
`and Packaging Society IMAPS.
`
`In addition to
`
`being a member of these professional organizations I have served on committees
`
`at SEMATECH.
`
`15.
`
`I have authored or co-authored dozens of papers reports and
`
`presentations relating to semiconductor processing semiconductor equipment
`
`fluid delivery components in semiconductor processing and equipment reliability.
`
`16.
`
`I am an inventor of four issued U.S. Patents Nos. 6679476 related
`
`to a high-purity control valve 6204174 related to semiconductor processing
`
`7118090 related to a high-purity fluid control valve and 9224626 related to
`
`design of CVD equipment components.
`
`17.
`
`For more aspects of my qualifications and publications see my CV
`
`attached hereto as Exhibit A.
`
`1.
`
`Technology Background
`
`A.
`
`The Development Of Integrated Circuits
`
`18.
`
`Todays high-density integrated circuits trace their lineage back to the
`
`first electronic computers of the 1940s which used vacuum tubes to perform two
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`Dr. Glew Declaration re IPR 2016-00386
`U.S. Patent No. 8653672
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`important electrical
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`functions switching i.e.
`
`turning electrical current on and off
`
`and amplification increasing the amplitude of a signal while retaining its electrical
`
`characteristics. Ex. 2158 at 2. Because vacuum tubes were large power-hungry
`
`fragile and had limited operating time scientists soon developed solid-state
`
`transistors to perform the functions of and replace vacuum tubes. Ex. 2158 at 3.
`
`19. Where the earlier tubes used a vacuum to control
`
`the flow of
`
`electrons the first solid-state devices instead used semiconducting material. Ex.
`
`2158 at 3.
`
`In addition they were discrete because they had only one device
`
`such a transistor diode capacitor or resistor per semiconductor chip. Ex. 2158
`
`at 2-3. As a result more than one discrete semiconductor chip was needed to
`
`form a complete circuit. Ex. 2158 at 2. Although discrete solid-state transistors
`
`were an improvement over vacuum tubes the resulting circuits and computers
`
`were still
`
`relatively large. See Ex. 2158 at 2-3.
`
`20.
`
`In 1959 when Jack Kilby at Texas Instruments combined several
`
`transistors diodes and capacitors five components total to form a complete
`
`circuit on a single semiconducting chip which itself was used as a circuit resistor.
`
`Ex. 2158 at 4. Kilbys invention included an integrated circuit meaning an
`
`integration of a completed circuit in and on the same piece of semiconducting
`
`material. Ex. 2158 at 4.
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`Dr. Glew Declaration re IPR 2016-00386
`U.S. Patent No. 8653672
`The Kilby chip differed from modem integrated circuit chips in that it
`
`21.
`
`was not flat but instead connected its components using individual wires. Ex.
`
`2158 at 4-5. Scientists at Fairfield Camera developed a way of using metal
`
`patterns instead of individual wires to connect
`
`the circuit components thereby
`
`modifying the Kilby integrated circuit to the form still prevalent
`
`today.
`
`B.
`
`The Four Stages Of Integrated Circuit Manufacture
`
`22.
`
`In 1959 Kilbys first
`
`integrated circuit had five components. Ex.
`
`2158 at 4. Through continued efforts to improve manufacturing processes to allow
`
`smaller components and circuits by 1995 a single integrated circuit could include
`
`more than 250 million components. Ex. 2158 at 5-6.
`
`23.
`
`The intricate complex manufacturing process developed over the
`
`years for achieving such highly-dense integrated circuits can be generally divided
`into four distinct stages 1 material preparation 2 crystal growing and wafer
`preparation 3 wafer fabrication and 4 packaging. Ex. 2158 at 13. Around
`
`the 672 Patents filing date each of these steps was typically done by separate
`
`manufacturers at separate plants. Ex. 2158 at 12-13 15-16.
`
`24.
`
`In the first stage the semiconductor material itself
`
`is created. Ex.
`
`2158 at 13. For a silicon semiconductor
`
`the raw starting material is sand which is
`
`converted to pure silicon with a polysilicon structure. Ex. 2158 at 13.
`
`10
`
`
`
`25.
`
`In the second stage the semiconductor material is first
`
`formed into a
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`Dr. Glew Declaration re IPR 2016-00386
`U.S. Patent No. 8653672
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`silicon crystal with specific electrical and structural parameters and then sliced into
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`thin disks called wafers. Ex. 2158 at 13-14.
`
`In 1995 each of these generally
`
`round silicon wafers were generally 8 to 10 inches in diameter. Ex. 2158 at 8.
`
`Wafer manufacturers typically also oxidize each wafer before shipping because the
`
`resulting dielectric layer of silicon dioxide protects the wafer during shipment. Ex.
`
`2158 at 65.
`
`In addition because growing a dielectric layer on the wafer is usually
`
`the first step of wafer fabrication the next manufacturing stage buying a wafer
`
`that already has a silicon dioxide layer saves the fabricating company a
`
`manufacturing step. Ex. 2158 at 65.
`
`26.
`
`The third stage is wafer fabrication during which individual
`
`integrated circuits are formed on the surface of the silicon wafer. Ex. 2158 at 14.
`
`Around the filing date of the 672 Patent several hundred to several
`
`thousand
`
`identical
`
`integrated circuits could be formed on the surface of a single wafer. Ex.
`
`2158 at 14. The area of the wafer occupied by a single integrated circuit is known
`
`as a die or chip. Ex. 2158 at 14.
`
`27.
`
`Following fabrication each of the dies on the wafer is electrically
`
`tested in a process known as a wafer sort. Ex. 2158 at 14. Wafer sort is
`
`sometimes considered as the last step in the wafer fabrication sometimes as the
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`11
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`
`
`first step in the fourth and last manufacturing stage which is packaging. Ex. 2158
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`Dr. Glew Declaration re IPR 2016-00386
`U.S. Patent No. 8653672
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`at 14.
`
`28.
`
`In the packaging stage the wafer is separated into individual dies.
`
`Ex. 2158 at 14-15. Circa the 672 Patents priority date each individual die that
`
`passed the wafer sort typically would then be placed into an individual protective
`
`package. Ex. 2158 at 14-15. This protective package not only protects the
`
`integrated circuit chip from damage and contaminants it also provides an electrical
`
`lead system that allows the chip to be connected to a printed circuit board or
`
`directly into an electronic product. Ex. 2158 at 15.
`
`C.
`
`The Wafer Fabrication Stage Of Integrated Circuit
`Manufacture
`
`29.
`
`The third manufacturing stage wafer fabrication takes several
`
`thousand individual steps which can be divided into two primary phases front end
`
`of the line and back end of the line. Ex. 2158 at 14.
`
`In the front end of the line
`
`FEOL the transistors and other devices are formed in the wafers surface. Ex.
`
`2158 at 14.
`
`In the back end of line BEOL the devices are wired together with
`
`metallization processes and the circuit is then sealed with a protective layer. Ex.
`
`2158 at 14.
`
`30.
`
`The possibly thousands of steps involved in wafer fabrication are
`
`generally done using three categories of materials conductors semiconductor
`
`and
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`12
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`
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`dielectrics in four basic operations layering patterning doping heat treatments.
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`Dr. Glew Declaration re IPR 2016-00386
`U.S. Patent No. 8653672
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`See Ex. 2158 at 29-31 71.
`
`1.
`
`Wafer Fabrication Materials
`
`31.
`
`A materials conductivity
`
`is its ability to allow the flow of electrical
`
`current and materials may be divided into three categories based on their electrical
`
`conductivity conductors dielectrics and semiconductors. Ex. 2158 at 29-31.
`
`32.
`
`In a conductor electric current can flow freely in other words it has
`
`high conductivity
`
`and low resistance. Ex. 2158 at 29. Materials that are good
`
`conductors include copper silver and aluminum. Ex. 2158 at 29 398-400.
`
`33.
`
`A dielectric is a material at the opposite end of the conductivity
`
`spectrum from a conductor and has very low conductance
`
`and high resistance to
`
`the free flow of electrical current. Ex. 2158 at 30. Dielectrics are therefore used
`
`as insulators in electrical circuits and examples of dielectrics include glass such
`
`as silicon dioxide ceramics such as silicon nitride and plastics. Ex. 2158 at 30
`
`36 73.
`
`34.
`
`As the name implies semiconductors fall between conductors and
`
`dielectrics and have some conducting and some resisting ability. Ex. 215 8 at 31.
`
`Examples of semiconductors include silicon and germanium. Ex. 2158 at 31.
`
`2.
`
`Basic Wafer Fabrication Operations
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`13
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`Dr. Glew Declaration re IPR 2016-00386
`U.S. Patent No. 8653672
`To perform the possibly thousands of steps necessary for wafer
`
`35.
`
`fabrication manufacturers generally use four basic operations in different
`
`sequences and variations layering patterning doping and heat treatments. Ex.
`
`2158 at 71.
`
`36.
`
`Layering is the operation used to add thin layers to the wafer surface.
`
`Ex. 2158 at 72. For example the simple transistor structure shown in
`
`cross-section
`
`below shows a number of layers that have been added to the wafer surface.
`
`Ex. 2158 at 72. The layers may be conductors semiconductors or dielectrics
`
`and as discussed below they can have a large variety of functions and be made in a
`
`large variety of ways. Ex. 2158 at 72.
`
`Deposited
`Passivation
`
`Layer
`
`Deposited
`Metal
`
`Layer
`
`Grown
`Odde
`Layers
`
`-
`
`is
`
`s
`
`All
`
`P
`
`Figure 4.4 Cross section of completed metal gate
`MOS transistor with grown and deposited layers.
`
`37.
`
`Patterning is the series of steps that results in the removal of selected
`
`portions of one or more layers of materials that were added during one or more
`
`prior layering operations. Ex. 2158 at 72-73. This removal of select portions of
`
`layered material creates a pattern on the wafer surface. Ex. 2158 at 72-73. As
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`14
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`Dr. Glew Declaration re IPR 2016-00386
`U.S. Patent No. 8653672
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`illustrated below the patterning may result in one or more holes in the layered
`
`material or one or more remaining islands of material. Ex. 2158 at 72-73.
`
`1ýý Patfsrntng ýý
`
`Process
`
`Layered Wafer
`
`Figure 4.7 Patterning.
`
`Nole
`
`or
`
`1
`
`Island
`
`38.
`
`The repeated combination of layering and patterning in
`
`different sequences and variations is critical
`
`to the formation of the physical
`
`part parts of transistors diodes capacitors resistors and metal conduction
`
`systems in and on the wafer surface. Van Zant teaches
`
`these parts are created one layer at a time by the combination of
`
`putting a layer on the surface and removing portion with a patterning
`
`process to leave a specific shape. The goal of the patterning
`
`operations is to create the desired shapes in the exact dimensions
`
`feature size required by the circuit design and to locate them in their
`
`proper location on the wafer surface and in relation to the other parts.
`
`Ex. 2158 at 73.
`
`39.
`
`Doping is the process that puts specific amounts of dopants in the
`
`wafer surface through openings in the surface layer created by patterning. Ex.
`
`2158 at 73-74. The dopant
`
`is a substance inserted into a pure semiconductor
`
`to
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`15
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`Dr. Glew Declaration re IPR 2016-003 86
`U.S. Patent No. 8653672
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`produce a desired electronic characteristic. Ex. 2158 at 31-32. For example
`
`doping pure silicon can create areas of very precise resistivity values in the
`
`semiconductor material. Ex. 2158 at 32-34. Doping is also used to make
`
`polysilicon into a conductor or metal this is a different application than doping
`
`to modify a semiconductor.
`
`40.
`
`In addition doping is used to create pockets in the wafer surface that
`
`are either rich in electrons or rich in electrical holes. Ex. 2158 at 16. This is
`
`critical
`
`to the formation of the structure that makes semiconductor devices
`
`function the junction. Ex. 2158 at 16. A transistor requires two junctions to
`
`work and each junction is formed by creating a n-type region that is rich in
`
`electrons has negative polarity next to a p-type region that is rich in holes or
`
`put another way is missing electrons and thus has a positive polarity. Ex. 2158 at
`
`16.
`
`Junction
`
`----
`-
`- - -
`
`-
`
`P-N
`
`N-P
`
`Figure 1.24 P-N and N-P junctions.
`
`41.
`
`There are more than one doping techniques. One doping technique is
`
`thermal diffusion which is a chemical process that takes place when the wafer is
`
`heated to roughly 1000C and exposed to vapors of the proper dopant through a
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`Dr. Glew Declaration re IPR 2016-00386
`U.S. Patent No. 8653672
`hole created by layering and pattering. Ex. 2158 at 74. Another doping
`
`technique is ion implantation in which ionized dopants are shot at the wafer at
`
`high speeds like a bullet from a gun. Ex. 2158 at 74.
`
`Ion implantation is
`
`followed by a high temperature anneal. See Ex. 2159 at 494.
`
`70
`
`Thsnnal Ditiuaon
`
`Ion Source
`
`FIgura 4.8 Doping.
`
`Ion Impiantown
`
`42.
`
`Using thermal diffusion or ion implantation doping to create n-type
`
`and p-type pockets in the wafer surface allows the formation of the electrically
`
`active regions and N-P junctions required for operation of the transistors diodes
`
`capacitors and resistors of the integrated circuit. Ex. 2158 at 74.
`
`43.
`
`Heat treatments are the operations by which the wafer is heated and
`
`then cooled to achieve specific results. Ex. 2158 at 74. For example one
`
`important heat
`
`treatment
`
`takes place after ion implantation. Ex. 2158 at 75.
`
`Because implantation of the ionized dopant materials causes a disruption of the
`
`wafers crystal structure after the doping the wafer is heated to about 1000C to
`
`17
`
`
`
`repair the disruption. Ex. 2158 at 75. This type of restorative heat treatment
`
`is
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`Dr. Glew Declaration re IPR 2016-003 86
`U.S. Patent No. 8653672
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`known as an anneal. Ex. 2158 at 75.
`
`3.
`
`Exemplary Fabrication
`
`44.
`
`To illustrate how these different categories of materials and basic
`
`manufacturing operations can be used in fabrication the following is a simplified
`
`description of the primary steps for making a simple Metal Oxide Semiconductor
`
`MOS silicon-gate transistor structure.
`
`45.
`
`As depicted below the illustrative MOS silicon-gate transistor
`
`comprises three regions specifically an n-type source region and an n-type drain
`
`region formed in a p-type wafer. Ex. 2158 at 510-513. A doped polysilicon gate
`
`connects the source and the drain regions such that when threshold voltage is
`
`applied to the gate current travels from the source region through the gate to the
`
`drain. Ex. 2158 at 510-513.
`
`Drain
`
`Gate
`
`Source
`
`Channel
`
`17
`Figure 1618 MOS transistor operation.
`
`46.
`
`The following simplified steps which could in fact take thousands of
`
`discrete steps show how layering masking doping and heat treatments could be
`
`18
`
`
`
`used with dielectrics semiconductors
`
`Dr. Glew Declaration re IPR 2016-003 86
`U.S. Patent No. 8653672
`and conductors to make such a MOS
`
`silicon-gate transistor on a wafer surface. Ex. 2158 at 510-513.
`
`Starting Wafer
`
`L L
`
`47.
`
`Layering Operation To begin the front end of line phase of the
`
`fabrication a layer of dielectric silicon dioxide is grown on the silicon
`
`semiconductor wafer. Ex. 2158 at 80-8 1. This dielectric is called the field oxide
`
`and serves as a protective layer and doping barrier. Ex. 2158 at 80-81.
`
`Field Oxide
`
`48.
`
`Patterning Operation A patterning process is then used to create a
`
`hole in the field oxide dielectric that defines the location of the source gate and
`
`drain areas of the transistor. Ex. 2158 at 80-81.
`
`49.
`
`Layering Operation After the hole is made in the field oxide another
`
`dielectric is grown over the exposed silicon. Ex. 2158 at 80-81. This silicon
`
`dioxide layer will serve as the gate oxide. Ex. 2158 at 80-81.
`
`19
`
`
`
`Dr. Glew Declaration re IPR 2016-003 86
`U.S. Patent No. 8653672
`
`Mask and Grow Gate Oxide
`
`50.
`
`Layering Operation Another layering operation is then used to
`
`deposit a layer of polycrystalline silicon polysilicon over the gate oxide
`
`dielectric. Ex. 2158 at 80-8 1. This semiconductor material will become part of
`
`the gate structure. Ex. 2158 at 80-81.
`
`Deposit POlysilicon
`
`51.
`
`Patterning Operation Next patterning is used to create two openings
`
`in the masking oxide and polysilicon layers. Ex. 2158 at 80-8 1. These openings
`
`define the source and drain areas of the transistor. Ex. 2158 at 80-81.
`
`SouroalDraln Mask
`
`f7
`
`20
`
`
`
`Dr. Glew Declaration re IPR 2016-003 86
`U.S. Patent No. 8653672
`Doping Operation A doping operation is then used to create n-type
`
`52.
`
`pockets in the source and drain areas. Ex. 2158 at 80-81.
`
`53.
`
`Layering Operation Following the doping yet another layer of
`
`dielectric silicon dioxide is layered over the source and drain areas. Ex. 2158 at
`
`80-81.
`
`Source/Drain Doping and Reoxidetlon
`
`LLn -1
`
`P
`
`54.
`
`Patterning Operation Patterning is then used to create holes called
`
`contact holes through the dielectric in the source gate and drain areas. Ex.
`
`2158 at 80-81.
`
`55.
`
`Heat Treatment Operation The wafer is next heated at a very high
`
`temperature in a nitrogen gas atmosphere to create a layer of silicide over the
`
`exposed contacts in the source and drain regions. Ex. 2158 at 80-81. This
`
`silicide is necessary to ensure a good electrical contact with the metal
`
`layer that
`
`will be deposited in the following phases. Ex. 2158 at 80-81.
`
`56.
`
`This is the end of the front end of line phase the fabrication of the
`
`active and passive parts of the transistor and other components of the circuit and
`
`21
`
`
`
`Dr. Glew Declaration re IPR 2016-00386
`U.S. Patent No. 8653672
`the next step marks the beginning of the back end of line phase the addition of
`
`the metal systems necessary to connect
`
`the different components. Ex. 2158 at 14
`
`395.
`
`57.
`
`Layering Operation In the first step of the back end of line phase a
`
`thin layer of conducting material such as an aluminum alloy is deposited over the
`
`entire wafer. Ex. 2158 at 80-81.
`
`58.
`
`Patterning Operation After the deposition of the aluminum alloy that
`
`metallization layer is patterned so as to leave only the portions necessary to
`
`connect
`
`the surface components. Ex. 2158 at 80-81.
`Contact Mk vW Matauization
`
`Metal
`
`i
`
`h
`
`P
`
`59.
`
`Layering Operation The final
`
`layer is a protective layer known as the
`
`passivation layer not shown in the above figures which is often a dielectric and
`
`is used to protect
`
`the components during testing packaging and use. Ex. 2158 at
`
`80-81.
`
`60.
`
`As this transistor is being formed the other components required for
`
`the circuit such as diodes resistors capacitors and other transistors are also
`
`22
`
`
`
`Dr. Glew Declaration re IPR 2016-00386
`U.S. Patent No. 8653672
`formed in other areas of the circuit in a similar manner using similar operations.
`
`Ex. 2158 at 82.
`
`D.
`
`Different Techniques For Producing And Layering Dielectrics
`
`61.
`
`As the foregoing example illustrates different dielectric materials are
`
`layered throughout
`
`the fabrication process with each dielectric layer having a
`
`different location each being created at a different stage and each serving a
`
`different specific purpose. Ex. 2158 at 72-73 79 81-82. As a result each
`
`layered dielectric needs to have certain specific properties depending on where
`
`and when it
`
`is produced and the purposes it must serve. Ex. 2162 at 47-48 of 895
`
`see also Ex. 2164 at 7821-791 There is likely quite a long list of factors that go
`
`into choosing between dielectrics and an engineer would weigh those using his
`
`knowledge and skills..
`
`62.
`
`These dielectrics can be produced and layered using a large number of
`
`techniques and the particular technique used will greatly impact
`
`the properties of
`
`the resulting dielectric and therefore its usefulness for any particular dielectric
`
`layer and purpose. For example dielectric silicon dioxide layers can be produced
`
`and applied in hundreds of different ways each resulting in a silicon dioxide with
`
`different properties and potential uses. Ex. 2158 at 154 Ex. 2146 at 225 306
`
`Ex. 2159 at 55.
`
`23
`
`
`
`63.
`
`For these reasons dielectrics are not created equal each silicon
`
`Dr. Glew Declaration re IPR 2016-00386
`U.S. Patent No. 8653672
`
`dioxide dielectric for example may have the same chemical formula-SI02-but
`
`any one SiO2 can have vastly different characteristics and behaviors from any other
`
`SiO2 depending on how it
`
`is made and its resulting molecular structure and form.
`
`Ex. 2165 at 72 74-76 of 700 Ex. 2164 at 5414-18.
`
`Indeed silicon dioxide
`
`more than almost any material exists in many polymorphs. Ex. 2163 at 9. The
`
`following are just a few examples of the many different structures that SiO2 can
`
`take depending on how it
`
`is made
`
`24
`
`
`
`Dr. Glew Declaration re IPR 2016-003 86
`U.S. Patent No. 8653672
`
`Ex. 2163 at 9 10 of 13.
`
`64.
`
`There is many variations in the way silicon dioxides are formed
`
`and the properties of the silicon dioxide may be different depending on the
`
`details of the formulation and processing parameters used. Ex. 2164 at
`
`1338-20.
`
`in semiconductor
`
`fabrication fall
`
`The primary techniques for forming and layering different types of dielectrics
`into one of two general categories 1 growing
`dielectrics and 2 depositing dielectrics. Ex. 2158 at 72.
`
`1.
`
`Growing Dielectrics Using Thermal Oxidation
`
`65.
`
`To grow a dielectric is to form it from and on the material of the wafer
`
`surface itself. Ex. 2158 at 157-158. There a numerous ways of growing
`
`dielectrics including thermal oxidation and nitridation. Ex. 2158 at 72.
`
`66.
`
`Thermal oxidation is a prevalent
`
`technique for growing a silicon
`
`dioxide dielectric from a silicon wafer. Ex. 2158 at 72 157. Oxidation is
`
`performed by exposing a silicon wafers surface to oxygen which converts the
`25
`
`
`
`Dr. Glew Declaration re IPR 2016-00386
`U.S. Patent No. 8653672
`pure silicon into silicon dioxide. Ex. 2158 at 157 Ex. 2159 at 53. This can be
`
`done by exposing a silicon wafer to air dry oxidation or water wet oxidation.
`
`In fabrication this exposure is done at temperatures between 900
`Ex. 2159 at 53.
`C and 1200 C. Ex. 2158 at 157.
`
`67.
`
`As a result of the growth conditions of thermal oxides the resulting
`
`silicon dioxide possesses a very dense and pure molecular structure. Ex. 2158 at
`
`Ex. 2159 at 53. Purity is equivalent
`
`to having no or extremely low levels of
`
`unwanted chemical elements or molecules in the film and the exclusion of mobile
`
`ionic contaminants and particulates. Ex. 2158 at 363.
`
`68.
`
`Another characteristic of silicon dioxides grown using thermal
`
`oxidation is that they exhibit internal compressive stress when returned to lower
`
`temperatures. Ex. 2159 at p. 58-59 Ex. 1040 at 128 Ex. 2160 at 233. Stress is
`
`an internal
`
`force per area on a material and may be either tensile or compressive.
`
`Ex. 1040 at 114.
`
`If the force pushes inwardly along a layers horizontal plane it
`
`creates compression and is a compressive stress. Ex. 1040 at 114.
`
`If the force
`
`pulls outwardly along a layers horizontal plane it creates tension and is a tensile
`
`stress. Ex. 1040 at 114. Tensile stress can cause cracking far more readily than
`
`compression while excess compressive stress can cause buckling. Ex. 1040 at
`
`114 117 Ex. 2146 at 195 the preferred stress in. a dielectric is
`
`26
`
`
`
`Dr. Glew Declaration re IPR 2016-003 86
`U.S. Patent No. 8653672
`
`compressive... since dielectric films under tensile stress exhibit more of a tendency
`
`to crack. Silicon fractures approximately four times more readily in tension
`
`than compression.
`
`69.
`
`Other typical and important characteristics of silicon dioxides grown
`
`using thermal oxidation include the ability to withstand high temperatures without
`
`changing its form and properties of good adhesion the ability to stick well to
`
`other materials su
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