r
`
`EXHIBIT NO.
`
`M. 0.
`
`onnor
`
`EXHIBIT NO.
`
`M. 0. OConnor
`
`2001 Tiechnology
`dm P f
`R
`0a
`OP
`a
`Semiconductops JM
`
`I
`
`Ilil uv
`
`M
`
`The International Technology Roadmap for Semiconductors ITRS is a
`collaborative effort within the semiconductor
`the
`industry to confront
`challenges implicit in Moores law. Representatives of the International
`Technology Working Groups for Design and Test outline some of the
`contributions made by 839 international experts as they sought to reach
`an industry-wide consensus on its RD needs out to a 15-year horizon.
`
`mar-Intel
`con-Over
`shar-tronic
`con-Rodgers
`break-Yervant
`high-Zorian
`under-edition
`rep-International
`
`Alan Allan
`
`Intel
`
`Don
`Eden feld
`
`William H.
`
`Joyner Jr.
`Semiconductor
`
`Research Corp.
`
`Andrew B.
`Kahng
`University of
`
`California
`San Diego
`
`Mike
`
`Intel
`
`LogicVision
`
`nificant
`
`or the past 40 years the semiconductor
`industry has distinguished itself by the rapid
`pace of improvement
`in its products. This
`growth has resulted principally from the
`industrys ability to decrease exponentially
`the minimum feature sizes it uses to fabricate inte-
`grated circuits commonly referred to as Moores
`law. The most significant
`trend for society is the
`decreasing cost per function which has led to sig-
`improvements in productivity and quality
`of life through proliferation of computers elec-
`communication and consumer electronics.
`two decades the phenomenal
`the past
`increase in research and development
`investments
`has motivated industry collaboration and spawned
`many partnerships consortia and other coopera-
`tive ventures. The International Technology Road-
`ITRS is an especially
`map for Semiconductors
`successful worldwide cooperation that presents an
`industry-wide consensus on the best current esti-
`mate of its RD needs out to a 15-year horizon.
`
`As such the Roadmap provides a guide to the efforts
`of companies research organizations and govern-
`ments to improve the quality of RD investment
`
`decisions made at all
`levels and it has helped chan-
`nel efforts to areas that truly need research break-
`
`throughs.
`
`Excerpts from the Executive Summary and three chapters of The
`2001
`Technology Roadmap for Semiconductors
`International Sematech Austin Texas 2001.
`
`in 1992 as
`Since its
`the National
`inception
`Technology Roadmap for Semiconductors NTRS
`the Roadmaps basic premise has been that scaling
`of microelectronics would continue to reduce the
`cost per function by 25 percent and promote
`ket growth for integrated circuits by 15 percent
`annually. Thus the Roadmap is put together in the
`spirit of a challenge What
`technical capabilities
`does the industry need to develop to continue to
`follow Moores law
`The semiconductor
`
`industry is increasingly
`ing its research efforts via mechanisms such as
`sortia and collaborations with suppliers in a
`environment. The ITRS identifies
`precompetitive
`the principal technology needs to guide this shared
`It does this in two ways by showing the
`technology solutions currently under
`targets that
`development need to meet and by indicating where
`there are no known solutions of reasonable
`fidence to continued scaling in some aspects of
`semiconductor
`technology. Because they clearly
`warn where historical progress trends might end if
`the industry doesnt achieve
`some real
`throughs in the future these latter indicators
`light serious and exciting challenges.
`As the Overall Roadmap Process and Structure
`indicates the 2001 Roadmap is notable
`sidebar
`because it was developed with truly international
`representation. The contributions outlined here
`resent but a small portion of this immense
`taking over the past two years.
`
`research.
`
`Computer
`
`0018-9162/02/$17.00
`
`2002 IEEE
`
`TSMC 1022
`TSMC v. GODO KAISHA
`IPR2017-01841
`
`

`

`rep-resents
`tech-nology
`corre-random
`lith-industry.
`individ-developed
`corre-previous
`indus-define
`
`Overall Roadmap Process and Structure
`
`The 2001 International Technology Roadmap for Semiconductors
`an attempt to incorporate broad international
`input
`widest possible consensus on the semiconductor industrys future
`
`to build the
`
`needs.
`
`A corresponding International Technology Working Group ITWG
`focus ITVIGs
`area chapter. The eight
`writes each ITRS technology
`that sequentially span product flow design
`spond to typical suhactivities
`test process integration devices and structures front-end processes
`ography interconnects factory integration and assembly and packaging.
`ITWGs represent supporting activities
`Four crosscut
`ually overlap with product flow at multiple critical points environment
`safety and health defect reduction metrology modeling and simulation.
`ITWG receives input
`Each
`from the Technology Working Groups
`TWGs in five geographical
`regions Europe Japan Korea Taiwan and
`the US. One to two delegates represent each regional TWG on the
`sponding ITWG. The regional TWGs are composed of experts from
`try including chip-makers as well as equipment and materials suppliers
`In 2001 a total of
`research organizations and universities.
`government
`839 experts from the five regions volunteered their services
`in the 12 ITWGs.
`In addition each TWG incorporates
`feedback gathered from an even larger
`community through sub-TWG meetings and public Roadmap workshops.
`
`that tend to
`
`Historically developers have recognized dynamic
`access memory DRAM products as the
`technology drivers for the entire semiconductor
`Prior to the early 1990s logic technology
`as exemplified by microprocessing units MPUs
`at a slower pace than DRAM technol-
`ogy. During the past few years the development
`rate of new technologies
`used to manufacture
`microprocessors has accelerated and DRAM prod-
`uct generation every three years at four times the
`density has become obsolete as a way to
`technology nodes. A technology node
`resents the creation of significant
`technology
`progress governed by the smallest feature printed-
`approximately 70 percent of the preceding node.
`
`rep-
`
`Microprocessor products are closing the historical
`half-pitch technology gap versus DRAM and are
`now driving the leading-edge
`lithography tools and
`processes-particularly with respect
`to the printed
`in resist and physical gate length. As Figure 1
`shows the 2001 Roadmap explicitly acknowledges
`that DRAM and microprocessor products share the
`technology leadership role with MPU half-pitch
`In fact MPU half-pitch will
`closely tracking DRAM.
`catch up to DRAM half-pitch in 2004 the previous
`edition of the ITRS had projected this convergence
`for 2015.
`
`1000
`
`a
`
`100
`
`1
`
`2-year
`node cycle
`
`3-year
`node cycle
`
`2001 DRAM half-pitch
`Q 2001 MPU/ASIC half pitch
`1999 ITRS DRAM half pitch
`
`necessary
`
`Despite the continuous reduction in feature size of
`about 30 percent every three years the size of first
`DRAM product demonstration
`has continued to
`double every six years an increase of about 12 per-
`cent per year. This increase in chip area has been
`to accommodate
`59 percent more
`per year in accordance
`bits/capacitors/transistors
`with Moores law historically doubling functions
`per chip every 1.5 to 2 years. However
`to maintain
`historical trend of reducing the cost/function
`ratio by 25 to 30 percent per year the semiconduc-
`tor industry must continuously enhance equipment
`
`10
`1995
`
`1998
`
`2001
`
`2004
`
`2007
`
`2010
`
`2013
`
`2016
`
`Year of production
`
`In addition to the need to increase functionality
`while exponentially
`cost per function
`decreasing
`there is also a market demand for higher-perfor-
`products. Just as Moores law
`mance cost-effective
`functions per chip will double every
`predicts that
`1.5 to 2 years to keep up with consumer demand
`demand for processing
`there is a corresponding
`rates. In
`electrical signals at progressively higher
`the case of MPUs processor instructions per sec-
`and have also historically doubled every 1.5 to 2
`
`Figure 1.
`
`ITRS
`
`Roadmap
`
`tion continues with
`
`MPUhalf--pitch
`
`trends closely
`
`trackingDRAMand
`
`catching up to it in
`2004 instead of
`
`2015 as previously
`
`projected in the
`1999 Roadmap.
`
`accelera-per
`
`productivity increase manufacturing yields use the
`largest wafer size available and most important
`increase the number of chips available on a wafer.
`Both the DRAM and MPU models depend upon
`achieving aggressive design and
`process improvement
`If those targets slip pressure will
`increase to
`targets.
`print chip sizes larger than the present Roadmap pre-
`For MPU products increased processing power
`diets or further slow the rate of Moores law on-chip
`measured in millions of instructions per second
`functionality. Either of these consequences will have
`a negative impact upon cost-per-function reduction MIPs is accomplished through a combination of
`raw technology
`rates-the classical measure of our industrys pro-
`clock frequency
`performance
`improvement and competitiveness.
`multiplied by architectural performance
`
`years.
`
`ductivity
`
`instruc-January
`
`2002
`
`

`

`Table 1. Roadmap trends 2001-2016 for scaling cost power.
`
`Production year
`
`Chip performance characteristics
`
`2001
`
`2002
`
`2003
`
`2004
`
`2005
`
`2006
`
`2007
`
`2010
`
`2013
`
`2016
`
`130
`
`150
`
`90
`
`65
`
`115
`
`130
`
`75
`
`53
`
`100
`
`107
`
`65
`
`45
`
`90
`
`90
`
`53
`
`37
`
`80
`
`80
`
`45
`
`32
`
`70
`
`70
`
`40
`
`28
`
`65
`
`65
`
`35
`
`25
`
`45
`
`45
`
`25
`
`18
`
`32
`
`32
`
`18
`
`13
`
`22
`
`22
`
`13
`
`9
`
`6739
`
`11511
`
`19348
`
`28751
`
`DRAM half-pitch
`MPU/ASIC half-pitch
`MPU printed gate length
`MPU physical gate length
`On-chip local clock MHz
`Maximum number wiring levels
`
`Cost per function microcents
`
`DRAM cost/bit
`CP-MPU cost/transistor
`HP-MPU cost/transistor
`
`Test cost $K/pin
`
`1684
`
`7
`
`7.7
`
`107
`
`97
`
`2317
`
`3088
`
`3990
`
`5173
`
`5631
`
`8
`
`8
`
`8
`
`9
`
`9
`
`9
`
`10
`
`10
`
`10
`
`5.4
`
`75
`
`69
`
`3.8
`
`53
`
`49
`
`2.7
`
`38
`
`34
`
`1.9
`
`27
`
`24
`
`1.4
`
`19
`
`17
`
`0.96
`
`13.3
`
`12
`
`0.34
`
`4.71
`
`4.31
`
`0.12
`
`1.66
`
`1.52
`
`0.042
`
`0.590
`
`0.540
`
`3.0
`
`3.0
`
`3.0
`
`4.0
`
`4.0
`
`4.0
`
`Volume tester cost per high-frequency
`
`4.0
`
`3.0
`
`3.0
`
`3.0
`
`signal pin
`
`HP-ASIC-maximum
`
`Volume tester cost per high-frequency
`
`signal pin
`
`HP-ASIC-minimum
`
`Volume tester cost/pin CP-MPU
`
`Power supply voltage V
`
`1.0
`
`1.0
`
`1.0
`
`1.0
`
`1.0
`
`1.0
`
`1.0
`
`2.0
`
`3.0
`
`4.0
`
`7.0
`
`6.5
`
`6.0
`
`5.5
`
`5.0
`
`4.5
`
`4.0
`
`4.0
`
`2.0
`
`1.5
`
`Vdd high performance
`
`Vdd low operating power high Vdd
`
`1.1
`
`1.2
`
`1.0
`
`1.2
`
`1.0
`
`1.1
`
`1.0
`
`1.1
`
`0.9
`
`1.0
`
`0.9
`
`1.0
`
`0.7
`
`0.9
`
`0.6
`
`0.8
`
`0.5
`
`0.7
`
`0.4
`
`0.6
`
`transistors
`
`1.1
`
`1.1
`
`Vdd low standby power high Vdd
`
`1.2
`
`1.2
`
`1.2
`
`1.2
`
`1.2
`
`1.2
`
`1.1
`
`1.1
`
`transistors
`
`Allowable maximum power
`with heatsink W
`Cost-performance W
`
`High-performance
`
`Battery W-handheld
`
`130
`
`140
`
`150
`
`160
`
`170
`
`180
`
`190
`
`218
`
`251
`
`288
`
`61
`
`2.4
`
`75
`
`2.6
`
`81
`
`2.8
`
`85
`
`3.2
`
`92
`
`3.2
`
`98
`
`3.5
`
`104
`
`3.5
`
`120
`
`3.0
`
`138
`
`3.0
`
`158
`
`3.0
`
`dif-higher
`cou-increasing
`
`tions per clock cycle. The need for a progressively
`frequency associated with an
`operational
`average chip size will continue to fuel
`the development of novel process design and pack-
`
`In general signal propagation becomes more
`and inductive
`ficult due to increased capacitive
`piing which degrades edge rates and causes both
`timing uncertainty and potential
`logic errors.
`Additional signal degradation is associated with the
`inductance
`of wire bonds and package leads. Direct
`chip attachment may eventually be required for
`adequate mitigation of parasitic effects caused by
`
`the package.
`
`aging techniques.
`Table 1 reflects these considerations. The highest
`frequency obtainable in each product generation is
`related to the intrinsic transistor performance on-
`chip local clock and this relationship becomes
`even more direct as microarchitectural
`knobs for
`example pipelining become fully exploited.
`To optimize signal and power distribution across
`the chip the number of interconnect
`layers is likely
`to continue to increase. As interconnect
`size down-
`
`also continues the chip fabrication process
`will adopt wider use of copper low resistivity and
`intermetal
`insulating materials of pro-
`constant x - 2-3.
`gressively lower dielectric
`Designers will also use multiplexing techniques to
`increase the chip-to-board operating frequency
`
`off-chip.
`
`Computer
`
`indus-scaling
`manu-various
`
`Table
`
`trends. The ability to
`1 also shows cost
`reduce the cost per function by 25 to 30 percent each
`year is a unique feature of the semiconductor
`try and is the fundamental engine behind its growth.
`
`In support of this cost reduction RD and
`
`facturing require a continuously increasing financial
`investment. Even on a per-factory basis the capital
`cost of manufacturing continues
`to escalate.
`the 2001 Roadmap indicates
`However
`that logic
`transistor size is improving only at the rate of the
`
`

`

`inter-the
`manu-to
`high-vol-lent
`cir-functions
`automa-cost
`inte-ware
`power-ATE
`man-plexities.
`
`High-volume custom MPUs incorporate
`the most aggressive design styles and
`
`It
`
`is for these
`facturing technologies.
`ume parts that developers make changes
`to
`flow create new design styles
`the manufacturing
`and supporting tools the large revenue streams can
`pay for new tool creation and uncover subtle
`cuits issues. Thus while developing custom MPU
`designs is extremely labor intensive they offer new
`design and fabrication technology and new
`tion methods that
`the entire industry leverages.
`MPUs are part of the segment that drives
`gration density and design complexity the
`
`the set of system drivers that previous ITRS
`lithography 0.7 times linearly and 0.5 times area
`editions used providing quantitative
`reduction every technology node. Therefore to keep
`MPU chip sizes flat the number of transistors
`nally self-consistent models that support
`extrapolation and adapt more smoothly to
`can double only every technology node. Because the
`developments. Due to
`node rate is projected to return to a three-
`future technology
`technology
`DRAMs well-understood commodity nature
`year cycle after 2001 the transistors per MPU chip
`can double only every three years after 2001. DRAM the ITRS focuses
`custom
`on high-volume
`microprocessors AMS and SoC drivers.
`memory bit cell design improvements are also slow-
`ing down and the bits-per-chip rate will also be
`slowing in the future to keep chip sizes under control.
`for the decrease in DRAM and MPU
`To compensate
`functions per chip there will be increasing pressure
`find alternative enhancements
`from the equiva-
`productivity scaling benefits of chip and system-
`level architecture and designs.
`Even though the rate of increase in on-chip coin-
`plexity could slow in the future the number of
`per chip will continue to grow. Increased
`chip functions drive an increase of test-method
`complexity which in the past resulted in nonlinear
`to manufacturing
`increases
`test
`in capital for
`additional ATE automated test equipment hard-
`and longer device test times. Even though
`cost-per-pin is forecast to decline this is more
`than offset by increased device pin counts and com-
`Built-in self-test BIST and design for
`testability DFT must move forward to enable crit-
`ical manufacturing test cost scaling-for example
`reduced-pin-count ATEs.
`require advances
`Meeting these challenges will
`on all fronts-particularly
`new front-end processes
`that overcome the limitations of current comple-
`mentary metal-oxide semiconductor CMOS tech-
`nology-but here we focus on challenges in the
`design and test arena that
`is more relevant
`to
`Computers readership.
`
`9t functions per
`
`hip increases
`
`vesting the final
`
`71cts becomes
`
`reaSingly
`
`cflcult and
`
`speed performance envelope large-team design
`process efficiency test and verification power
`agement and packaged
`system cost. Historically
`there have been two types of MPUs over the course
`of the Roadmap cost-performance CP desktop
`and high-performance HP servers with constant
`die areas of 140 mm2 and 310 mm2 respectively.
`to previous ITRS models the core
`In contrast
`message in the 2001 model
`is that power and cost
`are strong limiters of die size. Future MPUs will
`likely require a merged desktop-server category the
`distinction is already blurred today and a mobile
`high-perfor-mance
`category essentially a low-power
`SoC.
`
`multi-Previous
`proces-is
`scal-The
`
`focused
`
`on MPUs
`ITRS editions
`DRAM and application-specific
`integrated circuit
`ASIC product classes with only cursory mention
`of system-on-chip SoC and analog/mixed-signal
`AMS circuits. The unstated assumption was that
`technological advances only needed to be linear and
`that all semiconductor products would deploy them.
`Today the introduction of new technology solutions
`increasingly application driven with products for
`different markets using different combinations of
`technologies at different times Battery-powered
`mobile devices are replacing wall-plugged servers
`and SoC and system-in-package designs that incor-
`porate building blocks from multiple sources are
`supplanting in-house single-source chip designs.
`2001 ITRS updates and more clearly defines
`
`Design productivity power management
`core organization I/O bandwidth and circuit and
`process technology are key contexts for the future
`evolution of the traditional MPU.
`The complexity and cost of
`design and verification of MPU products
`have
`rapidly increased to the point where developers
`devote thousands of engineer-years and a design
`team of hundreds to a single design yet
`sors reach market with hundreds of bugs.
`Power dissipation
`limits of
`cost-effective packaging estimated to reach 50 W
`per cm2 for forced-air cooling by the end of the
`Roadmap cannot continue to support high-supply
`scale at 0.85
`voltages. Historically these voltages
`times per generation instead of 0.7 times ideal
`ing and frequencies historically scale by 2 times per
`
`January 2002
`
`

`

`archi-package
`vari-age
`in-activity
`inter-encounter
`per-nitude
`re-general-purpose
`sin-competition
`
`for a while integrating a large number of these I/Os
`on a single chip presents challenges for design each
`circuit must be very low power
`test the tester
`needs to run this fast and packaging packages
`must act as balanced
`transmission lines including
`the connection to the chip and the board.
`The growing process
`variability implicit in feature size and device
`tecture roadmaps including thinner and less reliable
`
`lithography
`gate oxides subwavelength optical
`requiring aggressive reticle enhancement and
`creased vulnerability to atomic-scale process
`ability severely threatens parametric yield dollar per
`wafer after bin-sorting. This will require more
`vention at the circuit and architecture design levels.
`While using dynamic circuits is attractive for
`formance in lower-frequency
`or clock-gated
`gimes noise margin and power dissipation concerns
`this approach. Error-correction
`may limit
`for
`
`generation instead of the ideal 1.4 times.
`Past MPU system driver clock
`frequency
`future CMOS
`trends were interpreted as
`device performance switching speed require-
`and
`ments leading to large off-currents
`extremely thin gate oxides. Given such devices
`MPUs that simply continue using existing cir-
`cult and architecture
`techniques would exceed
`power limits by a factor of more than
`the Roadmap.
`25
`end of
`times by the
`Alternatively MPU logic content or
`logic
`would need to decrease to match pack-
`constraints. Portable low-power embedded sys-
`tems have more stringent power
`limits and will
`such obstacles even earlier than MPUs.
`Power efficiencies
`are up to four orders of mag-
`greater for direct-mapped hardware than for
`MPUs and this gap is increasing.
`As a result traditional processing cores will
`from application-specific or reconfig-
`urable processing engines for space on future SoC-
`like MPUs.
`
`face
`
`b
`
`w6w h
`
`ill
`
`limits of
`
`cost-effect
`
`packaging cann..
`
`continue to supp
`
`high-suppl
`
`increase as will using
`in logic will
`upset
`gle-event
`redundancy and reconfigurability to compensate
`for
`yield loss. Power management will
`require using a
`combination of techniques
`from several component
`technologies. Application OS and architecture
`optimizations include parallelism adaptive voltage
`and frequency scaling. The increased use of
`innovation.
`on-insulator techniques is a process
`Circuit design optimization techniques
`simultaneous use of multi-Vth multi-Vdd
`mum-energy sizing under throughput constraints
`and multidomain clock gating and scheduling.
`
`include the
`
`AMS designs include RF analog and
`digital and digital-to-analog converters. At least
`part of the AMS chip needs to measure signals with
`high precision. Because analog chips have very
`ferent design and process technology demands than
`digital circuits scaling them into new technologies
`challenge. While technology scaling is
`is a difficult
`always desirable for digital circuits due to reduced
`power area and delay it
`is not necessarily helpful
`for analog circuits in which dealing with precision
`requirements or signals from a fixed voltage range
`In general AMS circuits
`is more difficult.
`for
`example RF and embedded
`passives and process
`technologies for example silicon-germanium
`to cost-effective CMOS
`
`sent severe challenges
`
`gration.
`The need for precision also affects tool
`ments for analog design. Digital circuit design
`lows a set of rules that allow logic gates to function
`correctly As long as the design follows these rules
`precise calculation
`of exact signal values
`is not
`
`dif-ing
`pre-troller
`inte-latency.
`fol-speed
`require-Many
`
`silicon-applications
`mini-manufacturing
`bet-ter
`analog-to-pipelining
`
`In an MPU with multiple
`cores per die the cores can be smaller and faster to
`interconnect scaling and develop-
`counter global
`ers can optimize them for reuse across multiple
`and configurations.
`In addition to allowing power savings multicore
`architectures may exploit redundancy to improve
`yield. Future MPU organization will
`increase the on-chip memory hierarchy
`likely
`which if only in a relatively trivial way affords
`and total chip power.
`control of
`leakage
`Evolutionary microarchitecture
`changes-super-
`superscalar predictive methods-appear
`to be running out of steam. Thus more multi-
`threading support will emerge for parallel process-
`as well as more complex hardwired functions
`for networking graphics
`or specialized engines
`security and so forth. Flexibility-efficiency trade-
`offs shift away from general-purpose processing.
`In MPU systems I/O pins mainly
`to both high-level cache memory and main-
`Increased processor performance
`system memory.
`has been pushing I/O bandwidth requirements. L2
`or L3 caches
`traditionally use the highest-bandwidth
`port but recent designs integrate the memory con-
`on the processor die to reduce memory
`These direct memory interfaces require
`more I/O bandwidth than the cache interface.
`designs replace the system bus with high-
`interfaces that require much
`point-to-point
`I/O design exceeding gigabit-per-second
`rates. While serial
`links have achieved
`
`connect
`
`faster
`
`Computer
`
`these rates
`
`

`

`mixed-include
`sub-strate
`
`analog circuit blocks are major obstacles
`low-cost and efficient scaling of mixed-signal
`
`to
`
`functions.
`
`issues
`
`needed. Analog designers on the other hand must
`be concerned with a number of second-order effects
`to obtain the required precision. Relevant
`coupling capacitance inductance and
`and asymmetries local variation of supplies
`as well as implantation alignment etching and
`other fabrication effects. Analysis tools for these
`issues are mostly in place but require expert users
`synthesis tools are at best preliminary. Manu-
`for AMS circuits
`
`facturing
`
`test
`
`is essentially
`
`sties a
`
`slgný
`
`isist i
`
`highs
`
`s
`
`apply voltage and
`
`pays unchanged
`
`cross multiple
`l technology
`
`A yet-evolving product class SoC design
`integrates pieces of technology from other sys-
`tem driver classes-for example MPU mem
`ory AMS and reprogrammable fabrics-into
`a wide range of high-complexity high-value
`semiconductor products. Typically SoC man-
`ufacturing and design technologies were orig-
`custom
`inally developed for high-volume
`drivers. Since reduced design costs and higher
`levels of system integration are its principal
`goals the SoC driver class most closely
`the ASIC category.
`The primary difference between ASIC and SoC
`designs is that SoCs emphasize reusing intellectual
`property IP to improve productivity.
`In addition
`SoC integration potentially encompasses
`neous technologies. SoCs reuse both analog and
`high-volume custom cores as well as blocks of
`ware technology. The primary benefit of SoC designs
`is that reusing blocks is more efficient and cost
`from-scratch designs.
`tive than using equivalent
`Cost considerations drive the deployment of
`power process and low-cost packaging solutions
`turnaround time TAT design
`along with fast
`methodologies. The latter in turn require new
`standards and methodologies for IP description IP
`test including BIST and self-repair block
`face synthesis and so forth. In addition to the need
`increasing leakage and crosstalk arising from for chip-package cooptimization integration
`siderations drive the demand for heterogeneous
`integration which requires more accurate
`technologies such as flash DRAM MEMS
`crosstalk and delay modeling and fully differ-
`electric RAM FERAM magnetoresistive RAM
`design for RF circuits and
`shortage of design skills and productivity aris- MRAM and chemical sensors that
`implement
`ing from lack of training and poor automa-
`particular system components. Thus SoC is the
`and basic
`which requires education
`of multiple technologies not
`ver for convergence
`only in the same system package but also
`design tools research.
`in the same manufacturing process.
`An ideal design process would reuse existing
`Because SoC designs offer low-cost rapid system
`implementation power management and design
`mixed-signal designs and adjust parameters to meet
`a given SoC and
`productivity have important implications for the
`interface specifications between
`design space. The 2001 ITRS defines a
`the outside world. However such reuse depends on
`achievable
`a second type of MOSFET metal oxide semicon-
`low-power SoC LP-SoC PDA
`prototypical
`cation and applies two analyses to obtain future
`transistor that does not scale its
`field-effect
`maximum operating voltage. This has led to the
`power management requirements. The first
`sis accepts the system specifications 0.1 W peak
`specification of a mixed-signal CMOS
`power and 2.1 mW standby power in a top-down
`transistor that uses a higher analog supply voltage
`fashion. The second approach derives the power
`and stays unchanged
`across multiple digital
`tech-
`nology generations. Even with such a device how-
`requirements bottom-up from the implied logic and
`ever voltage reduction and development
`time of memory content as well as process and circuit
`
`resem-bles
`
`unsolved.
`For most of todays mixed-signal designs-par-
`ticularly classical analog designs-a voltage differ-
`ence represents the processed signal and the supply
`voltage determines the maximum signal. The most
`daunting mixed-signal challenges
`are
`
`decreasing supply voltage which requires cur-
`rent-mode circuits charge pumps for voltage
`and thorough optimization of
`enhancement
`
`voltage levels in standard-cell circuits
`relative parametric variations
`increasing
`which requires active mismatch compensation
`tradeoffs of speed versus resolution
`increasing numbers of analog transistors per
`which requires faster processing speed
`and improved convergence
`of mixed-signal
`tools
`
`increasing processing speed clock frequen-
`cies which requires more accurate modeling
`of devices and interconnects
`as well as test
`capability and package- and system-level
`
`inte-
`
`heteroge-
`soft-and
`effec-chip
`low-simulation
`con-SoC
`inter-gration
`ferro-ential
`dri-tion
`appli-ductor
`analy-Roadmaps
`
`poten-tially
`
`para-January
`
`2002
`
`

`

`100
`
`90
`
`80
`
`70
`
`60
`
`50
`
`30
`
`20
`
`10
`
`0
`
`-- Logic area contribution
`-
`
`LOP
`
`H
`
`LSTP
`
`Logic area contribution
`-Total memory area LOP
`Total memory area LSTP
`
`Die Size
`
`1 cm2
`
`2001
`
`2004
`
`2007
`
`2010
`
`2013
`
`2016
`
`Year
`
`devel-U
`engi-40
`rela--
`man-in
`chal-content
`cor-LP-SoC
`sup-hecause
`intercon-ments
`rel-more
`pre-we
`error-cycle
`para-that
`be-Despite
`fabrica-nated
`fea-$15
`
`The overriding message in the 2001 Roadmap is
`threat to continuation
`that design cost
`is the greatest
`of the semiconductor industrys phenomenal growth.
`engineering NRE
`nonrecurring
`Manufacturing
`costs are just reaching $1 million mask set and probe
`card whereas design NRE costs routinely reach tens
`of millions of dollars. We measure manufacturing
`times in weeks with low uncertainty whereas
`measure design and verification cycle times in
`months or years with high uncertainty. Moreover
`design shortfalls are responsible for silicon respins
`multiply manufacturing NRE costs.
`an acknowledged
`design productivity gap
`in which the number of available transistors grows
`faster than the ability to design them meaningfully
`in process technology has by far domi-
`investment
`in design technology. The good
`investment
`news is that developers
`continue to make progress
`in design technology DT The estimated design
`cost of a low-power SoC PDA was approximately
`million in 2001 versus $342 million if DT inno-
`1993 and 2001.
`vations had not occurred between
`The bad news is that software now routinely
`
`accounts for 80 percent of embedded-systems
`test cost has grown significantly
`opment cost
`tive to total manufacturing cost verification
`neers are twice as numerous as design engineers on
`microprocessor project teams-and the list goes on.
`In 2001 many previous design technology
`gaps
`became crises.
`
`DT faces two basic types of complexity silicon
`and system. Silicon complexity refers to the impact
`of process scaling and the introduction of new
`materials or device/interconnect
`architectures.
`ignorable phenomena implied
`Previously
`lenges now have greater
`impact on design
`rectness and value including
`
`nonideal scaling of device parasitics and
`ply/threshold voltages-leakage power
`agement
`innovation current
`circuit/device
`delivery
`coupled high- frequency devices and
`netts-noise/interference
`analysis and management
`manufacturing equipment
`process modeling library characterization
`interconnect performance
`scaling of global
`ative to device performance-communication
`
`signal
`
`integrity
`
`limits-statistical
`
`synchronization
`decreased reliability-gate insulator
`tunneling
`and breakdown integrity joule heating and
`electromigration single-event upset general
`
`fault tolerance
`
`complexity of manufacturing bandoff-reticle
`enhancement
`and mask writing/inspection
`flow NRE cost and
`process variability-library characterization
`analog and digital circuit performance
`tolerant design layout reuse reliable and
`dictable implementation platforms.
`
`Silicon complexity places long-standing
`digms at risk System-wide synchronization
`comes infeasible due to power limits and the cost of
`variability the
`robustness under manufacturing
`CMOS transistor becomes subject
`to ever-larger
`statistical variabilities in its behavior and
`tion of chips with 100 percent working transistors
`and interconnects becomes prohibitively expensive.
`System complexity refers
`to exponentially
`increasing transistor counts enabled by smaller
`ture sizes and spurred by consumer demand for
`increased functionality lower cost and shorter time
`include
`to market.
`
`Implied challenges
`
`Power gap
`Figure 2.
`effect on chiphip co m-
`
`position.
`
`Memory
`
`outstrips
`
`logic content
`
`faster
`
`with LSTP devices
`
`they
`
`have
`
`much
`o
`erat-
`
`g power than LOPpower than
`de
`depvices.
`
`meters. Table I shows power constraints projected
`through 2016.
`composition of
`Figure 2 projects logic/memory
`designs assuming that chip power is con-
`strained according to a power budget of 0.1 W and
`that chip size is constrained to 100 mm. Memory
`faster with LSTP
`content outstrips logic content
`low standby power devices
`because they have
`much higher operating power than LOP low oper-
`ating power devices. Without substantial
`improve-
`in power management capability memory
`will asymptotically dominate both models by 2016.
`Given the projection that PDA chip size will grow
`at approximately 20 percent per node even though
`power remains flat at 0.1 W this would lead to even
`extreme memory-logic imbalances in the long
`
`term.
`
`Computer
`
`

`

`Today 130 nm
`
`Tomorrow 50 nm
`
`System
`
`l
`
`design
`
`System
`
`model
`
`System
`
`design
`
`System
`model
`
`Verification moves to
`levels followed
`
`higher
`in lower levels by
`equivalence checking
`and assertion driven
`
`optimizations
`
`Performance
`
`model
`
`Specifications
`
`Design optimized over
`many constraints with
`
`tightly
`
`integratedanalyses
`and syntheses
`
`1SW
`
`RTL
`
`optimizations
`
`Integration through
`modular open
`architecture with
`industry standard
`interface for data
`
`control
`
`Shared data in memory
`to eliminate disk
`
`accesses in critical
`loops with common
`
`data for cooperating
`
`applications
`
`Incremental
`
`specification
`
`synthesis optimization
`and analysis
`
`Placementýý-
`
`Functional
`
`Performance
`
`Testability
`
`erification
`
`Analyze
`
`Performance
`
`Timing
`
`Power
`
`Noise
`
`Test
`
`Manufacturing
`
`Other
`
`F3. Evolution
`
`i
`Figure
`design system
`architecture into an
`
`integrated system
`
`wherein logical
`
`layout
`
`physical
`and other tools can
`
`operate together.
`
`_
`
`Functional
`
`Verification
`
`SW
`
`optimization
`
`ý
`
`File
`
`Masks
`
`Logic synthesis
`
`Timing analysis
`Placement optimization
`----
`
`r
`
`Performance
`
`Testability
`
`Verifica