`Request
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`for
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`Continued Examination (RCE)
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`Transmittal
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`12/170,191
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`First Named Inventor
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`Masafumi TSUTSUI, et al.
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`284
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`Attorney Docket
`Number
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`079195-0566
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`LC] Consider the arguments in the Appeal Brief or Reply Brief previouslyfiled on
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` i. (J Other
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`Enclosed
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`Miscellaneous
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`March 29, 2010
`Signature
`Takashi Saito
`Limited Recognition No.
` Name(PrinvType)
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`CERTIFICATE OF MAILING OR TRANSMISSION
`Thereby cerlify thatthis correspondence is being deposited with the United States Postal Service with sufficient postageasfirst class mail in an envelope
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`Signature]
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`Name(PrintType)
`Takashi Saito
`[dae|
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`
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`IPR2017-01841
`
`IP Bridge Exhibit 2015
`IP Bridge Exhibit 2015
`TSMC v. Godo Kaisha IP Bridge 1
`TSMCv. Godo KaishaIP Bridge 1
`IPR2017-01841
`
`

`

`Docket No.: 079195-0566
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`PATENT
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re Application of
`Masafumi TSUTSULetal.
`Application No.: 12/170,191
`Filed: July 09, 2008
`
`: Customer Number: 53080
`: Confirmation Number: 1644
`: Group Art Unit: 2814
`:
`Examiner: Howard Weiss
`
`For:
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`SEMICONDUCTOR DEVICE INCLUDING MISFET HAVING INTERNAL STRESS
`FILM (as amended)
`
`AMENDMENT ACCOMPANYING RCE
`
`Mail Stop RCE
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`Sir:
`
`In response to the Office Action dated December 31, 2009, wherein a three-month
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`shortened statutory period for responseis set to expire on March 31, 2010, Applicants
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`respectfully request reconsideration of the above-identified application in view of the following
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`amendments and remarks. A Request for Continued Examination is being filed concurrently
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`herewith.
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`WDC99 1850842-1.079195.0566
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`

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`Application No.: 12/170,191
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`AMENDMENTSTO THE CLAIMS:
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`A listing ofthe claims presentedin this patent application appears below. This listing
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`replacesall prior versions andlisting ofclaims in this patent application.
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`1-14. (Cancelled)
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`15. (Currently Amended) A semiconductor device, comprising a
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`MISFET, wherein
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`the MISFETincludes:
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`an active region made of a semiconductorsubstrate;
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`a gate insulating film formed on the active region;
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`a gate electrode formed onthe gate insulating film;
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`source/drain regions formed in regionsof the active region located on both sides ofthe
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`gate electrode; and
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`a silicon nitride film formed over from side surfaces of the gate electrode to upper
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`surfaces of the source/drain regions, wherein
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`the silicon nitride film is not formed on an uppersurface of the gate electrode, [[and]]
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`the gate insulating film is formed only under a lowersurface of the gate electrode, and
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`the source/drain regions include lightly doped impurity regions formed in regions of the
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`active region located on both sides of the gate electrode, and heavily doped impurity regions
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`formedin regions of the active region respectively extending outwardly from the lightly doped
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`impurity regions to be in contact with the lightly doped impurity regions and having a higher
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`impurity concentration than that of the lightly doped impurity regions.
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`WDC99 1850842-1.079195.0566
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`Application No.: 12/170,191
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`16. (Previously Presented) The semiconductor device of claim 15, wherein
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`the silicon nitride film is for generating a stress in a substantially parallel direction to the
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`gate length direction in a channel region located in the active region underthe gate electrode.
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`17. (Previously Presented) The semiconductor device of claim 16, wherein
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`the substantially parallel direction of the stress includes a direction tilted by an angle of
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`less than 10 degree from a direction in which carriers move.
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`18. (Previously Presented) The semiconductor device of claim 15, wherein
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`the silicon nitride film is directly in contact with the source/drain regions,
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`19. (Previously Presented) The semiconductor device of claim 15, wherein
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`the silicon nitride film is formed above the source/drain regions with a thin film
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`interposed therebetween.
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`20. (Currently Amended) The semiconductor device of claim 15, wherein
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` the source/drain regions include a
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`impurityregion-and a silicide layer.
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`21. (Previously Presented) The semiconductor device of claim 15, further comprising:
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`a sidewall formed on the side surface of the gate electrode.
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`22. (Previously Presented) The semiconductor device of claim 15,
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`wherein
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`a principal surface of the semiconductor substrate is substantially a {100} plane, and
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`the gate length direction of the gate electrode is substantially a <011> direction.
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`WDC99 1850842-1.079195.0566
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`Application No.: 12/170,191
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`23. (Previously Presented) The semiconductor device of claim 15, further
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`comprising:
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`an interlevel insulating film formed on the silicon nitride film; and
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`a contact plug providedso as to pass throughthe interlevel insulating film and thesilicon
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`nitride film and to be connected to the source/drain regions.
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`24, (Previously Presented) The semiconductor device of claim 15, wherein
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`the active region is divided by an isolation region formed in the semiconductor substrate.
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`25. (Previously Presented) The semiconductor device of claim 15, wherein
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`the gate insulating film is a silicon oxide film.
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`26. (Previously Presented) The semiconductor device of claim 15, wherein
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`the gate insulating film is a silicon oxynitride film.
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`27. (Previously Presented) The semiconductor device of claim 15, wherein
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`the gate electrode has a polysilicon film.
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`28. (Previously Presented) The semiconductor device of claim 15, wherein
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`the gate electrode has a metalfilm.
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`29. (Previously Presented) The semiconductor device of claim 15, wherein
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`the silicon nitride film is provided so as to coverat least part of
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`at least one of the source/drain regions.
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`30. (Previously Presented) The semiconductor device of claim 15, wherein
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`the silicon nitride film covers at least respective parts of the source/drain regions.
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`WDC99 1850842-1,079195.0566
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`Application No.: 12/170,191
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`31. (Previously Presented) The semiconductor device of claim 15, wherein
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`the silicon nitride film covers at least respective parts of both side surfaces of the gate
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`electrode.
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`32. (Previously Presented) The semiconductor device of claim 15, wherein
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`the MISFETis an nMISFET and
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`the source/drain regions are n-type source/drain regions.
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`33. (Previously Presented) The semiconductor device of claim 32, wherein
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`the silicon nitride film is for generating a tensile stress in a substantially parallel direction
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`to the gate length direction in a channel region located in the active region underthe gate
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`electrode.
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`34. (Previously Presented) The semiconductor device of claim 32, wherein
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`the n-type source/drain regions include an n-type lightly doped impurity region, an n-type
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`heavily doped impurity region anda silicide layer.
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`35. (Previously Presented) The semiconductor device of claim 15, wherein the silicon
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`nitride film directly contacts with the side surfaces of the gate electrode.
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`36. (Previously Presented) The semiconductor device of claim 24, wherein a lower
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`surface ofthe isolation region is located in the semiconductor substrate andis in direct contact
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`with the semiconductor substrate.
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`WDC99 1850842-1.079195.0566
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`

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`Application No.: 12/170,191
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`Status of Claims
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`REMARKS
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`Claims 15-36 are pending, of which claim 15 is independent. Claims 15 and 20 have
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`been amendedto correct informalities in the claim language and to more clearly define the
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`claimed subject matter. Care has been taken to avoid introducing new matter.
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`Rejection under 35 U.S.C. § 103
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`Claims 15-21, 23-34 and 36 were rejected under 35 U.S.C. § 103(a) as being
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`unpatentable over Xiang et al. (US 6,437,404) in view of Matsudaet al. (US 6,870,230). Claims
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`22 and 35 were rejected under 35 U.S.C. § 103(a) as being unpatentable over Xianget al. and
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`Matsudaetal., and further in view of Tatsuta (US 5,023,676). These rejections are traversed for
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`at least the following reasons.
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`Applicants respectfully submit that it would not have been obvious to combine Xiang
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`with Matsuda because it would not be technically possible to replace the gate structure of Xiang
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`with the gate structure of Matsuda.
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`In rejecting claim 15, the Examinerasserts that the gate
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`insulating film 58 of Xiang correspondsto the claimedgate insulating film and concedesthat
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`Xiang fails to disclose that the gate insulating film is formed only under a lower surface of the
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`gate electrode. The Examinerrelies on Matsudaasserting that the gate insulating film 3 of
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`Matsuda is formed only under a lower surface of the gate electrode 6a.
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`However, technologically,it is impossible to form the gate electrode 6a including the
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`gate insulating film 3 of Matsudain the recess portion of Xiang from which the dummygate
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`oxide layer 132 and the dummygate electrode 134 have been removed(see, FIG. 11 of Xiang).
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`Specifically, it is technically impossible to form a gate insulating film only on the bottom ofthe
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`Application No.: 12/170,191
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`recess portion so that the gate insulating film is formed only under a lower surface of a gate
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`electrode. Evenif, for example, a CVD process was employedto form the alleged gate
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`insulating film within the recess portion, the gate insulating film would necessarily be formed on
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`the side surfaces of the recess portion, and the gate electrode would have the gate insulating film
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`not only on the bottom surface, but also on the side surfaces. As such, it would not have been
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`obvious to combine Xiang with Matsuda because it would be technically impossible to replace
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`the gate structure of Xiang with that of Matsuda, and evenif it was replaced, the resultant
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`structure would be different from the claimedstructure.
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`Further, Applicants respectfully submit that Xiang fails to disclose that “the source/drain
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`regions include lightly doped impurity regionsformedin regions ofthe active region located on
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`both sides ofthe gate electrode, and heavily doped impurity regionsformedin regions ofthe
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`active region respectively extending outwardlyfrom the lightly doped impurity regions to be in
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`contact with the lightly doped impurity regions and having a higher impurity concentration than
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`that ofthe lightly doped impurity regions,” as recited by amended claim 1. In rejecting original
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`claim 20, the Examinerasserts that regions 50 and 50 correspondto the claimed lightly doped
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`impurity region, and regions 64 and 66 correspondto the claimed heavily doped impurity region.
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`However,it is clear that the regions 50/52 and 64/66 have the same impurity
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`concentration. As shown in FIG.7, in step 180, source and drain regions 182 and 184 are
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`formed (see, column 5, 58-60 of Xiang). Thereafter, as shown in FIG.9, in step 200,silicide
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`regions 202 and 204 are formed in the source and drain regions 182 and 184, respectively (see,
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`column 6, lines 12-14 of Xiang). Thus, as shown in FIG.9,the silicide regions 202 and 204 are
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`formed suchthat each of the parts of the source and drain regions 182 and 184, other than the
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`silicide regions 202 and 204,is divided into a part corresponding to an associated one of the
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`WDC99 1850842-1.079195.0566
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`Application No.: 12/170,191
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`source and drain extensions 50 and 52 and a part corresponding to an associated one ofthe strips
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`64 and 66 and the two parts are separated from each other by an associated oneofthesilicide
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`regions 202 and 204. Thus, the source and drain extensions 50 and 52 have the same impurity
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`concentration as that of the strips 64 and 66. As such,it is clear that Xiang fails to disclose the
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`aboveidentified features of amended claim 15.
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`Based on the foregoing, the combination of Xiang and Matsuda does not render claim 15
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`or any claim dependent thereon obvious. It is also clear that the remaining cited reference does
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`not cure the deficiencies of Xiang and Matsuda. Accordingly, Applicants respectfully submit
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`that claims 15-21 and 23-34 are patentable over the cited references. Thus,it is requested that
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`the Examiner withdraw the rejection of claims 15-36 under 35 U.S.C. § 103(a).
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`WDC99 1850842-1.079195.0566
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`Application No,: 12/170,191
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`CONCLUSION
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`Havingfully respondedtoall matters raised in the Office Action, Applicants submit that
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`all claims are in condition for allowance,an indication for whichis respectfully solicited. If
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`there are any outstanding issues that might be resolved by an interview or an Examiner’s
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`amendment, the Examineris requested to call Applicants’ attorney at the telephone number
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`shown below.
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`To the extent necessary, a petition for an extension of time under 37 C.F.R. § 1.136 is
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`hereby made. Please charge any shortage in fees due in connection with thefiling of this paper,
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`including extension of time fees, to Deposit Account 500417 and please credit any excess fees to
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`such deposit account.
`
`Respectfully submitted,
`
`McDERMOTT WILL & EMERY LLP
`
`LLL
`
`Takashi Saito
`Limited Recognition No. L0123
`
`Please recognize our Customer No. 53080
`as our correspondence address.
`
`600 13" Street, N.W.
`Washington, DC 20005-3096
`Phone: 202.756.8000 MEF:TS/Ilg
`Facsimile: 202.756.8087
`Date: March 29, 2010
`
`WDC99 1850842-1.079195.0566
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