`
`DOCKET NO.: 2003195-00123US1
`Filed By: David L. Cavanaugh, Reg. No. 36,476
`Dominic E. Massa, Reg. No. 44,905
`Michael H. Smith, Reg. No. 71,190
`1875 Pennsylvania Ave. NW
`Washington, DC 20006
`Tel: (202) 663-6000
`Email: David.Cavanaugh@wilmerhale.com
`Dominic.Massa@wilmerhale.com
`MichaelH.Smith@wilmerhale.com
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
`Petitioner
`
`v.
`
`GODO KAISHA IP BRIDGE 1
`Patent Owner.
`
`Case IPR2017-01841
`
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 7,893,501
`CLAIMS 1, 4, 7, 9-11, 14, 16-18, and 23-25 (Petition #1)
`
`
`

`

`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`TABLE OF CONTENTS
`
`Page
`INTRODUCTION ........................................................................................... 1 
`I. 
`II.  MANDATORY NOTICES ............................................................................. 2 
`A. 
`Real Parties-in-Interest .......................................................................... 2 
`B. 
`Related Matters ...................................................................................... 2 
`C. 
`Counsel .................................................................................................. 2 
`D. 
`Service Information ............................................................................... 3 
`E. 
`Fee for Inter Partes Review ................................................................... 3 
`III.  CERTIFICATION OF GROUNDS FOR STANDING .................................. 3 
`IV.  OVERVIEW OF CHALLENGE AND RELIEF REQUESTED .................... 4 
`A.  Grounds for Challenge .......................................................................... 4 
`B. 
`Prior Art Patents and Printed Publications Relied Upon ...................... 4 
`C. 
`Relief Requested .................................................................................... 5 
`PERSON OF ORDINARY SKILL IN THE ART .......................................... 5 
`V. 
`VI.  TECHNOLOGY BACKGROUND ................................................................. 6 
`VII.  OVERVIEW OF THE ’501 PATENT .......................................................... 14 
`A. 
`Priority Date of the ’501 Patent........................................................... 19 
`B. 
`Summary of the Prosecution History .................................................. 19 
`VIII.  CLAIM CONSTRUCTION .......................................................................... 21 
`IX.  GROUNDS FOR FINDING THE CHALLENGED CLAIMS INVALID ... 21 
`A.  Ground 1: Claims 1, 4, 7, 9-11, 14, 16-18, and 23-25 are
`rendered obvious by Igarashi in view of Woerlee .............................. 21 
`1. 
`Independent Claim 1 ................................................................. 22 
`2. 
`Dependent Claim 4 ................................................................... 46 
`3. 
`Dependent Claim 7 ................................................................... 48 
`4. 
`Dependent Claim 9 ................................................................... 50 
`5. 
`Dependent Claim 10 ................................................................. 54 
`6. 
`Dependent Claim 11 ................................................................. 65 
`7. 
`Dependent Claim 14 ................................................................. 67 
`8. 
`Dependent Claim 16 ................................................................. 68 
`9. 
`Dependent Claim 17 ................................................................. 69 
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`10.  Dependent Claim 18 ................................................................. 70 
`11.  Dependent Claim 23 ................................................................. 72 
`12.  Dependent Claim 24 ................................................................. 74 
`13.  Dependent Claim 25 ................................................................. 75 
`CONCLUSION .............................................................................................. 78 
`
`X. 
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`
`I.
`
`INTRODUCTION
`Petitioner Taiwan Semiconductor Manufacturing Company Ltd.
`
`(“Petitioner”) respectfully requests inter partes review (“IPR”) of claims 1, 4, 7, 9-
`
`11, 14, 16-18, and 23-25 of U.S. Patent No. 7,893,501 (“the ’501 patent”) (Ex-
`
`1001).
`
`The ’501 patent claims a conventional MISFET device. The limitations of
`
`claim 1 (the sole independent claim) are directed to features that were standard to
`
`many, if not all, MISFET devices – an active region made of a semiconductor
`
`substrate, a gate insulating film, a gate electrode, source/drain regions, and a
`
`silicon nitride film.
`
`Applicant obtained allowance of the claims after multiple rejections by
`
`amending claim 1 to require that the gate electrode protrude upward from the
`
`silicon nitride film. The Examiner’s reason for allowance stated that the
`
`protruding gate electrode was not in the “prior art of record.” However, the
`
`Examiner did not have the benefit of references like U.S. Patent Publication No.
`
`2002/0145156 to Igarashi et al. (“Igarashi,” (Ex-1004)) and U.S. Patent No.
`
`5,960,270 to Misra et al. (“Misra,” (Ex-1005)), which are two examples of
`
`MISFETs with a protruding gate electrode.
`
`There was nothing novel about having a protruding gate electrode. The
`
`specification of ’501 patent does not even mention this feature, let alone identify
`
`1
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`

`

`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`any purported advantages. Moreover, MISFETs with a protruding gate electrode
`
`are disclosed in prior art references such as Igarashi and Misra. Claim 1 thus
`
`recites nothing more than a conventional MISFET with widely used features.
`
`The dependent claims merely recite conventional aspects of MISFETs that
`
`are disclosed and rendered obvious by the prior art – e.g., the choice of gate
`
`electrode material and the inclusion of standard structures like thin films, interlevel
`
`insulating films, and sidewalls.
`
`Each of the challenged claims is therefore unpatentable.
`
`II. MANDATORY NOTICES
`A. Real Parties-in-Interest
`Taiwan Semiconductor Manufacturing Company Ltd. is the real party-in-
`
`interest.
`
`B. Related Matters
`Petitioner is filing three other inter partes review petitions challenging
`
`claims of the ’501 patent. The following litigation would affect or be affected by a
`
`decision in this proceeding: Godo Kaisha IP Bridge 1 v. Xilinx, Inc., Case No.
`
`2:17-cv-00100 (E.D. Tex.).
`
`C. Counsel
`Lead Counsel: David L. Cavanaugh (Registration No. 36,476)
`
`Backup Counsel: Dominic E. Massa (Registration No. 44,905)
`
`Backup Counsel: Michael H. Smith (Registration No. 71,190)
`
`2
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`
`D.
`Service Information
`Email: David L. Cavanaugh, David.Cavanaugh@wilmerhale.com,
`
`Dominic E. Massa, Dominic.Massa@wilmerhale.com
`
`Michael H. Smith, MichaelH.Smith@wilmerhale.com
`
`Post and Hand Delivery:
`
`WilmerHale, 1875 Pennsylvania Ave. NW
`
`
`
`Washington, DC 20006
`
`Telephone: 202-663-6000
`
`Facsimile: 202-663-6363
`
`Pursuant to 37 C.F.R. § 42.10(b), Powers of Attorney accompany this
`
`Petition. Please address all correspondence to lead and backup counsel. Petitioner
`
`consents to service of all documents via email.
`
`E.
`Fee for Inter Partes Review
`The undersigned authorizes the PTO to charge the fee set forth in 37 C.F.R.
`
`§ 42.15(a) for this Petition to Deposit Account No. 08-0219. Review of 13 claims
`
`is requested. The undersigned authorizes payment for additional fees that may be
`
`due with this petition to be charged to the above-referenced Deposit Account.
`
`III. CERTIFICATION OF GROUNDS FOR STANDING
`Petitioner certifies pursuant to Rule 42.104(a) that the patent for which
`
`review is sought is available for inter partes review and that Petitioner is not
`
`barred or estopped from requesting an inter partes review challenging the patent
`
`claims on the grounds identified in this Petition.
`
`3
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`IV. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED
`Pursuant to Rules 42.22(a)(1) and 42.104(b)(1)-(2), Petitioner challenges
`
`claims 1, 4, 7, 9-11, 14, 16-18, and 23-25 (“the challenged claims”) of the ’501
`
`patent and requests that each challenged claim be cancelled.
`
`A. Grounds for Challenge
`This Petition, supported by the declaration of Dr. Stanley Shanfield
`
`(“Shanfield Decl.,” Ex-1002), demonstrates that there is a reasonable likelihood
`
`that Petitioner will prevail with respect to at least one of the challenged claims and
`
`that each of the challenged claims is unpatentable for the reasons cited in this
`
`petition. See 35 U.S.C. § 314(a).
`
`B.
`Prior Art Patents and Printed Publications Relied Upon
`Petitioner relies upon the following patents and printed publications:
`
`1.
`
`U.S. Patent Publication No. 2002/0145156 to Igarashi et al.
`
`(“Igarashi,” Ex-1004), filed on October 9, 2001 and published on October
`
`10, 2002, is prior art to the ʼ501 patent under 35 U.S.C. §§ 102(a), 102(b),
`
`and 102(e).
`
`2.
`
`U.S. Patent No. 6,406,963 to Woerlee et al. (“Woerlee,” Ex-1006),
`
`filed on December 14, 2000 and issued on June 18, 2002, is prior art under
`
`35 U.S.C. §§ 102(a), 102(b), and 102(e).
`
`Igarashi is prior art under 35 U.S.C. §102(b) because it published on October
`
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`10, 2002, which is more than a year before the earliest claimed U.S. filing date of
`
`the ’501 patent, which is June 3, 2004. Igarashi is also prior art under 35 U.S.C.
`
`§102(a) and §102(e) because it has a U.S. filing date of October 9, 2001 and was
`
`published on October 10, 2002, which are before the earliest claimed priority date
`
`of the ’501 patent, which is June 16, 2003 based on JP 2003-1700335.
`
`Woerlee is prior art under 35 U.S.C. §102(b) because it issued on June 18,
`
`2002, which is more than a year before the earliest claimed U.S. filing date of the
`
`’501 patent, which is June 3, 2004. Woerlee is also prior art under 35 U.S.C.
`
`§102(a) and §102(e) because it has a U.S. filing date of December 14, 2000 and
`
`published on June 18, 2002, which are before the earliest claimed priority date of
`
`the ’501 patent, which is June 16, 2003 based on JP 2003-1700335.
`
`C. Relief Requested
`Petitioner requests that the Patent Trial and Appeal Board cancel the
`
`challenged claims because they are unpatentable under 35 U.S.C. § 103.
`
`V.
`
`PERSON OF ORDINARY SKILL IN THE ART
`A person of ordinary skill in the art (POSITA) at the time of the alleged
`
`invention of the ’501 patent would have had the equivalent of a Master’s degree in
`
`electrical engineering, physics, chemistry, materials science, or equivalent training,
`
`and two years of work experience in field of semiconductor manufacturing.
`
`Additional graduate education could substitute for work experience, and additional
`
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`work experience/training could substitute for formal education. (Shanfield Decl.
`
`¶¶30-32 (Ex-1002).)
`
`VI. TECHNOLOGY BACKGROUND
`The challenged claims relate to semiconductor devices, which existed long
`
`before the filing of the application that became the ’501 patent. The claims recite
`
`features that were standard to many, if not all, MISFET transistors, such as an
`
`active region made of a semiconductor substrate, a gate insulating film, a gate
`
`electrode, source/drain regions, and a silicon nitride film. (Shanfield Decl. ¶33
`
`(Ex-1002).)
`
`Metal-insulator-semiconductor field effect transistors (MISFETs) were
`
`developed long before the ’501 patent. The small size of MISFETs as compared
`
`with prior vacuum tube technologies helped enable much of the modern computer
`
`and electronics industry that developed from the 1970s and 1980s through the
`
`present. (Shanfield Decl. ¶34 (Ex-1002).)
`
`MOS transistors are a type of MISFET where the insulating film is an oxide,
`
`such as silicon dioxide or silicon oxynitride. MOS transistors are by far the most
`
`common type of MISFET. (Shanfield Decl. ¶¶35-36 (Ex-1002).)
`
`The figure below from J. Plummer et al., Silicon VLSI Technology:
`
`Fundamentals, Practice and Modeling, at 86 (1st ed. 2000) (Ex-1008) shows an
`
`6
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`example of a MISFET, and more particularly, a MOS transistor.1 (Shanfield Decl.
`
`¶36 (Ex-1002).)
`
`
`
`MISFETs include active regions made of a semiconductor substrate. The
`
`active regions are found between the shallow trench isolation regions (STI). (See
`
`Rabaey at 42-43 (Ex-1010).) The active regions are where the transistors are
`
`formed. (Id. at 42.) The source and drain regions (green), the channel (area
`
`between the source and drain regions), and the well (“N Well” and “P Well”) are
`
`formed in regions of the active regions. (Plummer at 86 (Ex-1008).) The gate
`
`electrode (orange) is formed above the channel. (Shanfield Decl. ¶¶37-38 (Ex-
`
`1002).)
`
`1 Color and labels have been added to facilitate the description.
`
`7
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`The gate electrode (orange) is separated from the channel by an insulating
`
`film (red). (Plummer at 86 (Ex-1008).) The doped regions of the source and drain
`
`regions (green) are formed by doping the substrate with impurities. (Id. at 80-82.)
`
`It was common and conventional for source and drain regions (green) to have a
`
`lightly-doped region, a heavily doped region, and a silicide film, as shown in the
`
`figure above. (Id.) The lightly-doped and heavily doped regions are sometimes
`
`referred to as LDD (lightly-doped drain) and HDD (heavily-doped drain), although
`
`it is understood that both the source and drain are lightly and heavily doped.
`
`(Shanfield Decl. ¶38 (Ex-1002).)
`
`The STI are formed using the trench method and define the active region.
`
`This process is illustrated in textbooks such as Rabaey and Plummer. Rabaey
`
`explains: “The process starts with the definition of the active regions—these are
`
`the regions where the transistor will be constructed. All other areas of the die will
`
`be covered with a thick layer of silicon dioxide (SiO2) call the field oxide. This
`
`oxide acts as the insulator between neighboring devices, and it is either grown (as
`
`in the process of Figure 2-1) or deposited in trenches (Figure 2-2)—hence, the
`
`name trench isolation.” (Rabaey at 42 (Ex-1010).) Figure 2-6 illustrates this
`
`process, which begins with the step “Define active areas” and “Etch and fill
`
`trenches.”
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`8
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`
`(Rabaey at 43, Fig. 2-6 (Ex-1010).) Figure 2-7(c) shows the process of forming
`
`the trenches through a “plasma etch of insulating trenches using the inverse of the
`
`active area mask” to form an “NMOS and a PMOS transistor”:
`
`
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`9
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`
`
`
`(Rabaey at 44, Fig. 2-7 (Ex-1010).) (Shanfield Decl. ¶39 (Ex-1002).)
`
`The Plummer textbook similarly includes sections on “Active Region
`
`Formation” (section 2.2.2) and “Process Options for Device Isolation—Shallow
`
`Trench Isolation” (section 2.2.3). Plummer explains that “Modern CMOS chips
`
`integrate millions of active devices (NMOS and PMOS) side by side in a common
`
`silicon substrate” and that “it is usually assumed that the individual devices do not
`
`10
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`interact with each other except through their circuit interconnections.” (Plummer
`
`at 52-53 (Ex-1008).) Plummer further explains that “individual devices on the chip
`
`are electrically isolated from each other … by growing a fairly thick layer of SiO2
`
`in between each of the active devices.… The regions between these thick SiO2
`
`layers, where transistors will be built, are called the ‘active’ regions of the
`
`substrate.” (Id. at 53.) Plummer also explains that active regions may be defined
`
`by STI regions: “STI actually etches trenches in the silicon substrate between
`
`active devices and then refills them with SiO2.” (Id. at 57.) Figures 2-6 through 2-
`
`9 illustrate this process of forming the STI regions that separate and define the
`
`active regions:
`
`
`
`11
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`
`
`
`
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`12
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`
`
`
`(Id. at 57-59, Figs. 2-6 to 2-9.) (Shanfield Decl. ¶40 (Ex-1002).)
`
`Silicon nitride films were commonly included over the source and drain
`
`regions (green) in MISFET devices, with the gate electrode (orange) protruding
`
`above the silicon nitride film. (E.g., Igarashi at [0117-0118] (describing protruding
`
`gate electrode illustrated in Fig. 12), Fig. 12 (Ex-1004); Misra at 5:52-55; 6:67-
`
`7:15 (describing formation of protruding gate illustrated in Fig. 7), Fig. 7 (Ex-
`
`1005).) Silicon nitride films were commonly used for applications like etch stops.
`
`(E.g., Igarashi at [0047] (etch stop) (Ex-1004); Misra at 5:24-27 (etch stop) (Ex-
`
`1005).) The use of silicon nitride films in MISFET devices and design choices
`
`about what portions of the device to cover and how to locate the height of the gate
`
`relative to the nitride film were well understood before the alleged invention of the
`
`’501 patent. (Shanfield Decl. ¶¶41-44 (Ex-1002).)
`
`
`
`13
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`
`VII. OVERVIEW OF THE ’501 PATENT
`The challenged claims are directed to a transistor with the standard
`
`structures of conventional MISFETs at the time. As depicted in Figure 1 of the
`
`’501 patent, reproduced below, the claimed device of the ’501 patent includes: (1)
`
`an active region 1a made of a substrate 1, (2) a gate insulating film 5 (red), (3) a
`
`gate electrode 6a (orange), (4) source and drain regions 3a, 4a including a silicide
`
`layer (green), (5) a silicon nitride film 8a (blue), and (6) the gate electrode 6a
`
`(orange) that protrudes from the silicon nitride film 8a (blue). (’501 patent at 3:19-
`
`64, Fig. 1 (Ex-1001).) The active region 1a is located between the isolation
`
`regions 2 and is where the transistor is formed. (’501 patent at 3:19-64, Fig. 1 (Ex-
`
`1001).) (Shanfield Decl. ¶45 (Ex-1002).)
`
`
`
`14
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`
`
`
`The allegedly distinguishing feature of the claims of the ’501 patent is gate
`
`6a (orange) protruding above the silicon nitride film 8a (blue).2 (See Summary of
`
`the Prosecution History below.) The specification of ’501 patent, however, does
`
`
`2 The alleged invention described in the specification of the ’501 patent involves
`
`generating stress in the transistor channel by using tensile and compressive stresses
`
`of various layers. (See, e.g., ’501 patent, Abstract, 1:20-23 (Ex-1001).) (Shanfield
`
`Decl. ¶46, n.3 (Ex-1002).) However, the stress limitations are only recited in
`
`claims 2, 3, and 20. The vast majority of the claims, including all of the
`
`challenged claims in this IPR petition, fail to recite any stress limitations.
`
`15
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`not even mention the protruding gate electrode, let alone identify any purported
`
`advantages. (Shanfield Decl. ¶46 & n.3 (Ex-1002).)
`
`When the application that led to the ’501 patent was filed, there was nothing
`
`new about these standard transistor features. Multiple prior art references
`
`disclosed MISFETs with the same elements as the ’501 patent, including a
`
`protruding gate. For example, Igarashi, the primary reference for this petition,
`
`discloses a MISFET incorporating the claimed features:
`
`
`
`16
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`(Igarashi at Fig. 123 (Ex-1004).) (Shanfield Decl. ¶47 (Ex-1002).)
`
`Igarashi discloses (1) an active region made of a semiconductor substrate
`
`(active region made of substrate 1 where the transistor is formed) (Igarashi at
`
`[0068] (Ex-1004)), (2) a gate insulating film (gate oxide film 2) (red) (Igarashi at
`
`[0044] (Ex-1004)), (3) a gate electrode (gate electrode 3) (orange) (Igarashi at
`
`[0044] (Ex-1004)), (4) source and drain regions (impurity diffusion layers 4 and
`
`silicide film 5 of the source/drain) (green) (Igarashi at [0044] (Ex-1004)), (5) a
`
`silicon nitride film (silicon nitride film 8) (blue) (Igarashi at [0117-18] (Ex-1004)),
`
`and (6) the gate electrode 3 protruding upward from the silicon nitride film 8.
`
`(Igarashi at [0117-0118] (Ex-1004).) A POSITA would have understood based on
`
`the specifications that the relevant disclosure in Igarashi and the ’501 patent is the
`
`same even if the schematic illustrations are not identical. (Shanfield Decl. ¶48 (Ex-
`
`1002).)
`
`Misra, the primary reference in a separate petition, similarly describes a
`
`3 Fig. 12 has been annotated throughout with the reference numeral 8 for clarity. It
`
`would have been clear to a POSITA that this layer is the silicon nitride film 8
`
`because the same structure is identified with the reference numeral “8” in Fig. 11
`
`and because this structure is identified as the silicon nitride film 8 in the
`
`corresponding text. (E.g., Igarashi at [0117-0118] (Ex-1004).) (Shanfield Decl.
`
`¶47, n.4 (Ex-1002).)
`
`17
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`transistor with these claimed features. Figure 7, reproduced below, shows (1) an
`
`active region made of a semiconductor substrate (active region made of substrate
`
`12 where the transistor is formed) (Misra at 4:21-28, 4:31-33, 4:42-50, 6:16-19
`
`(Ex-1005)), (2) a gate insulating film (thermal gate oxide 27) (red) (Misra at 6:59-
`
`67 (Ex-1005)), (3) a gate electrode (gate electrode 28b) (orange) (Misra at 6:66-
`
`7:2, 7:14-20 (Ex-1005)), (4) source and drain regions (source and drain electrodes
`
`26 and 28 and silicide region 18) (green) (Misra at 4:42-46, 6:16-33 (Ex-1005)),
`
`(5) a silicon nitride film (plasma enhanced nitride layer 20) (blue) (Misra at 5:20-
`
`27 (Ex-1005)), and a gate electrode 28b protruding upward from the silicon nitride
`
`film 20 (Misra at 5:52-55; 6:67-7:15, Fig. 7 (Ex-1005)):
`
`
`
`
`
`(Shanfield Decl. ¶49 (Ex-1002).)
`
`
`
`In fact, these are just a few of the many references that had the conventional
`
`feature of a protruding gate electrode. (See also, e.g., U.S. Patent Nos. 6,509,234
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`(Ex-1016); 5,726,479 (Ex-1017); 6,512,266 (Ex-1018); 6,806,584 (Ex-1013).)
`
`(Shanfield Decl. ¶50 (Ex-1002).)
`
`A.
`
`Priority Date of the ’501 Patent
`
`The ’501 patent claims priority to a Japanese patent, JP 2003-170335, filed
`
`June 16, 2003 and to U.S. Patent Application No. 10/859,219, filed June 3, 2004.
`
`Because each of the prior art references is prior art to the ’501 patent’s
`
`earliest claimed U.S. and foreign priority dates, Petitioner does not address
`
`whether the ’501 patent is entitled to its claimed priority dates. However,
`
`Petitioner reserves the right to challenge the priority claims of the ’501 patent.
`
`(Shanfield Decl. ¶¶51-52 (Ex-1002).)
`
`B.
`
`Summary of the Prosecution History
`
`The ’501 patent was allowed following multiple rounds of rejection after
`
`amending the claims to recite a gate electrode that protrudes upward from a silicon
`
`nitride film. The reason for allowance stated this feature was not in the “prior art
`
`of record,” but the prior art of record did not include Igarashi or Misra, which are
`
`two examples disclosing the claimed protruding gate electrode. (Shanfield Decl.
`
`¶53 (Ex-1002).)
`
`The ’501 patent issued from U.S. Patent Appl. No. 12/170,191, filed on July
`
`9, 2008. Following multiple rejections, Applicant amended pending claim 15
`
`(issued claim 1) to add “the gate electrode protrudes upward from a surface level
`
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`of parts of the silicon nitride film located at both side surfaces of the gate
`
`electrode.” (August 6, 2010 Response at 2 (Ex-1003).) Applicant characterized
`
`the amendment as follows:
`
`In the present subject matter, as shown in, for example, FIGS. 1 and
`4A, the gate electrode 6a, 6b protrudes upward from a surface level of
`parts of the silicon nitride film 8a, 8b located at both side surfaces of
`the gate electrode 6a, 6b. In other words, a height of the gate electrode
`from the surface of the substrate is higher than a height of the silicon
`nitride film disposed at the sides of the gate electrode.
`
`(August 6, 2010 Response at 8 (Ex-1003).) Applicant argued that the applied
`
`references failed to show a protruding gate. (August 6, 2010 Response at 9 (Ex-
`
`1003).) (Shanfield Decl. ¶54 (Ex-1002).)
`
`On October 15, 2010, the claims were allowed in a Notice of Allowance.
`
`The Examiner provided the following reason for allowance: “A MISFET as
`
`claimed including a gate electrode protruding upward form [sic] a surface level of
`
`parts of a silicon nitride film located on the gate electrode’s sides could not be
`
`anticipated nor, in combination, be rendered obvious over the prior art of record.”
`
`(October 15, 2010 Notice of Allowance at 2 (Ex-1007).) (Shanfield Decl. ¶55
`
`(Ex-1002).)
`
`The Examiner did not have the benefit of Igarashi or Misra, which each have
`
`a gate electrode that protrudes. Thus, this petition introduces new art that was not
`
`20
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`before the Examiner during prosecution. (Shanfield Decl. ¶56 (Ex-1002).)
`
`VIII. CLAIM CONSTRUCTION
`In an inter partes review, the terms in the challenged claims should be given
`
`their plain meaning under the broadest reasonable interpretation standard. Cuozzo
`
`Speed Technologies, LLC v. Lee, 136 S. Ct. 2131, 2139, 2141 (2016). Petitioner
`
`adopts that standard for this proceeding, but reserves the right to pursue different
`
`constructions in a district court, where different claim construction standards
`
`apply.
`
`Should the Patent Owner, seeking to avoid the prior art, contend that the
`
`claims have a construction different from their broadest reasonable construction,
`
`the appropriate course is for the Patent Owner to seek to amend the claims to
`
`expressly correspond to its contentions in this proceeding. See 77 Fed. Reg.
`
`48,764; 48,766-67 (Aug. 14, 2012).
`
`IX.
`
` GROUNDS FOR FINDING THE CHALLENGED CLAIMS INVALID
`Pursuant to Rule 42.104(b)(4)-(5), specific grounds for finding the
`
`challenged claims invalid are identified below and discussed in the Shanfield
`
`Declaration (Ex-1002). These grounds demonstrate in detail that claims 1, 4, 7, 9-
`
`11, 14, 16-18, and 23-25 are not patentable under 35 U.S.C. § 103. (Shanfield
`
`Decl. ¶58 (Ex-1002).)
`
`A. Ground 1: Claims 1, 4, 7, 9-11, 14, 16-18, and 23-25 are rendered
`obvious by Igarashi in view of Woerlee
`
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`Claims 1, 4, 7, 9-11, 14, 16-18, and 23-25 are rendered obvious by Igarashi
`
`in view of Woerlee. Igarashi and Woerlee were not considered by the Examiner
`
`during prosecution of the ’501 patent. (Shanfield Decl. ¶59 (Ex-1002).)
`
`1.
`Independent Claim 1
`As illustrated in the chart below and in the discussion that follows, Igarashi
`
`in view of Woerlee renders independent claim 1 of the ’501 patent obvious. A
`
`POSITA would have understood that the disclosure of the features in Igarashi
`
`common to different illustrations are applicable to the embodiment shown in
`
`Figure 12 because the same reference numerals are used to describe common
`
`features of Igarashi’s disclosure. See 37 C.F.R. 1.84(p)(4) (“The same part of an
`
`invention appearing in more than one view of the drawing must always be
`
`designated by the same reference character, and the same reference character must
`
`never be used to designate different parts.”) Where features differ between figures,
`
`the differences are described in the disclosure of Igarashi. (E.g., Igarashi at [0117]
`
`(“FIG. 12 is a schematic sectional view showing a semiconductor device according
`
`to Fifth Embodiment of the present invention. Fifth Embodiment will be described
`
`below referring to the drawings. The semiconductor device of Fifth Embodiment
`
`has the configuration in which the silicon nitride films 8 on the upper surfaces of
`
`the gate electrodes 3 are removed as in Fourth Embodiment, and the silicon nitride
`
`films 7 and the silicon nitride films 8 on the upper portions of the sidewalls of the
`
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`gate electrodes 3 are also removed, and a low-k film 15 is formed on the upper
`
`surfaces of the gate electrodes 3.”).) (Shanfield Decl. ¶60 (Ex-1002).)
`
`’501 Patent Claim 1
`[1p] 1. A semiconductor device,
`comprising a MISFET, wherein the
`MISFET includes:
`[1a] an active region made of a
`semiconductor substrate;
`
`[1b] a gate insulating film formed on the
`active region;
`
`[1c] a gate electrode formed on the gate
`insulating film;
`[1d] source/drain regions formed in regions
`of the active region located on both sides of
`the gate electrode; and
`[1e] a silicon nitride film formed over from
`side surfaces of the gate electrode to upper
`surfaces of the source/drain regions,
`wherein:
`[1f] the silicon nitride film is not formed on
`an upper surface of the gate electrode, and
`[1g] the gate electrode protrudes upward
`from a surface level of parts of the silicon
`
`Igarashi
`[0002], [0117],
`Fig. 12
`
`[0044], [0045],
`[0068], [0112],
`Fig. 12
`[0020], [0021],
`[0044], [0134],
`Fig. 12
`[0044], Fig. 12
`
`[0044], Fig. 12
`
`[0047-0048],
`[0117-0118], Fig.
`12
`
`[0117-0118], Fig.
`12
`[0117-0118], Fig.
`12
`
`23
`
`Woerlee
`
`
`2:61-64, 4:66-
`5:5, Fig. 13,
`claim 1
`
`
`
`
`
`
`
`
`
`
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`

`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`Igarashi
`Woerlee
`
`’501 Patent Claim 1
`nitride film located at both side surfaces of
`the gate electrode.
`
`
`a)
`Claim 1 – Preamble (element [1p])
`The preamble of claim 1 recites “[a] semiconductor device, comprising a
`
`MISFET, wherein the MISFET includes.” (’501 patent, claim 1 (Ex-1001).)
`
`Igarashi discloses the preamble. (Shanfield Decl. ¶61 (Ex-1002).)
`
`For example, Igarashi discloses: “The present invention relates to a
`
`semiconductor device, and a method for manufacturing the semiconductor device,
`
`specifically to the gate structure of an MOS transistor and the contact structure
`
`that contains gate wirings and LIC (local interconnect).” (Igarashi at [0002] (Ex-
`
`1004).)4 A metal–oxide–semiconductor (MOS) transistor is a type of MISFET
`
`where the insulator is an oxide. (E.g., Shimizu at 59 (“A MISFET having a gate
`
`insulating film made of a silicon oxide film is usually called a MOSFET (Metal
`
`Oxide Semiconductor Field Effect Transistor).”) (Ex-1009).) Thus, by disclosing a
`
`MOS transistor, Igarashi discloses a MISFET. (Shanfield Decl. ¶62 (Ex-1002).)
`
`Therefore, Igarashi discloses the preamble. (Shanfield Decl. ¶63 (Ex-
`
`1002).)
`
`b)
`Claim 1 – Active Region (element [1a])
`
`4 All highlighting (bold and italicized) is added unless otherwise noted.
`
`24
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`Claim 1 recites “an active region made of a semiconductor substrate.” (’501
`
`patent, claim 1 (Ex-1001).) Igarashi in view of Woerlee discloses this limitation.
`
`(Shanfield Decl. ¶64 (Ex-1002).)
`
`For example, Igarashi discloses a “semiconductor substrate 1,” as illustrated
`
`in Fig. 12:
`
`
`
`(Igarashi at Fig. 12 (Ex-1004); see also, e.g., id. at [0044]-[0045], [0112]
`
`(discussing the “semiconductor substrate 1”).) (Shanfield Decl. ¶65 (Ex-1002).)
`
`A POSITA would have understood that Igarashi discloses an active region
`
`made of the semiconductor substrate 1 because Igarashi discloses: “First, an
`
`insulating film for isolating elements is formed on a silicon semiconductor
`
`substrate 1. Element isolation is performed using methods such as the LOCOS
`
`method or the trench method. Thereafter, ion implantation is performed to the
`
`active element region for forming the well and controlling the threshold value.”
`
`(Igarashi at [0068] (Ex-1004).) That is, Igarashi discloses an “active region made
`
`25
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`U.S. Patent 7,893,501
`Petition for Inter Partes Review
`of the semiconductor subst